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11 Threads found on edaboard.com: Inductor Ibm
Hi there, in my circuit I'm using inductors of ibm-130nm (cmos8rf) with M1 ground-plane. When instantiating inductors we can select internal connection o external connection. For what I understand, internal connection should be used when one of the terminals is connected to an AC ground potential, which is my case. I supposed that the layout (...)
Hi, I am using ibm 7RF pdk for my project. For the inductor I am getting this error that the ground needs to be connected to the bulk. But in the layout, there is no bulk to connect to the ground. The screenshots are attached. Can anyone please help? Thanks, Alarka. 9651896519
This is easy. Do you have the layout in Cadence or as GDSII? Here is a video that shows how to import the inductor GDSII layout into Sonnet and analyze: Dr. Mühlhaus Consulting & Software GmbH ? Sonnet Tutorial Videos -> Sonnet inductor Flow with GDSII Data Do you have the process te
When I ran LVS, the schematic and the layout were matched. However, when I ran XRC, they were unmatched. There are some property errors as follows. PROPERTY ERRORS DISC# LAYOUT _______________________________SOURCE_____________ERROR ************************************************************************************************************
Hi all, I was designing a circuit, having an inductor, in cadence virtuoso with ibm 90nm pdk. inductors of this pdk have optional center taps. However, I do not need the center tap. So, I unchecked the 'include centertap wire?' option in the create instance box both in schematics and in layout. It worked for the pcells of the layout
Hi i am designing an LNA on ibm 130nm and cannot decide which capacitor,inductor or resistor to take for my LNA .I have to work for 2.4 GHz.Ifsomebody knows it.Please help me for it. Also tell me what is meant if its written that this capacitor is availble withBEOL metallizatin only. Thnax
Hello All, This is my first post to edaboard. i hope i would be welcome here. i have just started doing LVS using cms9flp on cadence Assura platform. i am having a problem performing LVS of inductors(symindp). inductor symbols has 3 terminals (input output and substrate) which are used for simulation but the pcell for layout only has 2 termin
Hello, I am in confusion about the symmetric inductor of ibm cms9flp. When I use it in my layout created by pcell, then a square sized box appears only with a blinking message -"unsupported stack", until the 'default' key is clicked in the 'create instance' box. When the 'default' is clicked, then the 'spiral metalization' field of t
When I place the layout of inductor(simindp) from IMB 9rf process in Virtuoso, it always gave me some error like the following: *error* eval: undefined function - AMSRound *Warning* Unable to determin library property "metals" Then no other component can be placed. What causes this problem? Thank you.
Hi guys, I'm new to the spiral inductor design. I will work on spiral inductor modelling in ibm 0.18um process. Please suggest me any papers or reference that i can refer to before the design in ibm model. Thanks, suria
Hello More info need (1) Current = ? (2) Vdd = ? (3) matching inductor external or on-chip?