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adc to fpga interface
hi, i am working on the topic adc to fpga interface, i am using 1674adc n epm7160sfpga. can u send me the vhdl coding for the same....
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Nov 2009 5:20 :: sudhirkv :: Replies: 2 :: Views: 81
sbc (embedded systems) with linux
first of all hello...i hope im not asking something that is already answerd :pwhat iam about to ask is for a project that intents to make a system to monitor sensors and activate some devices remotely...the project is to built a platform that monitor...
Embedded Systems and Real-Time OS :: 20 Nov 2009 13:45 :: jnash41 :: Replies: 5 :: Views: 327
new ethernet development board, open-source
i have released my new version of my fpga ethernet development board. its all open-source, but i am shipping units to those interested in buying assembled versions. detailed info is located here:http://via.dynalias.orga feature list (taken from the w...
PLD, SPLD, GAL, CPLD, FPGA Design :: 20 Nov 2009 6:06 :: pini_1 :: Replies: 9 :: Views: 1434
how to interface adc & fpga( board design) :?:
hello folks, i am a newbie in board designing, i need help in understanding how to interconnect or interface an adc with an fpga (spartan 3a dsp chip).i dont have any idea as to how it is done..please can any body give me relavent information or sit...
Professional Hardware and Electronics Design :: 18 Nov 2009 17:27 :: barath_87 :: Replies: 1 :: Views: 69
which fpga board fits this requirement?
higher spec than the digilent nexys 2-1200 in terms of fpga chip, has some sram/sdram and flash for data storage as well. some adc/dac and some text/number display, i also need high speed data interface which can connect to pc for data transfer and c...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Sep 2009 15:41 :: kel8157 :: Replies: 2 :: Views: 222
giant full color led display
hi for all,i need info about large full color (rgb) led display, something like display used on futbool or tenis games,where i can buy this large panel?have someone experience on this field,best regards...
Microcontrollers :: 11 Sep 2009 18:10 :: prusanoff :: Replies: 68 :: Views: 11284
spi design in fpga for adc interface
hi i need to design an spi master (which sits in fpga ) to communicate with the (16-bit, 100 ksps/200 ksps bicmos ad977/ad977a)a/d converter of analog devices.can anyone tell me how to proceed?thank you...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07 Sep 2009 10:51 :: palai_santosh :: Replies: 1 :: Views: 288
interface circuit to tcd1304
i have question regarding the interface to the tcd1304 toshiba linear array ccd.where do i turn on the adc?how is the integration time controlled?which signal clears out the reading?anyone had experienece with this linear array?thanksahgu...
Analog Circuit Design :: 27 Aug 2009 10:12 :: yarosvet :: Replies: 2 :: Views: 1584
digital oscilloscope project
hii m studying possibilities to make a digital oscilloscope for pc, with onboard ram to memorize samples.i have several questions : => wich bus is the easier to use (hard and driver for linux/windows) : pci, usb or ieee1394=> i though about using man...
Hobby Circuits and Small Projects Problems :: 03 Jul 2009 12:05 :: millwood :: Replies: 474 :: Views: 271849
sar adc 10bit parallel to cpld i2c
hello . any one can provide example using verilog to interface 10 bit sar adc parallel out to cpld/fpga and out put i2c data ?thx ....
PLD, SPLD, GAL, CPLD, FPGA Design :: 19 Jun 2009 11:42 :: wls :: Replies: 0 :: Views: 180
fpga input - making and interfacing 1 bit adc for an fpga
hi guys, i have an 12v analog signal that i want to convert to 1 bit digital and feed to an fpga.(1) how do i make a 1 bit adc for an fpga(2) how do i interface it to the fpga. any references would be helpfulthanks...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 May 2009 15:31 :: roddyalan :: Replies: 0 :: Views: 201
help getting started in cpld fpga design
ve searched the net and don;t know were to start to learn cpld fpga. i have myna books but i lack a development board. please does anyone know a cheap one. i want to play with pci and pci express to interface to high speed adc and micro controller....
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Apr 2009 11:10 :: timi :: Replies: 2 :: Views: 330
need info regarding audio video for fpga
hi every body, i am a recent college grad.. i am at basic level of understanding.. presently our application is to take 4 video and 2 audio inputs and do processing in an fpga.. so actually i wanted to know mainly 1) which fpga supports both audio an...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Feb 2009 5:44 :: pradeepkumar481 :: Replies: 13 :: Views: 717
transfer data from a adc channel to pc via pci interface
dear all, i am new to the dsp on fpga. i have a nallatach xtremedsp development kit with virtex 4 card. i would like to read data from a adc channel and transfer it via pci interface to my pc. i am thinking about implemeting it using a simulink model...
Digital Signal Processing :: 18 Nov 2008 1:49 :: xilinxgirl :: Replies: 0 :: Views: 171
read data from a adc channel to pc via pci on xtemedsp kit
dear all,i am new to the dsp on fpga.i have a nallatach xtremedsp development kit with virtex 4 card.i would like to read data from a adc channel and transfer it via pci interface to my pc.i am thinking about implemeting it using a simulink model.doe...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Nov 2008 1:47 :: xilinxgirl :: Replies: 0 :: Views: 150
sensor interfacing to a xinlinx spartan 3
hi, i need to connect a temperature sensor and a pressure sensor to a spartan 3 fpga board.can anyone suggest some senors that can be inferfaced to this?im not sure on what the spec of the sensors should be for this application........
PLD, SPLD, GAL, CPLD, FPGA Design :: 06 Nov 2008 19:52 :: sht11help :: Replies: 6 :: Views: 597
interfacing with accelerometer
i would like to create an interface between my accelerometer and an embedded computer. the accelerometer is of this type:- measurement specialities ach-01: http://www.meas-spec.com/vibration/documents/datasheets/oem_ach01.pdfthe embedded computer is ...
Analog Circuit Design :: 12 Sep 2008 22:25 :: sorenriis :: Replies: 22 :: Views: 900
oscilloscope
hi, to every body i am dreaming of making a portable oscilloscope with graphical lcd and a micro controller not yet decided wich micro controller. can any one suggest for a 40mhz 12 bit resalution which controller should i use and at what sp...
Microcontrollers :: 27 Jul 2008 5:50 :: tohbas :: Replies: 7 :: Views: 849
vhdl code for connecting adc to fpga
dear friends,im learning vhdl .i want an example of vhdl code for connecting a flash adcto the fpga.thanks a lot...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Jun 2008 11:35 :: missbirdie :: Replies: 7 :: Views: 2802
ndt basic using fpga
hi all,,i want a litel help in making my project on fpga ,,, i m planing to make a samall scale model of ndt(non distructive testing) here i giving general oveview,,i will take a anolog signal from sensonr thn give it to the adc ,,, i want to store 1...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Apr 2008 1:06 :: davr :: Replies: 7 :: Views: 267
interfacing very high frequency adc board question
hi,i have an ads5474 evaluation board. acd is expected to work up to 400 msmps.and i use another fpga board (virtex% sx95) with a high speed lvds connector to interface the evaluation board. i also have an appropriate cable which according to datashe...
Analog Circuit Design :: 06 Apr 2008 19:49 :: vahidkh6222 :: Replies: 10 :: Views: 456
fpga and adc intefacing
want to know about fpga and adc interfacing?is this interfacing differs with the fpga vendor or any standard interfacing is there???thanx in advance.:d...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Mar 2008 9:45 :: xtcx :: Replies: 6 :: Views: 596
verilog microwire module
robably made the confusion worse :cry:.it seemed simple enough when i first looked at it but after a few hours of coding and trying to reverse engineer spi examples i come for help.i need a microwire interface, only master mode.misosclkconversion sta...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Feb 2008 14:47 :: Rob B :: Replies: 4 :: Views: 942
zero if vs low if
which one is better, zero-if or low-if. my problem is that for zero-if i need to use quadrature demodulators with dual channel adcs where as for a low-if a single adc can be used but digital down conversion must be performed which consumes logic reso...
RF, Microwave, Antennas and Optics :: 24 Jan 2008 3:54 :: RFDave :: Replies: 11 :: Views: 935
spi interface
hi all,i am using several devices (adc, dac and sram) which all use the spi interface. now i know i can connect these devices to my fpga and have the devices all run as slaves and one master(fpga). howeverfrom doing some background reading i have not...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10 Dec 2007 2:02 :: alzomor :: Replies: 3 :: Views: 426
using fpga to control adc and dac
hi all,about to undergo a little project and i was wandering if anyone could provide a few answers to my questions please.i am going to use an fpga to control an adc to convert an audio signal and store the data into memory. then i am going to use th...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Oct 2007 16:10 :: Old Nick :: Replies: 6 :: Views: 918
adc
hi friends,,i need code vhdl code or verilog code for adc ans dac please help me ..with thanks raj.....
PLD, SPLD, GAL, CPLD, FPGA Design :: 08 Sep 2007 22:16 :: smoked :: Replies: 2 :: Views: 306
correct io standard for 125mhz signal..
hi...i am designing high speed transceiver on pcb, which has adc signals which are interfaced to spartan 3a fpga at bank 3 by lvpecl standard. this interface works at 250mhz.signals from the bank 1 of this spartan 3a fpga are interfaced to i/o of spa...
PLD, SPLD, GAL, CPLD, FPGA Design :: 20 Aug 2007 9:15 :: mta97e :: Replies: 5 :: Views: 1113
help in designing digital thermomter
plzzzzzzzzz someone give me the guideline in designing a digital thermometer in verilog and how to implement it also plz give me the source code........
PLD, SPLD, GAL, CPLD, FPGA Design :: 03 May 2007 23:14 :: mendozaulises :: Replies: 1 :: Views: 225
connect an adc to fpga
could anyone help me to find out how to connect an adc(ad9860) to fpga.thanks!...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03 May 2007 3:50 :: assabiq :: Replies: 3 :: Views: 387
why analog
hello alli want to know what an analog designer doalmost all our life now is digital .digital systems are everywhereso why we need analog design and what it is used forthanks...
Electronic Elementary Questions :: 22 Apr 2007 13:28 :: emadi :: Replies: 6 :: Views: 402
adc selection help needed!
yone, i want to sample signals from the electric guitar and make i talk to a digital fpga board... what adc type and resolution would be a good choice?? also what is the best way to interface it..? any help would be greatly apprecia...
Digital Signal Processing :: 10 Mar 2007 7:52 :: wiztronix :: Replies: 9 :: Views: 249
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implement a voice meter on fpga
hail, we are looking for a way to implement an analogue anudio signal from a ad into a fpga, and we need to detect the voice level / db level of that audio?? anyone has ecperience on this, who can guide us to the right direction / algorithm on this ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 28 Feb 2007 11:45 :: compvision :: Replies: 1 :: Views: 141
converting adc samples to an appropriate fixed point format
hi , i have a system with an adc that recieves an analog signal that may have values in the 0 - 5 v range. the signal must be filtered in the digital domain. my question is how should the 8 bit samples be converted to match the format of the filter c...
Digital Signal Processing :: 23 Oct 2006 10:39 :: echo47 :: Replies: 12 :: Views: 441
why use fpga not cpld to interface high speed adc
hi, guys,having seen some examples which use fpga to interface high speed adc, i just would like to know why not use cpld to the same job. what is the advantage of fpga over cpld in this job. thanks.karl...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Jul 2006 5:29 :: JeannieGumble :: Replies: 2 :: Views: 339
how to interfacing adc tc7109cpl with fga?
hi,can you help me for something? i want to use the fpga interface for the dual-slope a/d converter using tc7109cpl my analog input is sine wave signal so... how is design vhdl code to read the amplitute of sine signal? can you suggest me? th...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02 Jul 2006 20:28 :: EDALIST :: Replies: 1 :: Views: 156
general question (datasheets and interfacing)
lets say i want to interface an adc with a microcontroller. what values in the datasheet do i need to make sure that no ic will get damaged. thx...
Microcontrollers :: 16 May 2006 10:14 :: kender :: Replies: 3 :: Views: 162
adc-fpga interface
hi, this is my first time connecting an external component to the fpga. the adcs output can be 5 v .. im using digilent spartan 3 board, where vcco is connected to 3.3 v .. should i interface the adc to it direcrly since the fpga has internal clamp ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03 Nov 2005 18:53 :: echo47 :: Replies: 1 :: Views: 279
dsp with fpga
does anyone have any reference designs of a dsp implemented on an fpga?the kind of information im looking for involves schematics of interfacing various componenets, primarily adc. followed by how the hdl blocks come together to control the adc obtai...
PLD, SPLD, GAL, CPLD, FPGA Design :: 01 May 2005 23:02 :: echo47 :: Replies: 18 :: Views: 3434
short range wireless video
hi everybody,i need to design a short range (4-5 meters) wireless connection from a camera to an 1/2vga color lcd display. which is the best way? analog transmission? digital with compression? bluetooth?thank you for your suggestions!...
Professional Hardware and Electronics Design :: 26 Apr 2005 4:15 :: EEHardware :: Replies: 9 :: Views: 1059
spartan-ii vs spartan-3 questions
ok, i have searched the archives and i can’t seem to find much discussion about the advantages/disadvantages of the xilinx spartan-ii vs the spartan-3. i have read through the documentation of both devices and am left a bit more confused than when i...
PLD, SPLD, GAL, CPLD, FPGA Design :: 01 Dec 2004 7:52 :: Mazi3 :: Replies: 1 :: Views: 336
question about adc and dac
say that can implemetion adc or dav with fpga or cpld by vhdl. it is right or wrong ? if it is right, anyone give me some link, documents or source code about this problem. i am using fpga and cpld chip of xilinx and use ise 6.1thank so much. bye...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Jun 2004 11:51 :: jay_ec_engg :: Replies: 12 :: Views: 1974
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