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14 Threads found on edaboard.com: Interpolating Adc
Does anyone have Folding and interpolating adc behavior model in simulink or give me some suggestion?Thanks for your help!!
Hi In a typical folding & interpolating architecture, there are two main parts: the Coarse Quantizer and the Fine Quantizer. In all the papers that i have seen the Coarse Quantizer is of 2Bits and the rest of bits(4 up to 6) are related with the Fine Quantizer. In this way, adcs with bit numbers up to 8 are implemented. My question is why the Co
Hello friends If anyone has information regarding the design of Folding and Interpolation adc please upload the documents. Especially if anyone has Thesis related to Folding and interpolating adc.. Plz upload it. Advanced Thanks Shady205
Hello, I have just simulated my folding and interpolating adc. The resolution of that adc is 8 bit with 1.4v full scale input. 1 LSB is about 5.5mV. After i simulated it staticaly(without frequency). The digital output only changed when Vin is 6.9mV or more. Theoritically it will changed at 5.5mV or more. Somehow i found that the (...)
Hi, I have just discovered something strange with my 8-bit Folding and interpolating adc when the sampling rate is higher than 30 MHz. As you can see in attachment, when the input signal (V(vin)) 0 V (just ignore 1 V because it is the DC offset) the output of my adc showed '00111111'. It must be '00000000'. Does anyone experience this (...)
I have a different view for the above question.... In some architecture odd no of bits are possible (like simple flash, 2step flash, Folding-interpolating etc.).....even some times while doing the design....people may find that the resolution coming is 7bit or 9 bit...but they specify one bit lower ...with better spec..... What I think is that...
Dear Friends, Recently, I studied about Folding & interpolating adcs. I didn't undrestand how they actually quantize the analog signal? can anybody give me a clear guidance about how it works, any example or good paper that would explain the exact operation of it? I do appreciate you. Regards, Samaneh
hallo, Can i use the reference ladder for folding amplifier for coarse converter too? Or should i use another reference ladder just for coarse converter? I want to design 8-bit Folding and interpolating Converter.3 MSB and 5 LSB. the second one, my folding factor is 8 and i have 4 Folding Block to generate 4 folding signals. How to get the di
hello, I'm finishing with my thesis soon. My thesis is design of folding and interpolating adc. does someone has the eBook as guide to write my thesis?
Hi, I've just simulated a folding & interpolating adc and found a glitch around 0.5 V after an EX-OR logic in my digital part. In the attachment, V(c07) and V(c23) are the input and V(out_07_23) is the output of EX-OR. As you can see in waveform, there is a glitch of 0.5 V(at time 0.3 us) of the output of EX-OR.I'm wondering how this happened be
i'm simulating a 8-bit Folding and interpolating adc and just found out that its SFDR is at 60dB at sampling rate of 25MHz. When i increase the sampling rate to 40MHz the SFDR of my adc degrades to 30dB. Does anyone have the idea which main factors cause this? Thanks in advanced
Hi, i have just finished my diplom(Dipl. Ing(FH)) study in electrical engineering in germany. I have a good knowledge of CMOS IC analog design and my final thesis was design of folding and interpolating adc. I am fresh graduate and i found it tough to get the job in Ic design since all positions require at least 3 yr experience. Can someone give
WaveLab is a collection of Matlab functions that have been used by the authors and collaborators to implement a variety of computational algorithms related to wavelet analysis. A partial list of the techniques made available: orthogonal wavelet transforms, biorthogonal wavelet transforms, translation-invariant wavelets, interpolating wavel
hi everybody I have two questions. 1) i am designing a s/h amplifier for 6 bit adc at 1 ghz sampling frequency. i want know which op-amp i can use to obtain this high bw and resolution. 2) i want to know if it is a good idea to convert the fully differential output of s/h to single-ended before giving it to adc. the adc is (...)