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Interpolating Adc

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9 Threads found on edaboard.com: Interpolating Adc
sir i am doing 8 Bit folding 8 interpolating adc in cadence. plz tell me how to calculate INL,DNL factor using calculator option of cadence tool. is there any other way to calculate INL,DNL factor. How to calculate noise margin and SFDR ?
Hi, i have just finished my diplom(Dipl. Ing(FH)) study in electrical engineering in germany. I have a good knowledge of CMOS IC analog design and my final thesis was design of folding and interpolating adc. I am fresh graduate and i found it tough to get the job in Ic design since all positions require at least 3 yr experience. Can someone give
Hello, I have just simulated my folding and interpolating adc. The resolution of that adc is 8 bit with 1.4v full scale input. 1 LSB is about 5.5mV. After i simulated it staticaly(without frequency). The digital output only changed when Vin is 6.9mV or more. Theoritically it will changed at 5.5mV or more. Somehow i found that the (...)
hello, I'm finishing with my thesis soon. My thesis is design of folding and interpolating adc. does someone has the eBook as guide to write my thesis?
hallo, Can i use the reference ladder for folding amplifier for coarse converter too? Or should i use another reference ladder just for coarse converter? I want to design 8-bit Folding and interpolating Converter.3 MSB and 5 LSB. the second one, my folding factor is 8 and i have 4 Folding Block to generate 4 folding signals. How to get the di
Does anyone have Folding and interpolating adc behavior model in simulink or give me some suggestion?Thanks for your help!!
Dear Friends, Recently, I studied about Folding & interpolating adcs. I didn't undrestand how they actually quantize the analog signal? can anybody give me a clear guidance about how it works, any example or good paper that would explain the exact operation of it? I do appreciate you. Regards, Samaneh
Hello friends If anyone has information regarding the design of Folding and Interpolation adc please upload the documents. Especially if anyone has Thesis related to Folding and interpolating adc.. Plz upload it. Advanced Thanks Shady205
Hi In a typical folding & interpolating architecture, there are two main parts: the Coarse Quantizer and the Fine Quantizer. In all the papers that i have seen the Coarse Quantizer is of 2Bits and the rest of bits(4 up to 6) are related with the Fine Quantizer. In this way, adcs with bit numbers up to 8 are implemented. My question is why the Co