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34 Threads found on edaboard.com: Interpolation Adc
i want to buy a folding and interpolation adc monolithic, if anyone kown how where can buy one ,please give a help.many thanks
Hello all, I am now designing a clock driver for a folding interpolation adc. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver?? Thanks for your help, chemaphy
Hello friends If anyone has information regarding the design of Folding and interpolation adc please upload the documents. Especially if anyone has Thesis related to Folding and Interpolating adc.. Plz upload it. Advanced Thanks Shady205
Can somebody helps me out to know the pros & cons of Folding & interpolation adcs compare to pipeline and Flash adc OR suggest some good material for ? Thanks in advance...
my project requires to design folding and interpolation adc can you help me
I designed 7bit Folding interpolation adc with 1.2V 65nm 1P6M process. and I'm going to prepare mesurment. I used input track and hold amplifier. this picture show measurement setup Why used 'Bias T' ??
Hallo, How to determine the value of interpolation resistors for Folding and interpolation adc? Thx in advance
hi, I have just done a DC sweep for my folding and interpolation adc. The top pane show the four folding signals generated by the four folding blocks. The below pane shows the 32 signals as a result of interpolation of the 4 folding signals. I have a problem that there are some wrong with the interpolated signalsat around 1.0 v of (...)
it is 4 fold and 2 interpolation with no t/h. the folding pattern is ok and also interpolation but the comparator outputs arent showing the thermometer code as expected. comparators are separately working there is no problem with it. i want to know where i am going wrong also how to test the circuit. please help me in this becauz it i
Bandpass sampling is best approach to have reduced power consumptation for the adc implementation. I think most adc implementation independend from the architecture (Flash, Folding, interpolation, Multistage-Subranging,..) come down to about 150-500fJ/decisionstep. So a 10bit/1GS/s have (2^10-1)*1e9Hz*150fJ=153.5mW These results (...)
Hello all, I am now designing a clock driver for a folding interpolation adc. The output of the clock driver is connect to 32 comparators. The clock signal needs to be generated is 2GHz. Does anyone have experience with designing such a high speed clock driver?? Thanks for your help, chemaphy
Hi Everyone, I have just designed a 8-bit folding interpolation adc. When I simulate my adc, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the adc. Can anyone who has experience with (...)
Hello friends, Can anyone tell me how to measure the Clockfeedthrough of an adc(Folding & interpolation) and A Switched Capacitor Low Pass Filter (5th Order Butterworth) Thanks in Advance Shady205
Hi, I am trying to design an adc with 8bit 2GS/s specifications with minimum power consumption. The process is 0.13um BiCMOS. I am trying to look for papers and found some groups used folding+interpolation to achieve >1G with 8bits resolution. Is F+I the only possible way to achieve the specs or there are better ways to do it? Do anyone have some r
You are experiencing some "numerical noise" due to the interpolation between two simulation steps, i.e. your 2048 points do not always fall on one of the points calculated by the simulator. So, the 0.01ns simulation is probably the correct one.
hi i have a problem , i work with dspic30f2010 , i should convert an analog signal to digital so i use the adc of the dspic but after that i should treat the result of the conversion with a program of interpolation then transfer it with the can bus; my problem is that i read the datasheet, but i didn\'t find a solution , to do the program of inter
hallo, In the attachment(taken IEEE article) there are 12 reference voltages are paired with input signal. The article said, 1.eight differential pairs are needed for a folding a signal 2.two additional differential amplifiers(with ref9 and ref10) are used for the extension of the folding signals for the low and high side of the input range to
hi, I read the article that folding&interpolation adc facing frequency multiplication problem in adc processing. And S/H can eliminate this problem. Can anyone explain those ? Why frequency multiplicaiton happens ? and why S/H can eliminate it ? best
why use folding adc architecture ?? flash adc -> < 6bit and much more power flash + interpolation -> 8 bit pipeline adc --> can reach high bit high speed I think many design use pipeline adc for Scaler (as I know is 165M 10bit pipeline adc ..)
Hi Circuit_seller I have not used AIC23 chip. I just brawsed the datasheet for you and in my opinion the normalized frquency should be interpred like this. The '3' should not be interpred as a pi The interpolation filter in the adc works at the frequency much higer then the input sampling rate (44.1khz for example). In my poinion you
In speech,there is one king of compression named "waveform interpolation". Will it be popular in the future? thanks .
let me sum up some basic rules: - more pixel (higher resolution) you have, smaller are the pixels or bigger is the sensor... and - smaller are the pixel size, worst is the image ( smaller light to current/voltage conversion ratio : SNR !) - bigger is the sensor, more expensive is the system (smaller yield, large lenses...) so, basically, t
hi suppose i go for cross connection of diff pairs then what shud be the separation of neighbouring voltage references to have good interpolation. just for example take a 6 bit folding adc 3/3 then for 8 folding factor what shud be the slope, the value of resistance? i have a folding amplifer with f=8 but the problem is there is a tapering the
hi alzhrani, The demosaic algorthem is you want. You can search google by "demosaic" or "color interpolation". The following is weblink, I search from google. Sincerely, Jarod
your answer is decimation and interpolation
Thesis: An 8Bit 150MHz CMOS AD Converter This dissertation presents an 8-bit, 5-stage interleaved and pipelined adc that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of ?sliding interpolation? is proposed to obviate the nee
hi, how to use the cell fourier in analogLib of cadence I also confront this problem at the setup of this cell when I test my adc design @ Cadence "Model name": for which model? or as the filter transfer function?? "Fundamental Frequency": mean the transient frequency or the sampling frequency??
F/I adc work exactly like a flash. You have comparators and a resisitive string. You comparators have couple of stages of low gain preamps. One preamp/comparator generates one zero crossing (zx) at the referece value, because you look at Vin-Vref. Now imagine you can actally compbine severeal preamps and generate more zx in one "folding amplifier
The change in voltage should be proportional to the change in temperature Because the divider output voltage is proportional to the ratio Rx/(Rx + R0), it's not linear in Rx respectively temperature. In addition the non-linear Pt characteristic has to be considered, as you mentioned. Nevertheless, using a simple ratiometric RTD "sig
This code implements (some kind of) interpolation/value adjust: a=5*adc_val; b=a/255; c= 8.4375 + b; d= c*1500; e = 149-c; f = d/e; g= (f-100); //stright line equation h =g/0.22; h=h+10; I assume you get the value of the temp sensor in "adc_val". After the execution of this piece of code you get the temper
It's a linear interpolation, not accurate enough for the large temperature range. You should use a polynomial or a multi-point linear interpolation.
Hello! Let's assume that we have simple FMCW distance measurement system with linear frequency sweep from F1 to F2. Sweep duration is T. adc frequency is enough to digitize 128 points for each sweep duration T. Then we do some windowing and perform an FFT. For example 1024pt FFT (yes, i know about 128 points and interpolation, but it is from real
FFT's have a great number of uses. Generate quadrature signals from single input for Hilbert transform AM detector. Rolling butterfly interpolation of adc sampled waveforms to fill in points between adc sample points. Digital oscilloscope use this to reconstruct sampled waveform (known at sinX/X interpolation). Just (...)
Not sure about specifically what kind of resampling topic you are looking at. Resample can refer to aligning signals that need to be syncronized. For example if you have two independent async digitized audio signal that need to be combined into a single data stream you need to resample one or both to get symbol/bit alignment to allow combining