71 Threads found on edaboard.com: Inverter Rise Time
Both n-mos and p-mos widths are minimum widths(that means we cannot folde it to decrease the rise time ) then
To maintain the equal rise time and fall time to the inverter What are the steps your going to tack ?
ASIC Design Methodologies and Tools (Digital) :: 24.05.2006 04:20 :: p.sivakumar :: Replies: 12 :: Views: 4174
by source/sink current calibration or use current mirror to bias the output inverter stage
Other Design :: 05.03.2007 12:15 :: email@example.com :: Replies: 6 :: Views: 6631
i am working clock circuit with cmos logic gate,i.e,inverter,nand2,nand3,nor2,and the high level is 1.2v with low level 0v.
i want to set the rise time and fall time of them to a equal value.
so i short the input of them and give a vdc input and run the dc analysis while sweeping the input from 0 to 1.2v.
Analog IC Design and Layout :: 26.03.2010 23:07 :: urian :: Replies: 2 :: Views: 2822
Because of the (W/L) which is the width over the length factor. You are changing P MOS width rite? But the Kr changes. It will change the voltage transfer characteristic of the inverter. From there only,you can see the fall time and rise time.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.09.2010 05:09 :: john blue :: Replies: 5 :: Views: 860
I designed an inverter in TSMC 0.18um process. NMOS is 900nm/200nm X2. it can contain 2 contacts. and PMOS is 2.7um/200nm X2. So the width of PMOS is three time than NMOS. this inverter drive 10fF capacitor and an another inverter. .
rise time and fall time are equal (...)
ASIC Design Methodologies and Tools (Digital) :: 26.09.2011 22:35 :: wzhlove2003 :: Replies: 1 :: Views: 582
rise time is a function in both Ron of the transistor as well as CL
As the technology scales, the parasitic capacitance of the inverter (basic digital block for eg.) goes down.
However, the on-resistance does not scale on the same ladder....
Analog IC Design and Layout :: 07.06.2012 07:30 :: AmrZohny :: Replies: 2 :: Views: 401
Can you tell me why we should equate the rise time and fall time of a standard cell ?
Like a inverter, we usually draw a pMos 2 times wider than nMos to ensure the rise time is matching the fall time.
ASIC Design Methodologies and Tools (Digital) :: 06.06.2012 22:16 :: owen_li :: Replies: 1 :: Views: 388
in my opinion,normally the propagation delay and the rise/fall time are two parameters that have no directly relation, the propagation delay is for speed, while the rise/fall time is for signal quality, that the propagation delay is bad does not mean the rise/fall time is bad.
but for (...)
ASIC Design Methodologies and Tools (Digital) :: 15.11.2005 19:56 :: tarkyss :: Replies: 7 :: Views: 2784
There is no need actually to set inverter's switch point to VDD/2.
Electronic Elementary Questions :: 21.11.2006 23:01 :: adsl :: Replies: 6 :: Views: 681
Can anybody give me the complete derivation of rise and fall time equations of a cmos inverter?
Analog IC Design and Layout :: 24.02.2007 17:18 :: engrbabarmansoor :: Replies: 1 :: Views: 3329
it is often said in the inverter PMOS should be sized 2 or 3 times larger than NMOS, because PMOS has low mobility.----the inverter threshold voltage can be shifted to the middle, and the inverter is more symmetrical in terms of transition times, right?
In my circuit, when I size the PMOS and NMOS the (...)
Analog IC Design and Layout :: 16.05.2007 13:02 :: katrin :: Replies: 23 :: Views: 11253
To get equal rise time and fall time, size the nmos and pmos inverters in the opposite ratio of their mobilities. (W/L)n/(W/L)p = (mobility)p / (mobility)n
ASIC Design Methodologies and Tools (Digital) :: 11.09.2007 20:11 :: itsthepip :: Replies: 6 :: Views: 1837
i am using inverter in my project....i am using 130 nm tech...
and i am getting spikes...please help me in reducing the spikes in
the output of the inverter...
ASIC Design Methodologies and Tools (Digital) :: 02.12.2007 01:24 :: prasadel06 :: Replies: 7 :: Views: 859
I assume you are referring to a switched capacitor filter or a sigma delta circuit.
A rule of thumb is for the non-overlap time to be at least three times the rise time or the fall time (whichever is longer) of your buffer/inverter that you are using to drive the switches.
Analog IC Design and Layout :: 02.09.2008 22:14 :: hannerfherder :: Replies: 3 :: Views: 866
I have a Problem when connecting two digital components designed at the transistor level.
The firt module is supposed to controle the second module. When Used alone the rise/fall time of the output signals of the first module are perfect however when the 2 components are connected (output of module 1 to input of module 2) the rise (...)
Analog Circuit Design :: 28.02.2008 11:05 :: master_picengineer :: Replies: 5 :: Views: 780
To be accurate, it depends on the number of inverters you are having. Let us assume you have 'x' inverters.
You know f = 1/T. So the maximum operating frequency = 1/(5ns*n) = (200MHz/n).
So if you have 2 gates, the maximum operating frequency is 200MHz.
Hope you got the point. :)
Electronic Elementary Questions :: 20.07.2012 09:00 :: psurya1994 :: Replies: 4 :: Views: 521
I'm designing a CMOS inverter circuit.
Right side graph is output voltage.
My question is why is there a peaking at 1us, 2us, ...(yellow mark)
and how can i remove it?
Analog Circuit Design :: 10.09.2012 02:15 :: angbong :: Replies: 3 :: Views: 263
It is not the design task to have the Vth of the inverter in the middle of the supply voltage. The prior task is to guarantee symetric rise and fall times. So the dynamic is of more interst than the static case.
A symetric static (dc) transferfunction differs from symetric rise and fall times since there (...)
Analog IC Design and Layout :: 18.03.2005 08:20 :: eda4you :: Replies: 6 :: Views: 958
The NAND gate has two sereis NMOS transistors and two parallel PMOS transistors. So you cannot always obtain fall time= rise time.
However, if for an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = rise time. For the worst case (...)
Electronic Elementary Questions :: 21.03.2005 01:15 :: adel_48 :: Replies: 1 :: Views: 2318
I am designing a inverter driver to drive a 20-50pf capcitance. i use the
cascade of inverter structure (each is two times than the last one). But the delay
is too large to damage the timing.
So is there other method to do this things?
Added after 1 hours 16 minutes:
Analog Circuit Design :: 11.10.2005 09:18 :: gdhp :: Replies: 2 :: Views: 806
What I can think of is the fan-out is high. So the tool can put buffer, or use 2 inverters. Check if the first invertor only fanout to the second inverter (may be the first inverter also drive other logic).
Also, if you ask the tool the meet hold time, than this type of logic is expected.
ASIC Design Methodologies and Tools (Digital) :: 05.01.2006 14:24 :: leeenghan :: Replies: 4 :: Views: 585
In silicon, Mobility of electrons is around 3 times faster than holes.
If you take an inverter, fall time is quick and rise time is more. In order to overcome this problem, Pmos is usually made twice that of nmos. That is why they say NMOS is faster than PMOS.
ASIC Design Methodologies and Tools (Digital) :: 10.03.2006 02:57 :: carrot :: Replies: 5 :: Views: 2445
build your inverter and dummy load inverter, add test step source, run trasient simulation, measure for rise/fall time.
Analog IC Design and Layout :: 14.03.2006 22:54 :: qslazio :: Replies: 3 :: Views: 763
Please tell me how to calculate current in PMOS and NMOS of CMOS inverter.
the current depend on the load the inverter going to drive
according to the formula I= c* dv/dt
c= outout load
dv/dt= how fast the output voltage need to rise in a certain time, this depend on the speed requirement.
Analog IC Design and Layout :: 10.04.2006 04:49 :: surianova :: Replies: 3 :: Views: 2323
Technically speaking, it is easier to match the aspect ratio of PMOS and NMOS in CMOS inverters used in ring oscillator. Matching aspect ratio is necessary to make sure the rise time and fall time is correct. Matching aspect ratio in a differential amplifier is an entirely different level of difficulty because you also have (...)
RF, Microwave, Antennas and Optics :: 02.05.2006 06:12 :: SkyHigh :: Replies: 1 :: Views: 821
i only know inverter chains with resistors to generate pulses and delays
Analog IC Design and Layout :: 16.04.2007 04:30 :: strennor :: Replies: 2 :: Views: 863
If you are simulating the inverter
connect the output with the input (physically or virtually ) then try to adjust the aspect ration until the voltage of this point (input tied to the output) is equal to VDD/2
Then you have same strength PMOS and NMOS, it will keep the same input duty cycle if you use even number of successive inverters,
Analog IC Design and Layout :: 07.11.2007 05:27 :: rania_hassan :: Replies: 6 :: Views: 1175
hi, i wonder if anyone can help me with this "inverter delay measurement" problem i have.
Normally, textbooks define inverter propagation delay to be = RCln(2), which is the time interval between 50% change in input to 50% output change (CMIIW). Apparently, this formula is only good for very small input rise/fall (...)
ASIC Design Methodologies and Tools (Digital) :: 17.10.2007 14:15 :: irfansyah :: Replies: 1 :: Views: 869
Hi A.Anand Srinivasan,
Let consider a nand gate and you wanna determine the maximum frequency of it's inputs that support that gate. Suppose that this frequency is F. With such a freq the output signal gives good results but it has spikes. We know that inverter insertion resolves the problem however in introduces additional delay. Another solution
Analog IC Design and Layout :: 26.12.2007 03:35 :: master_picengineer :: Replies: 2 :: Views: 619
I want to test the delay of inverters from the lib by spectre.. So I added 1000 inverters serially .
Input is a long enough pulse like 100ns ,then make the plus come through the 1000 serial intverters. The output is an XOR of delayed and nondelayed input pulse...
here is the input and the vdd :
_vin (in 0) vsource dc=0 val0=0 val1=1.2 d
ASIC Design Methodologies and Tools (Digital) :: 30.08.2008 22:43 :: sheyang :: Replies: 5 :: Views: 565
I have a question about inverter design.
When designing inverter, usually (W/L)p is bigger than (W/L)n twice.
I know that's why kp is smaller than kn around 1/2.
When I extract kp,kn from my design model (0.18um),
it is kn=157u A/V^2 , kp=42u A/V^2.
Can I make a ratio (W/L)p and (W/L)n is 4:1 ?
in my case, which is right decision?
Analog IC Design and Layout :: 17.11.2009 19:26 :: k1gunner :: Replies: 4 :: Views: 725
lower metals are kept for nets connection that are not conducting heavy current.
top metals are for carrying heavy currents like clock,vdd,vss etc...
if we have wider metals in lower levels , you will face issues due to heavy capacitve effects of wide metals and biggest issue will be routing and die area.
for a small inverter output
ASIC Design Methodologies and Tools (Digital) :: 09.12.2009 23:59 :: ankitgarg0312 :: Replies: 5 :: Views: 1312
i do aplogize that i was really new here in this site... and for what i need i was asking about the parameters of the vpulse in pspice that needed to be applied as modulator in the 3-level diode clamped inverter...i did build the 3-level d.c.i. but when applying the vpulse on some switches things going not logic results and really crazy...i am in n
Power Electronics :: 24.02.2010 06:31 :: qais_abdulkareem :: Replies: 3 :: Views: 2461
Yes. For a given rise time, lower signal swing means slower slew (V/ns) which means the inverter input transistors' threshold voltages will take longer to hit, and that the input capacitance will take longer to charge.
ASIC Design Methodologies and Tools (Digital) :: 28.06.2010 22:19 :: randyest :: Replies: 3 :: Views: 593
Please help to find an best answer for following question:
Can I use inverter as level shifter? If no why?
Analog IC Design and Layout :: 26.07.2010 08:51 :: gangadharn :: Replies: 5 :: Views: 1614
you could use a gigabit logic inverter gate, capacitively couple the output to a short circuited transmission line. The gate provides a quick rise time, and the short circuited transmission line makes the pulse width narrow. Should work for a 3 Ghz mixer.
RF, Microwave, Antennas and Optics :: 18.10.2010 04:40 :: biff44 :: Replies: 2 :: Views: 504
Is this really needed ?
Would this really work ?
- A single transistor in a current source configuration and for the present signal polarity an inverter stage should basically do.
- The 10 k driver load resistance/Q3 gate capacitance sets a rise-time in a ?s order of magnitude, so you can't achieve 10 MHz. 115K can hopefully work.
Hobby Circuits and Small Projects Problems :: 30.10.2010 07:22 :: FvM :: Replies: 7 :: Views: 1534
That is the conventional way (putting decap between vdd and ground)to reduce the noise on the digital circuit. You had a question about the necessity of decoupling cap.
I would say that depends on:
1.the rise and fall time of you digital signals increases
2. The value supply and ground inductance.
3. How big is your digital circuit.
4. Does it
Digital communication :: 07.03.2011 09:03 :: Milad-D :: Replies: 1 :: Views: 564
Hi all ,
I need clarification on hold time of TSPC(+ve edge per my perception hold time for D=1 is zero(if we assume zero rise and fall times) and for D=1 it is delay of second inverter minus delay of first it
Analog IC Design and Layout :: 16.03.2011 12:48 :: Ravinder487 :: Replies: 0 :: Views: 896
You can simply imagine a capacitance between inverter in- and output.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.06.2011 03:50 :: FvM :: Replies: 3 :: Views: 546
I have this doubt, that to maintain the duty cycle we need all the buffers and inverters to be having the same rise and fall time. Am I right ?
ASIC Design Methodologies and Tools (Digital) :: 19.08.2011 03:18 :: pavanks :: Replies: 12 :: Views: 1246
Normally in inverter circuits mosfets fail when another phase is connected accidently by electricians
to the output of an inverter .This leads to all mosfets connected in parrelal in both half bridge to Blow. Normal overload protection circuit of the inverter don't work under these conditions. Some manufacturers claim as their (...)
Power Electronics :: 09.09.2011 09:17 :: spiba :: Replies: 43 :: Views: 3897
Logic IC's are made to change state of their output as quickly as possible. It becomes more important at fast data rates.
From my experiments it didn't matter how slowly or quickly the input crosses the threshold between lo and hi. I found I was unable to obtain a middle output.
This assumes the output is not loading the IC supply pins so muc
Electromagnetic Design and Simulation :: 29.09.2011 19:32 :: BradtheRad :: Replies: 1 :: Views: 674
In CMOS, PMOS is used as pull up device while NMOS is used as pull down. If you wants to have equal rise and fall time for a cell, you need to have equal pull up and pull down resistance. In PMOS majority carriers are holes while in NMOS majority carries are electrons. Electron mobility is nearly 2.5 times grater than holes. So PMOS is made (...)
ASIC Design Methodologies and Tools (Digital) :: 11.01.2012 02:21 :: yadavvlsi :: Replies: 3 :: Views: 493
Hello to all,
I'm not good at design in electronics but I became passionate about inverters. I found a logic operation of commercial grid inverter. I outlined in attachment my idea. It can be put into practice and if so worth the investment (cost compared to benefit)? I have not much time for
Electronic Elementary Questions :: 27.01.2012 13:18 :: vminga :: Replies: 3 :: Views: 265
I am a digital backend engineer, and have no much understanding about CMOS transistor.
I read a book these days and found it said "the resistance of pMos network should equate that of nMos network, in CMOS transistor".
like a inverter, the pMos should be nearly two times width than nMos, to make their resistance equal.
So, Can y
Analog Circuit Design :: 11.06.2012 02:46 :: owen_li :: Replies: 4 :: Views: 382
I tried using this formula to calculate rise and fall time in calculator , but the expression fails.Could anyone help me?
risetime(VT("/OUTPUT") M1 t M2 t 10 90)
Analog IC Design and Layout :: 11.01.2013 04:26 :: BB11 :: Replies: 2 :: Views: 473
I build simulation model of an sigma delta modulator (analog input digital output) in order to control transistors in 3phase full bridge resonant inverter. In negative feedback loop I have 1bit D/A converter and it gives +-5V.
Reference voltage is 5V*sin(2*pi*50Hz*time). I couldn't rise this voltage at 220V because of op amp input is max (...)
Electronic Elementary Questions :: 18.01.2005 07:28 :: epp :: Replies: 0 :: Views: 554
(3) Propagation Delay of 0.6ns.
This spec I don't think can be achievable
Think of a simple inverter in 0.35um, can u archieve a comparator comparable to an simple inverter?
Maybe the spec is wrong
Analog Circuit Design :: 29.10.2007 07:10 :: firstname.lastname@example.org :: Replies: 5 :: Views: 1599
I think what you're refering to goes by the name of 'super buffer'. It's nothing more than series of interters starting to minimum size to larger sizes as you move from right to left towards your load. You don't design a big inverter because that'll offer too much load to the your previous logic. Super buffer simply distributes the load in many sta
Analog Circuit Design :: 07.04.2005 12:41 :: chinito :: Replies: 12 :: Views: 6756