300 Threads found on edaboard.com: Latches
There are no asynchronous RAMs in an FPGA is that clear enough?
If you try to implement one it will either a) fail to implement, or b) end up as a huge design that implements latches in the LUT fabric to store bits.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-08-2017 02:40 :: ads-ee :: Replies: 3 :: Views: 440
Hi - I'm working on fixing a pool controller and there are 2 pcbs that are connected by a flat ribbon cable (6 connectors). The male part easily pushes into the female. Then there is a small tab that fits over it that latches and adds the friction to squeeze the ribbon in.
I can take a picture but I've run into this problem of trying to locate
Hobby Circuits and Small Projects Problems :: 02-20-2017 23:53 :: DaveInPA :: Replies: 1 :: Views: 352
Yes - I recommend you avoid latches - using them is poor design practice. And using buffer is generally frowned on, especally when y is not even used as a buffer.
Also because you have a clocked process, using else to hold the state machine in the same state is not required, as this will happen automatically.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2017 21:43 :: TrickyDicky :: Replies: 27 :: Views: 2367
You have made this thread on at least 2 other forums. Your video did not work on those forums but it works here.
The datasheet for the receiver IC says that it latches an output when it receives the coded pulses and its MOD pin is high. The output pulses when it receives the coded pulses and its MOD pin is low.
Hobby Circuits and Small Projects Problems :: 12-24-2016 17:00 :: Audioguru :: Replies: 4 :: Views: 705
Quartus synthesizes the miso output register code because it can be rewritten as regular synchronous register description according to the template. Just pull-out rising_edge(clk).
There are however many latches generated and missing sensitivity list entries will probably cause simulation to synthesis mismatch.
Don't know why the design is wr
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2016 13:59 :: FvM :: Replies: 4 :: Views: 1398
To convert the "simplified" example into something meaningful, there should be a first process line like
Reason: A combinational process should set the state of any affected signal in any conditional path and not generate latches. Signals working as state memory should be only set in clock edge sensitive processes.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-21-2016 19:00 :: FvM :: Replies: 3 :: Views: 482
The following section of code shows the warning:
Xst:737 - Found 1-bit latch for signal . latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
SIGNAL SIG_bit : STD_LOGIC := '0';
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-14-2016 10:26 :: rafimiet :: Replies: 13 :: Views: 1022
What I get reported is that next_pause_lasting and next_pulse_lasting will be generated as latches because they are not in each of if/else branches, but I don't see how I could fix it.
This is because you have "null" in the else branch. Because you're not using a clock, or signals that behave like a clock, the FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-08-2016 13:25 :: TrickyDicky :: Replies: 6 :: Views: 736
Any way to extract a list containing all the latches used in a netlist (Sram macro) ? Does any simulator support this kind of functionality ?
ASIC Design Methodologies and Tools (Digital) :: 11-04-2016 05:26 :: vasaroopak :: Replies: 1 :: Views: 436
as per datasheet following programming of B port helps
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0Eh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
Microcontrollers :: 09-11-2016 15:26 :: mvs sarma :: Replies: 3 :: Views: 465
You don't show read _s or pp_s in chipscope. I assume they are set to 1.
But this brings up another question, why are you using latches? There are no latches in an FPGA and have to be created with luts. They are prone to timing problems and will react to glitches on any signal. I highly recommend you do not use a latch.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-23-2016 05:57 :: TrickyDicky :: Replies: 5 :: Views: 369
I guess this link will help you understand better.
ASIC Design Methodologies and Tools (Digital) :: 08-21-2016 03:08 :: grvkpr18 :: Replies: 2 :: Views: 822
Cannot directly answer your question as I have never done STA on a latch based design.
In ASIC designing, within the design team, if you give a synth. design containing latches (which is not intended) the DfT engineer should be shouting back at you!
Better to fix such issues at the design stage and then go for STA and other ASIC design flows.
ASIC Design Methodologies and Tools (Digital) :: 05-30-2016 20:21 :: dpaul :: Replies: 6 :: Views: 542
Seems to refer to a 1:16 demux plus 16 RS-latches. Surely not available as a standard IC. You need to define a reset condition, by the way.
Digital Signal Processing :: 01-14-2016 15:24 :: FvM :: Replies: 6 :: Views: 716
thanks, but no pin 2 , if taken low, latches the chip off for good.
In the end , we have disabled it by jointly pulling LOAD pin low and discharging the SS cap with a BJT....we hope this is ok...datasheet doesn't tell.
Power Electronics :: 11-02-2015 20:38 :: treez :: Replies: 2 :: Views: 540
In usual terminology, a D-FF is an edge triggered device. Technically it's implemented as a combination of two latches, see the circuit from a HC74 datasheet.
The "DFF" shown in your post isn't edge triggered and can't work for a phase-frequency detector.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-16-2015 06:37 :: FvM :: Replies: 8 :: Views: 595
I'm restricting my answer to the problem why ccstate bits are analysed as clocks. This happens because the combinational process generates latches for all signals that aren't assigned in every case. You'll find many warnngs about latch inference in the compilation report.
I'm not really motivated to dive into the design details and find out poss
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2015 09:12 :: FvM :: Replies: 6 :: Views: 649
What is the use of sr latches in the reciever electronic board of a laser land leveller?
Digital communication :: 06-27-2015 04:29 :: jaiswalkshitiz14 :: Replies: 0 :: Views: 334
As stated in the previous post you should use a latch instead of the 245.
The point of a 16 bit interface is for speed, would using a latch be any faster than writing 8 bits at a time without the latches? I don't think so!!
A trick that I used is to connect 10K resistors between the data lines ie 10k between D0 and D8 10K between D1 and D9 etc. Thi
Embedded Linux and Real-Time Operating Systems (RTOS) :: 05-25-2015 01:09 :: pjmelect :: Replies: 2 :: Views: 1182
Check your gate drive currents against TRIAC specs.
Top method has full voltage across opto driver , giving excess current blowing R9
While bottom should work with sufficient drive current at a <<10V then shuts off gate drive then TRIAC latches.
While for med/high drive the following is recommended
Power Electronics :: 03-17-2015 04:25 :: SunnySkyguy :: Replies: 2 :: Views: 1390
Every FF is two latches. If you only need a latch, don't
pay for two.
ASIC Design Methodologies and Tools (Digital) :: 03-12-2015 00:15 :: dick_freebird :: Replies: 3 :: Views: 588
Recall that placing the reset section at the top results in latches if a signal is not reset as the logic becomes an async load.
Assuming you're talking about a synchronous process with async reset, it actually stays a register, with the async reset as the clock enable on the register. (at least with quartus - b
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-22-2015 22:37 :: TrickyDicky :: Replies: 8 :: Views: 656
How would you time your design if you use latches instead of flip flops?
ASIC Design Methodologies and Tools (Digital) :: 01-14-2015 22:40 :: shaiko :: Replies: 5 :: Views: 1246
but it works :)
How did you test the code? bit_cnt is implemented with unsafe latches, it's hard to imagine that bits are counted correctly.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-20-2014 18:29 :: FvM :: Replies: 7 :: Views: 1357
I am designing a Serializer and the last stage requires a high-speed architecture so I used TSPC topology for flip-flops and latches. The problem is I need the TSPC latch to delay its input signal by half a period and I tried everything but the delay is still about quarter a period. Is there any solution for that problem or is it common tha
Analog Circuit Design :: 12-02-2014 22:45 :: Engineer4ever :: Replies: 1 :: Views: 669
If you mean that you don't often see latches in RTL that is targeting fpga's, then that is probably because for fpga's latches are generally a bad idea. Static timing analysis and all that.
Do you want to use latches in an fpga design? If yes, then why?
- - - Updated - - -
Also, if you want latches, just us
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-27-2014 14:07 :: mrflibble :: Replies: 6 :: Views: 971
1. The original code doesn't work as a counter in real hardware.
2. A state-of the art synthesis tool recognizes that the counter'high is restricted to 12 by the code, thus the fifth FF will be discarded and replaced by a constant 0 bit. Only 4 latches, respectively D-FFs if using the working code suggested by shaiko.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2014 11:50 :: FvM :: Replies: 34 :: Views: 3165
They may have provided the component primitives libraries that may have historically provided latches, but the silicone doesnt have them. They will get emulated with Luts.
Afaik, no FPGA going back to the mid 90s (Ive worked with flex10ks) has latches - they are all made with luts and registers.
The reg in the slice/alut may have some async p
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-09-2014 14:23 :: TrickyDicky :: Replies: 9 :: Views: 1119
Someone suggested to use interface_timing=true for latches in .lib file. I cannot find info on what this attribute really does. In the Liberty reference manual, it says
Indicates that the timing arcs are interpreted according to interface timing specifications
semantics. If this attribute is missing or its value is set to false, the timing rela
ASIC Design Methodologies and Tools (Digital) :: 08-15-2014 18:23 :: k31th1408 :: Replies: 1 :: Views: 1128
Lockup latches can help in hold time violation during scan shift. How about during Capture?
ASIC Design Methodologies and Tools (Digital) :: 08-13-2014 20:59 :: priyutiru :: Replies: 2 :: Views: 885
Flip-flops are edge-triggered pairs of latches. You can't make
a flip-flop into a latch but you can make latches and inverters
into flip-flops. Why do you not use a latch library element as-is?
ASIC Design Methodologies and Tools (Digital) :: 07-27-2014 18:52 :: dick_freebird :: Replies: 4 :: Views: 651
latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. .
The error message is giving you a good hint. The value of outbus must be described in every single state. Likewise with any other signal that is on the
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-04-2014 17:09 :: rberek :: Replies: 2 :: Views: 2468
I am trying to figure out what are the possible problems you could get if you connected a mux output to one of its inputs.
So that when "select" is '0' it passes input1, otherwise it keeps the output value.
I know that it's a combinatorial loop and EDA tools might complain, but how on earth could you get an unstable/oscillating situati
ASIC Design Methodologies and Tools (Digital) :: 06-30-2014 15:39 :: George_P :: Replies: 2 :: Views: 616
The fact that you are using any latches usually points to poor design practice. WHy not post the code thats causing the problem?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-08-2014 07:28 :: TrickyDicky :: Replies: 7 :: Views: 2441
Everywhere we are seeing posts on why latches should be avoided in a design. But I would like start a contrary thread which captures where and all latches are used in the present day ASIC design flow.
I am listing here few practical usage of latches in the ASIC design. I would like others to add to the list.
1. latches (...)
ASIC Design Methodologies and Tools (Digital) :: 04-28-2014 10:10 :: mr_vasanth :: Replies: 12 :: Views: 1401
I wrote a small FSM (Mealy Machine) transition table design using VHDL and I'm using ISE(Xilinx Design tool) for synthesis. The synthesis goes fine but, It also throws some warning messages. It seems that my code is generating some latches, but I couldn't find a way to remove it.
The input X is the external input to the design which I pl
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-18-2014 15:11 :: bitprolix :: Replies: 2 :: Views: 1054
What are the errors/warnings/messages we should give a careful attention in a DC-synthesis report ?
I have listed down few that I could recollect.
1. Any unmapped components
3. non-resettable FFs
What else one has to look at and why ?
Any practical experience, which you missed to look at the synthesis report initially and found
ASIC Design Methodologies and Tools (Digital) :: 03-03-2014 13:14 :: mr_vasanth :: Replies: 1 :: Views: 666
I'm not sure if the code does what you want to achieve, I won't e.g. expect a decoder to genarted latches. But "incomplete sensitivity list" is an erroneous warning, sounds like a synthesis tool bug.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-15-2014 16:44 :: FvM :: Replies: 6 :: Views: 1182
Whats the problem?
Your control module produces latches, and the i1 and s1 signals are 32 bits wide - why?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2014 10:32 :: TrickyDicky :: Replies: 3 :: Views: 430
as my understanding on d latch, if clk is high, the d input will result in the output. and when clk goes low, the output is latched. and again if the clk goes high, then d input reflects at the output. but in the case of 74ls373 latch ic, when the clk goes low once, the out is latched for ever. even if the clk goes high again, no changes ha
Elementary Electronic Questions :: 02-04-2014 15:49 :: vasanth kumar :: Replies: 2 :: Views: 450
In xilinx how can one ensure that the synthesis tool will accept an array(0 to 255) of std_logic_vector(7 downto 0) is interpreted as ram and not luts.
I may need asynchronous write operation.
Also how to avoid latch inference for internal signals? What will be problems faced if latches are used?
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-13-2014 15:59 :: anoperson :: Replies: 2 :: Views: 496
RAM should be modeled in the following way. RAM modeled without clocks will mostly infer latches.
entity RAM is
generic ( K: integer:=8; -- number of bits per word
W: integer:=8); -- number of address bits
port (WR: in std_logic; --active high write enable
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-13-2014 03:57 :: vlsi_whiz :: Replies: 3 :: Views: 573
When you clear the RESET on latches , the latches shouldn't keep a voltage it should be at zero volts
1.) When I switch on the Enable switch to the Latch CD4043 , It will output a +14 volt , why is that , it should be zero volts right?
2.) There is a CD4017 Decade counter before the Latch CD4043, The CD4017 Decade counter takes 3 seconds to
Elementary Electronic Questions :: 12-28-2013 02:11 :: danny davis :: Replies: 0 :: Views: 675
I need to simulate a circuit with SR latches, in LTSpice.
The latch output should be 5V-9V. LTSpice has model for SR Latch as 'srflop' however, the output is only 1V.
How can I increase the output voltage?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-08-2013 19:44 :: abuhafss :: Replies: 1 :: Views: 7858
i have no idea why i am getting latch infer warnings in this code below
and i made sure that all cases covered including default case.
entity freqdomaintrainingseqmem is
state : i
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-03-2013 04:43 :: me0414013 :: Replies: 5 :: Views: 563
You shouldnt be assigning next state to present state - this is just going to create latches when you build it (you'll probably see a load of errors about this). I suggest just making it all a single clocked process.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-02-2013 20:58 :: TrickyDicky :: Replies: 8 :: Views: 1980
If you have a default value, assign it at the beginning of the process. Then you can be sure that no latch will be created.
This will also often make it possible to simplify the code:
output_proc : PROCESS (
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-02-2013 09:56 :: std_match :: Replies: 2 :: Views: 1220
Output Enable or OE pin on many digital logic ICs or some digital driver ICs is used to make output enable/disable...if this pin is in its active state then the content of internal latches/gates of that particular IC is reflected on the keeping this OE pin in its inactive state the ouputs are tristated/high impedance states...
Microcontrollers :: 11-10-2013 16:20 :: aashitech :: Replies: 4 :: Views: 4650
There is many topologies are available for FF ..
In simple, Two latches are combined to give you a FF of your choice...
Refer "CMOS circuit Design, layout and simulation" by JAcob Baker or search the net..
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-05-2013 10:04 :: kenambo :: Replies: 5 :: Views: 829
Not clear what you are asking for.
A "bistable latch" can be either a RS or D latch. The circuit and behavioral description will be found in any digital logic text book (or Google). You get a 4 bit device by instantiating four single bit latches.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-31-2013 13:23 :: FvM :: Replies: 3 :: Views: 1282