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the fdtd programming guide (beta)
once more it is i, the fdtd junkie.a few words : i am currently doing my diploma thesis which involves fdtd. hence i had to learn this method from scratch in order to truly grasp it. although many books on fdtd do exist some of which (like sullivans)...
Electromagnetic Design and Simulation :: 22 Nov 2009 17:56 :: medaziz :: Replies: 28 :: Views: 1916
post layout simulation problem
dear all,i did prelayout and postlayout simulation of an opamp,in prelayout simulation all transistors are working in saturation and gain is good 64 db,but where as in post layout simulation,few transistors going to linear and gain falls to 50 db,h...
Analog IC Design & Layout :: 22 Nov 2009 5:35 :: eecs4ever :: Replies: 2 :: Views: 81
strange error in ads's schematic simulation
my project file is huge since i did everything in one project, so i cant upload the project until i figured out a way to separate a single layout design, together with the associated layout file, substrate file, and simulation data nicely, and i do n...
Electromagnetic Design and Simulation :: 19 Nov 2009 7:15 :: kspalla :: Replies: 2 :: Views: 114
analog circuit design tool
hi marie,it is tough to get in any of these software until u have access through educational institutes or huge co-orporations.if you are seeking to learn this on your own, well u can get there manuals but not the softwarethats true marie, and some t...
Software Downloads/Uploads :: 17 Nov 2009 9:15 :: koosdoos :: Replies: 33 :: Views: 14309
microstrip bandpass filter design
hello everybody,fist off, id like to thank this community for all the valuable information and the answers to many of my questions ive found here so far. this is my first post.although microstrip filters are not the main part of my job, i need to des...
RF, Microwave, Antennas and Optics :: 11 Nov 2009 3:49 :: mnigj :: Replies: 8 :: Views: 435
looking for an opportunities in asic physical design
hi i am having 3+ years exp in asic physical design and i am looking for a job change... skills: * familiar with backend design flows * synthesis * static timing analysis * static ir drop analys...
EDA Jobs, Promotions, Advertising :: 10 Nov 2009 19:48 :: pilu.sandeep :: Replies: 1 :: Views: 132
return loss in filters - feed line and resonator mismatch
when we talk abt filters we talk only abt insertion loss but we dont talk abt return loss why??????when iam designing a combline or interdigital using tapped line input i directly give feed line( 50 ohm) to resonator which is having an impedance of ...
RF, Microwave, Antennas and Optics :: 09 Nov 2009 3:55 :: sandeepsreeman :: Replies: 8 :: Views: 261
problem when i made simulation momentum in ads
hi all,i have a project of design amplifier at 4 ghz in ads and when i made dc_block i had a good result for s11&s12 but when i simulate it by momentum i had a bad result, so i dont know where is the problem.you can see my numbers.thx...
RF, Microwave, Antennas and Optics :: 08 Nov 2009 22:23 :: tomtomson :: Replies: 7 :: Views: 183
layout problem - common centroid techniques
hi dear all friends,i want to draw layout of comparator used in my adc. this comparator must be so accurate thus i have to use of common centroid techniques. preamplifier used in my work consists of differential difference amplifier followed by regen...
Analog IC Design & Layout :: 08 Nov 2009 17:48 :: erikl :: Replies: 5 :: Views: 315
rf transformer design with ads momentum
hello everybody,ive drawn a small spiral inductor with the momentum layout-editor in layer cond, and the same inductor in layer cond2. in between there is my substrate with epsilon_r. so ive got a transformer now.for s-parameter simulation i inserted...
Electromagnetic Design and Simulation :: 06 Nov 2009 16:05 :: jk_olivo :: Replies: 3 :: Views: 612
segment error in visualization of a complex momentum model
i simulated a coplanar curved signal divider (without air bridge) in momentum, and im sure the meshing is fine enough to capture all the details. but after running the simulation, it gave very odd visualization. i tried both strip and slot mode, but ...
Electromagnetic Design and Simulation :: 06 Nov 2009 16:03 :: alexneverhurts :: Replies: 2 :: Views: 66
what other software tools can sombody use except cadence?
as far as i know, we can use labview and spice for schematics. are there any other program tool used? labview is only for schematics or both schematic analysis and layout?what is your opinion about magic? this one, is it only about layouts? which is...
Analog Circuit Design :: 05 Nov 2009 16:12 :: dick_freebird :: Replies: 2 :: Views: 147
regarding virtuoso xl layout editor
hi all,i am designing a residue stage for pipelined adc. i have just finished the simulation phase and now have to do the layout. i have heard about this virtuoso xl layout editor tool. could someone answer my following questions regarding that.1. is...
Analog IC Design & Layout :: 05 Nov 2009 15:45 :: Mr.dal :: Replies: 5 :: Views: 162
awr desing environment tutorial
hi all, i am new user to awr design environment (microwave office), can any one send me tutorials or links to learn using this software. thanks in advance...
RF, Microwave, Antennas and Optics :: 05 Nov 2009 10:12 :: haseb_09 :: Replies: 33 :: Views: 7051
grid tie inverter - open source project
i would like to join (or start) a grid tie inverter open source project. does anyone know if there exists such a project? i could probably design such a thing myself but it would take me a long a$$ time, so im looking for more team members.mr.cool[...
Power Electronics :: 05 Nov 2009 4:20 :: Mr.Cool :: Replies: 4 :: Views: 354
which is the best software for pcb design?
i am new in pcb design.i worked with pulsonix, eagle & ultiboard.i think the best is pulsonix:-p...
PCB Routing & Schematic Layout software & Simulation :: 04 Nov 2009 4:57 :: soesilo :: Replies: 207 :: Views: 38032
native device layout problem
hi, why is that native nmos transistor cannot be placed within a deep nwell.i have a case in which the whole analog ckt is placed within a deep nwell but i am not able to place a native mos.i am using umc65.thanks in advance....
Analog IC Design & Layout :: 04 Nov 2009 4:18 :: evi :: Replies: 5 :: Views: 414
extracting power nets only from layout
in the past i used to use a tool that would take a lvs clean layout create a view showing only the metal layers attached to a supply pin. this was very handing to make sure there was not any blocks relying on minimum sized wire for their supply lead...
Analog IC Design & Layout :: 02 Nov 2009 8:28 :: llbaobao :: Replies: 3 :: Views: 159
cadence encounter tutorial
here is the cadence tutorial.please reply me your valuable comment....
Analog Circuit Design :: 01 Nov 2009 2:30 :: foreveryanyee :: Replies: 7 :: Views: 2809
hfss tutorial for transmission line vias
hi, i have been contacted by many people from edaboard forum about hfss tutorial. so, i have uploded a tutorial with its hfss projects.i hope this work will be helpfull....
Electromagnetic Design and Simulation :: 31 Oct 2009 9:25 :: breadpig :: Replies: 211 :: Views: 57463
the presicion of mom-cap in 12bit adc
hi, all: the project is a 12bit sar-adc, the 6 msbs is binary-weighted mom-cap, the unit is 68ff, and the msb is 68*32=2176ff. the 6 lsbs is resistor divider.in the pre-simulation the enob is 11bit. but in the post-simulation the enob is just 8.6...
Analog IC Design & Layout :: 30 Oct 2009 7:19 :: timof :: Replies: 2 :: Views: 207
folded cascode lna - tunning circuit to actual lna
hello. im a student working on the folded cascode lna designed by my senior to work on 2.14ghz. the lna have been fabricated and the chip is measured. the s-parameters measured shown some deviation from the desired spec. i am required to do optimizat...
Analog Circuit Design :: 30 Oct 2009 5:11 :: snafflekid :: Replies: 5 :: Views: 162
nport working in spectre, won't netlist in hspice
i have a working spectre simulation using an nport to load the s-parameter file of the package and a layout extraction for the chip. i need to generate an hspice model, but the netlist fails. i get the following messages:messages:error: missing or ...
Analog IC Design & Layout :: 29 Oct 2009 23:52 :: dapwapo :: Replies: 0 :: Views: 90
problem on post layout simulation
i am using drc, lvs and lpe files (available from umc 90nm design kit). drc and lvs are running well, but when i run calibre-> pex (parasitic extraction) the following error is generated:undefined layer name parameter: nsd_clpe file has definition ru...
Analog IC Design & Layout :: 29 Oct 2009 4:58 :: Reeuenta :: Replies: 5 :: Views: 501
wilkinson power divider design
on power divider. currently, i have come out with something and the s-parameters simulation results are as expected. however, as i was doing the momentum simulation, the results were erratic!! the layout came about directly from the schematic. i ...
RF, Microwave, Antennas and Optics :: 27 Oct 2009 13:24 :: Aver :: Replies: 11 :: Views: 2340
strange postsimulation results
i use calibre pex for my layout postsimulation, but i find a strange problem.for sub-block a and sub-block b, when i extract the separate pex calibreview for a and b, and simualte, the results are very bad, resolution from 10bit(presimulation) to 6bi...
Analog Circuit Design :: 26 Oct 2009 14:14 :: lhlbluesky :: Replies: 5 :: Views: 189
q calculation of inductor
how i can measure the q of a spiral inductor(tsmc 0.18um) in ads?...
Analog IC Design & Layout :: 26 Oct 2009 11:34 :: rezaee :: Replies: 19 :: Views: 609
cadence orcad & cadence virtuoso
hi,i want to know the differences between these two product lines? both have its own simulator and schematic capture. but virtuoso have ic layout features. others?...
Software Problems, Hints and Reviews :: 23 Oct 2009 11:50 :: sudheerkm :: Replies: 7 :: Views: 735
pic-getting started with design
hi,the end result of my project should be a full layout and 3d model of a device that includes the pic18.what is the best software for the layout/3d and pic simulation.thanks....
Microcontrollers :: 21 Oct 2009 0:02 :: slogin5 :: Replies: 0 :: Views: 78
calibre pex post-simulation problem, too
first, thanks everyone who give me help these days.now, i still have some problem. in pre-simulation, my circuit can work well. but when i extracted pex netlist in calibre, and do layout post-simulation with the extracted netlist (with spectre), i fi...
Analog Circuit Design :: 16 Oct 2009 13:27 :: wpchan05 :: Replies: 2 :: Views: 123
layout post-simulation problem
i use calibre pex for layout post-simulation, but relative to the pre-simulation results, post-simulation results diff very much; in some cases, it even cant work.why? what is the reason? and how to find the problem in layout, and fix them one by one...
Analog Circuit Design :: 15 Oct 2009 12:58 :: lhlbluesky :: Replies: 2 :: Views: 99
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post layout simulation using hspice
hello friends, i have created a layout in virtuoso, extracted rc for the same using starrc xt. now i want to do post layout simulation using hspice. the rc extracted netlist contains r and c values for the different nets, now how can i interact th...
Analog IC Design & Layout :: 12 Oct 2009 7:45 :: penghan :: Replies: 3 :: Views: 132
cadence license problem
my previous license list in .cshrc is:setenv lm_license_file /usr/commercial/cadence/license/tools.sun4v/license/license.datsetenv cds_lic_file $lm_license_filecadence worked well before. but the license was expired, i cannot edit or simulate circuit...
Linux Software :: 10 Oct 2009 20:21 :: R00KIE :: Replies: 3 :: Views: 390
help needed for reduction of time of modelsim simulation
i am working on fpga project, simulation of my project is completed in one day, and the constraint of time on simulation is making my progress slow on this project. help is required in this regard to cut short the processing of simulation...
PLD, SPLD, GAL, CPLD, FPGA Design :: 08 Oct 2009 4:23 :: irshan :: Replies: 2 :: Views: 120
charge pump bug, need help
hi : i have a charge pump circuit like fig. , from the simulation result it can pump upto the 12v , but in real measurement, i find the block cannot pump to the high voltage. the question is it really hard to find the bug on the wafer, anyone whoh...
Analog IC Design & Layout :: 07 Oct 2009 10:14 :: leo_o2 :: Replies: 7 :: Views: 342
lvs sometimes successed sometimes failed
same schematic and same layout, lvs gave me different results.in the si.out, it saidnet-list ambiguities were resolved by random selectionthis randome selection sometimes right sometimes wrong. will this chip work in reality?any one have the same sit...
Analog IC Design & Layout :: 29 Sep 2009 21:37 :: JoannesPaulus :: Replies: 4 :: Views: 228
candence vituoso ic 6.1 doubt
hi...i am using cadence virtuoso ic 6.1 for my analog design..for a transient analysis of 6.6 ms my circuit taked 14hrs to finish the simulation. is there any options available in the tool which will help bring down the simualtion time....thanks in a...
Analog IC Design & Layout :: 29 Sep 2009 14:09 :: prashantbabu :: Replies: 4 :: Views: 255
how to simulate netlists such as edif and ngc files ?
hi , if we want to instantiate an edif or ngc netlist file in a vhdl code , then how can we simulate it in modelsim or activehdl ?in modelsim when i copy the edif file or ngc file in my folder , after i write a vhdl code and instantiate it as a compo...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Sep 2009 13:35 :: farhada :: Replies: 3 :: Views: 240
ads circuitcosimulation error message _failed to find model
hello!i´m workin with ads2008. it´s not my first circuit co simulation. now i´ve a layout to simulate at 900mhz. the same layout simulation worked fine at 434mhz.but at 900mhz i get an errormassage during simulation and it stops:warning detected by ...
Electromagnetic Design and Simulation :: 25 Sep 2009 9:32 :: kspalla :: Replies: 1 :: Views: 108
how to include device capacitance in parasitic extraction?
question:do you know a method to get a tabulated list of nodes with total node capacitance including the device capacitance contribution?---------------------------------------------parasitic extraction generates a node list with associated capacitan...
Analog IC Design & Layout :: 24 Sep 2009 9:06 :: mengcy :: Replies: 1 :: Views: 156
microstrip combline bandpass fiter
hi my specs abt the design of combline bandpass filter is ripple in passband is 1db and bandwidth is 20mhz and centre frequency is 1.8ghz and attenuation on stop band is 60db at 1.88ghz . manually i designed first coupled line filter when i implement...
Electromagnetic Design and Simulation :: 22 Sep 2009 9:27 :: chandregowda :: Replies: 2 :: Views: 276
si solutions comparision
hi, brosas we know, now in industry, we have several pcb si parameter modeling/extraction/simulation solutions, for example:cadence pcb si solutions (specctraquest)ansoft ansoftlinks+q3d+hfss+designer+siwave solutonssynopsys hspiceagilent adsmentor g...
Electromagnetic Design and Simulation :: 18 Sep 2009 2:27 :: asiaswallow :: Replies: 5 :: Views: 855
what is front end and back end ?
im working as a newbie in a memory company ..they use these terms frequently ...can anyone tell me what they mean...
ASIC Design Methodologies & Tools (Digital) :: 17 Sep 2009 13:20 :: vlsi123 :: Replies: 3 :: Views: 375
difference between simulation and measured results in ads
what are the chances that ads simmulations does not match with the actual measured results?got this problem when i designed a meander antenna in layout and simulated using momentum. a very prominent resonance appears at 200 mhz, which is completely ...
Electromagnetic Design and Simulation :: 14 Sep 2009 16:09 :: skysearcher :: Replies: 2 :: Views: 237
port in advanced design system
hi to my friends.who can explain that what is applied to a port in ads/layout envirenment .and is there important the value of components in momentum simulations ?for example is it any diffrences between a momentum simulation that its layout have a r...
RF, Microwave, Antennas and Optics :: 14 Sep 2009 10:13 :: moreho :: Replies: 0 :: Views: 72
tft analog design in cadence?
hi, id like to simulate tft analog circuits using cadence. i have not been able to find much information about tft process support in cadence tools. does anyone have any experience with this? basically, id like to see (and implement) the full flow of...
Analog IC Design & Layout :: 13 Sep 2009 2:26 :: averros :: Replies: 2 :: Views: 219
how to / become professional pcb designer/
hi pcb newbie`s,to become a professional in pcb one should have good knowledge on the following points :1.drawing schematics in different tools/pkgs (altium,pads, allegro,..etc)2.understanding the errors and procedure of rectifications3.board details...
PCB Routing & Schematic Layout software & Simulation :: 12 Sep 2009 8:58 :: kvmanikandan :: Replies: 1 :: Views: 342
pass the commands from vc++ program to the command window i
who has the reference of cadence skill language...
Analog IC Design & Layout :: 11 Sep 2009 3:29 :: cop02ia :: Replies: 63 :: Views: 14304
problem desigining a microstrip tl
hi,i am a pure vlsi guy and have no clue of designing a tlbut, i had to do it for some other reason using hfssmy design is giving me the same results irrespective of the dimensions usedtool used : hfssquick reply could be helpfulregards,satish...
Electromagnetic Design and Simulation :: 09 Sep 2009 12:54 :: chemic :: Replies: 8 :: Views: 267
vhdl q?
im trying to do a pulse generator to be implemented in a cpld the idea is to get an output pulse of 280 us derived from a 25khz clock the pulse starts on rising edge of trigi wrote this and it worked as expecteted when i simulated in modelsim entity...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Sep 2009 12:05 :: anee_anil :: Replies: 7 :: Views: 1086
design translation between cadence and mentor tools
hello,i just got a strange question:is it possible to have complete design translation between mentor flow and cadence flow? i specifically mean by complete design everything: schematics, layout, simulation scripts, vhdl code, cells, ... just everyth...
Analog IC Design & Layout :: 09 Sep 2009 6:35 :: bravo_echo_11 :: Replies: 0 :: Views: 120
problem in simulation- schematic opens in design type only
hello sir,i am a beginner to learn circuit simulation.i am using orcad release 9.10.every time i make a project, perform simulation but after some time when i want to open my simulated circuit,there schematic opens in the design type only. as simul...
General :: 08 Sep 2009 5:54 :: senthilkumar.b :: Replies: 3 :: Views: 234
multisim 9 -working demo
the designsuite 9 software includes a fully integrated version of multicap, multisim, ultiboard and ultiroute.the capture and layout functionality in this software will work in perpetuity, and simulation and autorouting are available to you for a 45-...
Software Links :: 08 Sep 2009 1:03 :: mtzkhirt :: Replies: 12 :: Views: 23745
electronics work bench
hi electronics workbench for electronics educators, design engineers, and engineering students with powerful, easy-to-use tools for schematic capture, interactive spice circuit simulation, board layout, and design validation....
Software Downloads/Uploads :: 04 Sep 2009 8:48 :: graciousparul :: Replies: 0 :: Views: 699
lna circuit in rfic- lna's gain is lower than simulated
i have designed a lna circuit in rfic with charted rf cmos 0.18um process. the lnas measured current and bias voltage agree with its simulated ones.also, the lnas input and output port have been matched well with vswr<2 at 1.55ghz. however, the ln...
Analog IC Design & Layout :: 03 Sep 2009 10:25 :: dipak.rf :: Replies: 4 :: Views: 249
analog cmos parameters calculation
dear all, when we desgin analog cmos circuit by hand calculations, we need to know gm, rds, cdb, cgs and cgd, could some experts tell me how to get the above parameters from model file.the model file are very complicated, i dont know how to calcula...
Analog IC Design & Layout :: 29 Aug 2009 8:18 :: liuguojia387 :: Replies: 5 :: Views: 539
post layout simulation-tanner
hican somebody tell me regarding ost layout simulation in tanner.assume that i have got the layout extractedfrom the tanner standard place and route.can modelsim be used if i have a sdf filethanks in advance...
ASIC Design Methodologies & Tools (Digital) :: 29 Aug 2009 3:04 :: ksrinivasan :: Replies: 0 :: Views: 114
post-layout simulation
hello, i have finished the calibre pex and successfully extracted the netlist. but i do not know how to use the new netlist to run the post layout simulation i tried to google it but seems there is no up-to-data guide on cadence 6.1 anybody c...
Analog IC Design & Layout :: 26 Aug 2009 14:47 :: yassin2705 :: Replies: 10 :: Views: 662
schematic and post layout performance difference in 65nm
hi,i am working in 65nm technology and i have a problem with the post layout and schematic performance difference. take an example of the conventional transmission gate based mux, the post layout simulation has a performance degradation of at least 3...
Analog IC Design & Layout :: 25 Aug 2009 13:14 :: gafsos :: Replies: 9 :: Views: 728
microwave office lumped components in em
hiif i would like to make a wilkinson microstrip power divider, is it possible for mwo to somehow include the isolation resistor. either in the em-simulation orafterwards by incorporating the layout with the schematic.i have done this in ads and then...
Electromagnetic Design and Simulation :: 24 Aug 2009 22:52 :: kobasa :: Replies: 14 :: Views: 1339
diode simulation issue
hello, everyonewhen i use spectre to simulation diode, chose junction model parameters, level 1. it is said that the effective area is equal to area · m, unitless. so does pj, unitless?what does unitless mean? if the area and junction perimeter ...
Analog Circuit Design :: 20 Aug 2009 10:56 :: prcken :: Replies: 2 :: Views: 259
charge pump pll post simulation
i designed a cppll with the smic 018um , the ouput of it is 480mhz. i used the ring oscillator for the vco. when did the post-layout simulation of the vco, i found the result of it is very different with the result of the pre-layout simulation. such ...
Analog IC Design & Layout :: 20 Aug 2009 10:30 :: mengcy :: Replies: 9 :: Views: 742
spectre simulation error - "input.scs": unable to
hi all...i finished my layout, lvs, and pex in my research project circuit design but i m in stacked in spectre simulation...i showed the model library path..1)finger cap and 2) resistor what i have used in my circuit. but once i simulate in ac analy...
Analog IC Design & Layout :: 17 Aug 2009 22:02 :: coffeelox :: Replies: 5 :: Views: 283
calibre lvs and extraction
hello all,i am having trouble with calibre lvs. my problem is that calibre lvs does not recognize the pins i placed in the layout. for example, in an inverter my schematic has 4 ports (in, out, vdd!, gnd!) but calibre lvs states that my layout has 0 ...
Analog IC Design & Layout :: 17 Aug 2009 5:15 :: deepak242003 :: Replies: 7 :: Views: 792
what next after tspice simulation
hi friendsiam doing a work on digital asic implementation .the backend tool is tanner.my flow till now is vhdl-->synthesis(leo spec)-->edif-->tanner spr-->place and route-->drc-->netlist extraction-->t spice simulation/wedit waveform viewer-->what ne...
ASIC Design Methodologies & Tools (Digital) :: 15 Aug 2009 5:07 :: rob1012 :: Replies: 2 :: Views: 204
how to detect high current flow in circuits ?
evening gents,can anyone explain to the how to detect high current flow in circuits, i believe a low value resistor is used? does anyone have any suggested circuit examples?regards,ringo888...
Electronic Elementary Questions :: 14 Aug 2009 10:26 :: ringo888 :: Replies: 6 :: Views: 396
cmos lc vco
hi i have designed a cmos lc vco. i want to improve the output swing of the vco. pre layout simulations show that the output swing is 1.4 v (0.18u process)but after laying out all the blocks the output swing drops to 0.8v peak to peak.i would appreci...
Analog IC Design & Layout :: 13 Aug 2009 4:07 :: benever :: Replies: 7 :: Views: 552
difference btw back end and front end in vlsi
hi all,im an vlsi studenti searched in the net but i couldnt get the exact difference between back end and front end methodology in vlsi and asic design flow.i feel it was much differ from pcb layout back and front end design.can anyone clear me this...
ASIC Design Methodologies & Tools (Digital) :: 12 Aug 2009 12:43 :: salma ali bakr :: Replies: 5 :: Views: 506
error in co-simulation in ads soft
hello all, i tried to co-simulate the amplifier attached but i have encountred an error which is also atteched.is someone knows how can i resolve this problem,thank you in davance,n...
RF, Microwave, Antennas and Optics :: 12 Aug 2009 9:19 :: nassim1 :: Replies: 11 :: Views: 489
best signal integrity simulator
hi, alldo you think is the best signal integrity simulator for pcbs ?please post reply with a technical data and personal experience if you have !for example wich the si program have a pre-layout placement and post-layout routing simulation ?discussi...
PCB Routing & Schematic Layout software & Simulation :: 11 Aug 2009 7:04 :: chakravarthy80pcb :: Replies: 27 :: Views: 5327
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