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41 Threads found on edaboard.com: Layout And Interview
Hi, Can anyone share a number of interview questions for Analog layout engineer position? and ofcourse possible answers will be much appreciate if you are kind enought. or can you give any URL that i can read for my incoming interview. God bless!!! Liz
Hi all, Can anyone share some examples of IC design interview Q&A? Please give the example questions relate to R,L,C, CMOS, layout and digital. many thanks.
hi guys can you anybody have layout and PCB related Technical questions and answer plz updated . i need it . Thanks Regards V.jagaveerakumar
Hi fellow friends and professionals I am a final year student and have been shortlisted for an interview for VLSI layout engineer position next week. I have prepared on some topics; ?MOSFET characteristics, operations, cross sectional view ?Digital logic gates, multiplexers, boolean algebra, flip flops (...)
Hi fellow friends and professionals I am a final year student and have been shortlisted for an interview for VLSI layout engineer position next week. I have prepared on some topics; ?MOSFET characteristics, operations, cross sectional view ?Digital logic gates, multiplexers, boolean algebra, flip flops (...)
Hello can i find any book which can have all basic questions and answers on digital,analog,PCB layout and EMI/EMC. simply interview questions for experienced people on mixed signal hardware designer thanks in advance Usha M
Draw an inverter. Draw the layout. No, I use a P-well process (or whatever is opposite of what you draw) Redraw it. Draw a 4-1 mux using transmission gates (or whatever they think you don't know based on how you answered #1) What tools do you know? Do you know Verilog (or VHDL)? How many pins was the biggest project you have made? Wha
but post-layout simulation is time-consuming, as long as forever.
Here are few question Gain, (how to improve gain?) Bandwidth, (how to improve bandwidth?) Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!) Slew rate,(How to improve slew rate?) Offset,(how to eliminate offset? Chopper stabilized circuits, autozero) Noise,(what is thermal, flick, shot noise? (...)
I would graduate in 2006 with a master's degree. I have been doing research on RFIC(LNA and Mixer) since I did my thesis for my bachelor's degree. and during my graduate study, I have been respingsible to circuit design and optimization for a low voltage supply mixer with new topology and common gate LNA with active (...)
I use prime power to analyze power consumption. First extract the RC in layout, then run post simulation to get a waveform, then use the waveform and RC to calculate your power. Note the post sim case is the one you think power consumption is the most.
hello salma thanks a lot for ur prompt response the position is for a layout engineer
Hi Satya, In case if you are fresher then You should be ready with circuit analysis. Apart from that you should have the through study on current mirrors, reference circuit, single stage amplifier, and Op-amp. In Op-amp you must know diffrent type of circuits, feedback and compensation technique, pole zero analysis, gain/phase margin and (...)
what are interveiw question based on cmos ic layout ?
and some layout basics to improve your circuits performance. Also know the details of the project you've involved.
hello, nice to be on this forum.recently i received a call from a company for a interview for the post of analog layout engineer. i would like to know what are the topics i should be strong while attending the interview. this is post for a fresher. please can anyone mention the skills needed in electronics, (...)
here is the place to post vlsi job offers. this must contain format like below.This is only for vlsi jobs. Thanx. company: company location: job position: job description: experience requirement: qualification requirement: interview date: Added after 6 minutes: Hardware Engineer Kyocera Wireless
Clock skew is a major problem in the design of large-scale high-speed ASICs. CTS layouts that use a dedicated clock trunk line or CTS to resolve this clock skew problem. Through buffer insertion and layout and flip-flop layout is performed to minimize clock skew in the chip.
I'm learning layout. I'm doing my first inverter using a pmos and an NMos transistr from the library. I know that the pmos bulk have to be connected to vdd, the nmos bulk to gnd. That is not clear for me in the picture sowing the layout of the 2 transistors. I drawed the layout of the inverter, but I dont know to connect the (...)
Hi All, I have a question about the layout of IC. For high speed differential signals (few GHz to 10GHz), I know the width depends on the current of the signals, but what is distance between these trace? does this related to the width of the trace? Thanks in advance CDZ
Hi, You can check the following link for some tips: btw, as dick_freebird already mentioned, the interview questions depend on the type of layouts the opening is for and the experience they are looking for. In general for jobs which require some experience, be thorough wi
I have few points, 1. Leakage : Since memory is a charge storing element. 2. Speed : How fast read/write operations are done. How many clock cycles does it requires to complete one read/write operation. 3. During layout how much area does it take (depending on size of memory) People can add more.
Hi All, I have an interview for a hardware electrical enginner postion to prepare. Anybody has advices and suggestions? Any good materials or tutorials to review before going to the interview? The job description is as following: RESPONSIBILITIES: Your responsibilities include but not limited to the following: - Hardware design (...)
I'm trying to get the answer for these questions, and would appreciate any help I can get here. * What is EM and it effects? -Usually driving a small wire with large currents (this happens usually in poer meshes) causes metal fatigue and deformation which furher hampers the ability of the wire to carry electrons effectively. If (...)
Hi All, Could anybody tell me what kind of questions are generally asked from Digital CMOS layout during a job interview ? I have an upcoming interview coming up for design engineer and there is a dedicated session on layout. Any help is highly appreciated. TIA
-- Posted this in the job section, nobody seems to be replying -- Hi All, Could anybody tell me what kind of questions are generally asked from Digital CMOS layout during a job interview ? I have an upcoming interview coming up for design engineer and there is a dedicated session on layout. Any (...)
To begin with be dextrous with voltage and current calculation in a simple R network! :P Study at RC and RLC circuits: time constants, rise time, falltime, stability.. General: gain, phase margin, gain margin, SR, input imp, output imp, small signal models, input and output offset, mismatch and in analog (...)
You have not mentioned what type of interview you are referring to actually im attending an written exam followed by an interview to get admission for custom layout training. So the portion of the exam includes BJT, FET, CMOS etc. based on this i needed some help to clear it. :)
IC layout/ PHYSICAL DESIGN CERTIFICATE COURSE Learn concepts of layout design including standard cell layouts and custom analog layouts. Sahyogee Tech Solutions Course Highlights: Curriculum defined by industry experts Emphasis on teaching industry-relevant concepts Focus on (...)
Hi, I am doing layout mask designing certificate course, can anybody tell me interview question regarding that.
Test point insertion is to add flip flop for scan testing. DRC means design rules check, and there are some DRC for the ATPG, for layout.... Which one your questions is related?
The backend process include: Circuit design, circuit synthesize, layout, P&R(Place and route), pin assignment The backend support include: P&R(Place and route), pin assignment
What kind of job interview were you done for this questin? layout position, or designer, or system manager
hi u can refer Razavis Book regards analayout
Guess CAdence schematic and layout editors would be good start. and then decent text editor Knowledge - som C would help and SKILL language is obviously must. There is a skill develop. tool but as far as I know it won't help you any.
i guess it's similar to layout pattern.
Hi Folks I will have an Test Engineer position onsite interview. Since I don't do any test before, I am just wonder what kind of testing questions they will ask , I feel they will ask some PCB layout questions, and some coding questions. Can someone elaborate the PCB layout questions and coding (...)
Hi everyone. Thanks for showing your interest. My company is a newly startup in Singapore. The parent company is from Korea. We are looking for experienced design engineers in the area of power management IC. The project we are doing will be such as LDO, DC/DC converter with internal power MOSFET (buck/booast), Analog switches, LED drivers Ic, e
Hi, Can anyone answer to following question. Post layout STA(with SPEF) passes but the simulation fails on the same logic path. What might be the reason? Regards,
hello friends, i got a question in an interview... after you done the layout for an inverter, DRC says that you need to put a guard ring for pmos and nmos???? option 1: we can stretch p-cell and n-cell...then put a guard ring for both.. option 2: without stretching the both cell, simply put a guard ring then (...)
I am new for the layout. I was asked below question during the interview, "there are two seperate gnds for digital and analog, VSS-D and VSS-A, in the layout. how does the layout pass LVS and Calibra?" May I know how to approach it? Thanks in advance.