31 Threads found on edaboard.com: Layout And Wide
I am a Electrical engineer and have over 3 and half years of experience of professional PCB Designing.I gained wide exposure on all aspects of PCB layout expertise is on Altium Designer, Eagle,PADS,P-CAD and Allegro.
I worked with many local and international clients and (...)
EDA Jobs :: 03-25-2017 12:59 :: Nick Arsi :: Replies: 0 :: Views: 945
I have a designed a layout in SoC encounter based on NangateOpenCellLibrary 45nm. I want to modify the minimum spacing between only two wires of Metal4 to be from 0.14um to 0.07um, so I modified the minimum spacing of Metal 4 layer in LEF tech. file of the used library. If I want to do RC extraction after this modification, should I also modify min
ASIC Design Methodologies and Tools (Digital) :: 03-02-2017 11:59 :: oAwad :: Replies: 1 :: Views: 257
Whenever I open an existing Allegro layout or create a new one, when I attempt to create artwork (274-X Gerbers), I get a listing of the layers, but NO check boxes from which to select what layers I want to export the gerbers. See attached picture.
Could it be a graphic card issue as I noticed the aspect ratio is a bit wide and I do not (...)
Software Problems, Hints and Reviews :: 09-01-2016 04:58 :: ctocci :: Replies: 0 :: Views: 228
In the post layout extraction ( pex extraction ), if there's any problem occurs in pex means, we need to vary ( increase or decrease the resistance & capacitance ) in some signal lines..
I think we can reduce the resistance by using an higher metal instead of using metal 1 or 2.. Likewise, I need to know that " How to increa
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-18-2014 07:29 :: Blue Hawk :: Replies: 4 :: Views: 976
Of course this is ok. For the layout you have to consider the parasitics, and probably you'll have to change its value.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-03-2014 16:40 :: erikl :: Replies: 1 :: Views: 651
first: don´t be afraid of the switcihng technique. It works well. Most important is the layout design. short and wide traces, good power plane, multiple vias to gnd, use ceramic capacitors and good quality inductors.
there are ready to use step down switching modules as pin compatible replacement for 78xx.
If you (...)
Hobby Circuits and Small Projects Problems :: 05-22-2014 09:36 :: KlausST :: Replies: 2 :: Views: 836
I don' understand the layout. Gnd isn't even connected between power input and outputs. In any case there will be huge ground voltage drops spreading over to the controller side.
With small changes, e.g. rotating the relays by 180 degrees, the current pathes can be considerably improved. You need extra wide traces for 9 (...)
Analog Circuit Design :: 03-06-2014 22:24 :: FvM :: Replies: 7 :: Views: 499
First, your problem has nothing to do with common centroid. LVS cannot understand if you used such a technique.
1)Using multiplier must give you multiple objects. I have not encountered this before. Generally I use a mix of multiplicity and fingers.
2) You haven't connected the bulk of the transistors. You must add a contacts for the
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-15-2013 06:13 :: lamoun :: Replies: 3 :: Views: 965
Post layout analysis just takes care of and incorporates the extracted parasitics.
If you are interested in matching accuracy, you should run Monte Carlo simulations, if your fab/foundry provides the parameters for local, distance, wafer wide & wafer lot mismatch, as well as for process mismatch, s. e.g.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-23-2012 13:46 :: erikl :: Replies: 1 :: Views: 617
All this software is somehow useful for planar filter design, if you know the filter design methodology.
HFSS, Sonnet and CST can do EM simulation to analyze the layout when it is ready.
ADS and AWR can do both: fast circuit model simulation to develop the initial layout, and also EM simulation to analyze (...)
Software Links :: 05-12-2012 09:42 :: volker_muehlhaus :: Replies: 2 :: Views: 63
Your 20dB insertion loss at peak is far too high. Something is wrong with your interdigital filter, probably too wide spacing between the coupled lines. These oscillators in particular were built hundreds of times, mostly worked from the first try. The author optimized the circuit and the layout for the specified transistor, so if you (...)
RF, Microwave, Antennas and Optics :: 03-26-2012 18:09 :: rfmw :: Replies: 7 :: Views: 1149
I'm currently working on my senior project for my EE degree and I am designing a PCB that requires a bipolar power supply. Currently my PCB design (version 1, with a single ended power supply) has 4 layers, the middle being power and ground. The power planes are split into analog and digital planes as well, as noise is of concern. I'm (...)
PCB Routing Schematic Layout software and Simulation :: 12-17-2011 00:29 :: Ductapemaster :: Replies: 1 :: Views: 2750
how to design high speed opamp which can deliver 100mA of output current?
Do we need very wide mosfet at the last stage ?
e.g. when the W/L=1, the bias current is 1uA. then when 100mA then W/L=100000? how to layout??!!
and the large mosfet will cause low speed. how to high speed?
thank you a lot!!!
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-24-2011 07:53 :: xuexucheng :: Replies: 0 :: Views: 846
Can anybody help me for pierce oscillator layout. used as macro.
Actually i have done modifications in Pierce oscillator layout.
actually frequency is 20MHz. used wide metal routing for xtalin and xtalout nets, which are going to core pins, and done the sheilding for those nets.
subcircuits are (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-03-2010 11:42 :: gksivas :: Replies: 1 :: Views: 1252
I have a wide devices of W/L 120u/0.6u. I am planning to do multifinger device simply because of the area issue in layout.
What is the limitation in # of fingers ?
The PDKs which I know, don't put a limit on the # of fingers. More often the W/finger is limited, e.g to max. 10 or 20?m.
What is the exact u
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-07-2010 13:52 :: erikl :: Replies: 1 :: Views: 1553
The main important point you must consider in the BandGab layout is the parasitic resistance, rather than parasitic capacitance.
So you have to Route using mult-Stack-wide-metals between the BJT, Current mirrors, and Resistor Network
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-27-2010 17:58 :: Fady Atef :: Replies: 14 :: Views: 2803
Isn't easy to summarize the line guide for RF layout.
- minimize capacitance parassitcs in critical net
- take in account the coupling due to high frequency
- isolate and protect sensitive/aggressive blocks
- good contact of substrate
Anyway a good reference is "The art of analog layout" by Alan Hasting.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-09-2009 09:56 :: climber73 :: Replies: 5 :: Views: 1093
I designed a meander antenna in ADS layout and wish to improve the S11 by matching the input impedance at the port (50 ohm) thats Single mode transmission line excited. Any suggestions?
RF, Microwave, Antennas and Optics :: 08-12-2009 06:14 :: nerve_ece :: Replies: 1 :: Views: 1748
my Rdson of the main switch and synchronous switch is about 100mohms(0.35um technology). they are also very wide.
my question now is, how do we layout the switch so that even after extraction, the ON resistances does not increase too much.
could any of you give me an actual snapshot of the switch (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-05-2009 17:51 :: amriths04 :: Replies: 1 :: Views: 1078
Hi AdvaRes - I guess the process is indicating that if you are using a wide metal then some process need a multiple rows of vias i.e 10X10 VIA's or maybe that you need a large size of vias but normally large sized VIAs are used in bondpads or IOPADS.
I would suggest that if you used wide metal make a multiple rows and columns of vias, (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-27-2008 10:04 :: fixrouter4400 :: Replies: 6 :: Views: 2776
I was just wondering what all precautions we have to take while routing very low voltage signal traces (sub-micro volts and fA?s) .Also what are constraints regarding layout, power lines and decoupling supporting that.
Thank you so much in advaNCe!!
PCB Routing Schematic Layout software and Simulation :: 12-20-2007 11:38 :: smith_suez :: Replies: 1 :: Views: 1338
1)the tuning range is limited , coz it depends on the mechanical tuning
2) there are 2 usually used , topologies , serie feedback , and parallel , the parallel used alot in the SAT receivers
3) i don't know , how much it will deviate but it will depend on ur layout , and the prasitics
4) if u want wide (...)
RF, Microwave, Antennas and Optics :: 10-24-2007 12:18 :: khouly :: Replies: 4 :: Views: 1394
You are describing a layout trick for large (wide) transistors. It is much easier to explain if you can see the picture. Essentially, for very large W the poly gate becomes fairly long and thus has a fair bit of resistance associated with since it poly is fairly high in ohms/sqare compared to metal. You split up the large transistor into (...)
ASIC Design Methodologies and Tools (Digital) :: 05-04-2007 01:19 :: eternal_nan :: Replies: 1 :: Views: 1613
pls see the book
cmos circuit design, layout, and simulation
by r. jacob baker
if u get soft copy pass it to me pls
Analog Circuit Design :: 11-13-2006 15:48 :: wael_wael :: Replies: 2 :: Views: 1846
During ESD testing 4KV HBM the current pulse can reach up to 2 - 2.5A within 100-150nsec.
So for I/O it is better to layout power lines as wide as possible.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-17-2006 06:51 :: Fom :: Replies: 13 :: Views: 2595
This is my headphone amp built. A very good sound, extended bass and wide soundstage. If anyone wants to try it, mail me for pcb layout.
Hobby Circuits and Small Projects Problems :: 07-29-2006 14:55 :: RSK :: Replies: 0 :: Views: 1289
After I used many years Calibre and from time to time Dracula for layout parasitic extractions, now I have to do this with Assura.
I find few things that put me in a difficult position, and make to untrust Assura results. (Like a conffirmation that Assura don't work properly)
Description case 1:
I have two (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-26-2006 09:58 :: gabi71ro :: Replies: 0 :: Views: 888
I have designed a LNA for wide-band application. After finishing layout and postsimulation, i found mismatching of input and output make the noise figure deterioation. But ,presimulation shows matching is good. Is the result believable?
How to improve it?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-11-2005 07:21 :: lordfire :: Replies: 2 :: Views: 1050
I use layout Plus 10.3.0. in some cases we need to have a track that has a wide width (e.g. 60 mils for VCC or GND). but we may have components that have low pad spacing such as SMD ICs. if we want to route these tracks to these components, we may route the track with wide width (60 mils) to a point near the component pin (...)
PCB Routing Schematic Layout software and Simulation :: 10-14-2005 07:31 :: kashimonga :: Replies: 0 :: Views: 1513
the RF layout topic , it is hard to find in a book or article
it depends in many things
even the foundaries when providing u with models , it is valid for a shape of layout
and it depends very much on the width and length
so the transistors u donot have a real wide variaty of (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-16-2004 00:50 :: khouly :: Replies: 6 :: Views: 2400
hi after matching the two port atf36077 with s11=-9db,s22=-9 db at (8-12 ghz),without using the discontinuity,if i use the discon.the resuls change alot,if i neglect it,is it affect the layout and the s parameter results,also if i put lamda/4 for the gate and the drain ,it also affect the result.what i do pls help me
if i want (...)
RF, Microwave, Antennas and Optics :: 07-29-2004 21:11 :: abdoeng :: Replies: 4 :: Views: 1003