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Ldo Frequency Response

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13 Threads found on edaboard.com: Ldo Frequency Response
okay I think the answer was in general, focusing on the ldo itself. ldo in itself is a two pole system or can be higher depending upon the op-amp you are using. ldo is voltage sensing current source. actually in an ldo application you want to damp the response to get a stable output/current. The high (...)
I was reading about ldo. In there as the load current increases the non-dominant pole and RHP pole move to high frequency while the LHP zero doesn't change. I have no doubt in this. But what it says is that the transient response slows down as the load current increases because of the above statement. Could you please explain me this? I (...)
PSRR : Power supply rejection ratio What clock? Suppose a ldo will be designed for a system with different clocks, such as 10K 1.5M 12M 24M 48M and so on! So do I have to gurantee the PSRR of the ldo @ all the frequency above? In other word, how to decide the frequcy I care when I design evaluate PSRR
The most important frequency response of for the ldo circuitry is the magnitude/phase characteristic of the complete open loop (including all parts which are part of the loop). This simulation is necessary for evaluating the stability properties after closing the loop.
I guess he will use NMOS ldo for better efficiency.
I want to draw frequency response of a ldo circuit with ADS but I dont know how I can do it?
Hello everyone, now I am trying to optimize the load transient response of a ldo. But it seems like it is difficult to achieve good gain and enough phase margin at the same time in the feedback loop. I tried to increase the gain to improve the load transient response. But if the phase margin is not enough, the load transient shows
The dominant pole in the ldo without compensantion is the output pole of the error amplifier. The frequency response may be sufficient for your application without any compensation if the load charge won't be below a specific value (ie below 50-100 uA). If this is the case you may not need to worry with the capacitors, you will have a fast (...)
Hi, I'm facing a problem with my ldo: I thought evthg was ok, but then as I ran corners the phase response started to look a bit strange as you can see on the attached plots. At 125C and down to about 60C the phase starts at 0, then quickly goes up to a decent value and then behaves normally (edasim1.gif). If I run at 60C the phase starts at 180
can you upload IEEE paper robust frequency compensation scheme for ldo regulators or A capacitor-free cmos low-dropout regulator with damping-factor .. or Single Miller Capacitor frequency Compensation Technique for Low ... by the way , you make ldo by BJT or CMOS process Added after 2 minutes:
hello i need an advice from you. what methods of ldo compensation do you know? simple compensation with output capacitor and its ESR is not enough cause it's susceptible to process and temperature variations. it should add a left-hand zero and no pole into the frequency response. i found only one solution with VCCS regards
What's your need? A high speed error amp for ldo?
Hi all, I have simulated a ldo's open loop frequency response (break the loop at Vfb with ac input), and found its gain was about -40dB@DC. The error amplifer is a two stage op with open loop gain 65dB@DC, but the gain will reduce to -40dB once adding the PMOS power transistor into the loop. My questions are: 1.Should the loop (...)