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203 Threads found on edaboard.com: Ldo Not
Bond wire inductance is probably not a problem unless you are trying to make a ldo which can follow extremely high dI/dt on the supply-input path. But usually this job is assigned to the output filter capacitor which is more suited to the job. A "cap free" ldo would care more. Bond wire resistance is a real thing and at 200mA could amount (...)
Hi all, I have a problem when doing ac simulation. If my ldo is 1V output voltage with 1mA current, which kind of output load should I use in ac simulation (HSPICE)? 1. Using a 1mA current source directly ? 2. Using a resistor with the value of 1kohm ? Thanks. CD Hi, If you are using current source then it wil
i ordered the ic . I have trouble with components because most of them are not kept on stock . I get to components based on orders , and delivery times are long here... It's not worth to order by myself since i order only a few components (let's say 3 pieces of LT3080) so the shipping is more then the value of those components. That's why i order t
"High" isn't helpful. Quantify your expectations / requirements. ldo power dissipation is (VIN-VOUT)*IOUT neglecting ground current. ldo delivered power is VOUT*IOUT ldo efficiency is POUT/(POUT+PDISS). For a 5-3.3V your nominal eff% is 3.3/5 or 66%. not heinous, not fabulous. Probably on a par with a (...)
Consider "noise" a vague term. You should better analyze interference level versus frequency and specify your clean power supply requirements. Different ldo have different degree of ripple rejection. Ripple rejection at the typical SMPS pwm frequencies is not generally good and mainly achieved by output capacitors. Respectively a good LC filter
OK, I think a ldo will do the job. For instance ADP333, but there are many other. This one has the benefit that it's stability is almost not affected by the ESR of the output capacitor.
Hello people! I am wondering about the drop out voltage of the next particular ldo. I am planing to use a LT1634-5 to make stable a power supply of 5V. It is going to be admissible to have a drop out voltage of 100mV. However having a look to the datasheet of this component i am not able to find this specification. And furthermore I simulate wit
i used the transformer from WURTH ELEKTRONIK ( Transformateur d'isolation with 3 W,vin 85V ? 265V,vout 5V) , standard power diodes 1N4007, capacitor2200uF, regulator from TEXAS INSTRUMENTS LM2940IMP-5.0/NOPB Régulateur ldo , 0V ? 26V, 500mV Dropout, 5Vout, 1Aout, SOT-223-3
I can happily work the amp from 12 volts to a safe value of 16 volts There is just about enough overhead to use a 12V regulator in that case. Something like a 78S12 will give a constant 12V out with input ranging from 14.5V up to about 30V and can handle 2A. It will need a heat sink but not a huge one. An ldo regulator would
Hello guys, I appreciate very much If you could help me. I can't understand the following: I know that the dropout voltage of an ldo is related to the minimum input voltage necessary to maintain regulation. So, If a datasheet says the dropout for a specific regulator is 100mV, and the output voltage is 3.3V, I should get 3.3V with a minimum 3.4V
There's mismatch and there's mismatch. not all of it stems from simple VT scatter. You may find that devices operated in saturation (considered by most to be a Good Thing) are more sensitive to things like variations in Leff than VT. You can attack this by looking at mismatch and process variation separately / orthogonally. In a piece-part ldo
Your specification is incomplete and unclear. What is the required output voltage? Is a variable output range as well? Even an ldo linear regulator has a minimum dropout voltage, an input voltage of only 0.3 volts would like not be sufficient for voltage regulation except for a few millivolts output. BigDog
Hi, ...from Layout perspective not from layout perspective...but maybe from the ldo. Usually in each ldo´s datasheet there is a chapter about the output capacitor. Read the datasheet. There is no general rule.. it really depends on the type of ldo you use. Klaus
ldos cannot respond to infinitely fast step loads. The capacitor bank qualities need to take up the slack, and this means not just C but ESL/ESR. The loop feedback, if accessible, is also worth tweaking. It's a team sport, basically.
Hi, Did you read the datasheet? --> LM317 is specified for only 1.5A. **** 5V input and 4.2V output with 2A max current. This means the dropout voltage of the regulator must be less than 0.8V. Expect a dropout voltage at the LM317 of at least 1.5V (see chart "dropout voltage" in datasheet). So the LM317 Can neither deliver the current , nor deli
I think an ldo pass-Tx should always operate in saturation region to allow for good regulation. If - at high output current - its operation point moves below its saturation voltage into the triode region, the ldo gain gets worse, so the output error increases.
Why not use a 5V adapter and regulate down with an ldo regulator like a LF33 or similar?
Hello I am starting with new project and would like to use PIC18F97J94 (100pin TQFP). Device will be used for communication with PC over USB or BLUETOOTH. Device will be powered from USB power supply (+5V) or alternative battery supply (voltage from 4V to 9V). I will step-down any input voltage to 3.3V with ldo fixed linear voltage regulator,
7806 is not the best ldo to use here. edit** Reason? ldo will drop 2.5V at 1.5A at 85'C , which means you need 8.5 min anyway but chances are your load demands more than 1.5 and that's causing shutdown on starting. Power dissipation (9-6V)*1.5A= 4.5W is a big problem A heatsink will improve overtemp condition, but not (...)
Designing an ldo assumes you need low dropout voltage not low power loss. When the dropout is not low, design of thermal power loss is key. Pin = 10V*300mA = 3W Pout = 4.5* 300mA = 1.35W Ploss in ldo = Pin-Pout= 1.75W Efficiency= Pout/Pin=45% No heatsink on a TO-220 is... Rja = 60 deg C/W Rjc = 5 deg C/W With no (...)
You have chosen an adjustable ldo as a voltage source with no current sense resistor, so that will not work. The concept in ldo's is to regulate the feedback to match the internal Vref. For CC operation this would have to be 1.21 across a current shunt , which dissipates too much power. Standard Current shunts go for 75mV max drop but this (...)
Unless you know that your supply is regulated , expect up to 40% variation from full load up to no LED load. So choice of solution is best with ldo for efficiency and regulation NPN with zener is ok but not 1% as shown as they also have 7% tolerance typical at a max current and maybe 5% for a 1W type with less dissipation. A
I thought it was the ldo that was 0.6V not Vdd. In any case you just want to generate a low voltage with a uA load? How about 3V and a resistor divider?
You can make a very supply insensitive bandgap by placing it under local regulation - an internal ldo. Even a crude one can be very effective, it doesn't need good tempco itself (bandgap can take that out), only to cut supply swing from 10% to <1% and this is pretty doable (have done, good results). A supply insensitive ramp is not as easy but if
What is the ICMR or you Op-amp? What is the Output Voltage that you are targeting? Do the two match? You should have designed the entire ldo together and not in parts (Error Amplifier and then Power Transistor)
Probably this peak amplitude is much higher (depends to your ac simulation step) and it could seriously deteriorate overall performance of system. Check on transient simulation the behaviour of ldo output.
hello can anyone tell me how to decide input voltage range n reference voltage for designing ldo in 45nm CMOS technology??
Current sensors are always designed for 50 or 75 mV drop max for thermal reasons. If 24V@40W then Imax= 1.67A and 50mV shunt would be 0.05V/1.67=0.03 dissipating, I^2R=50mW Obviously this circuit uses a PTC and would only be used for OVP and your supply is over-voltage!! It is not intended to be used as an ldo. The zener is too low and would get
Vdd supports 15V Logic and 3 Terminal regulators will source current but not sink any, hence if the ldo output is pulled up, it doesn't take much current to do so. However the driver chips indicates. Vss Logic supply offset voltage w.r.t. COM = Vcc -25 & V + 0.3 and Iqdd Quiescent for Vdd supply current = 30 uA max. - meaning it s
Hi, Can anyone recommend onchip ldo architecture with good PSRR performance? I did some literature search but they either need too big output cap to be integrated, or multiple ldos in cascode which is not practical for low supply operation. Thanks.
For transformer with 9V, 18V, 54VA your sharing one rectifier is not good for efficiency What are the worst case load currents? I+5, I+12 DC. The ldo will reject EMI easily but min. Drop for chosen regulator I recall is >2v , 5V will have biggest drop and get hot, so VI drop must be dissipated in heatsink.
zeners are not efficient nor stable compared to bandgap reference diodes used in all ldo's (LM317 type and many others) Zeners must draw more than the worst case load to ensure when loaded there is still enough current to get past the knee in the zener. Then when no load, that current * voltage can lead to thermal problems for high power. So
Hello Im trying to wire a atmega with a 3.3 ldo and a 3.7v lipo battery and its charger. For the lipo charger i thought to use the MCP73831 and for the ldo not sure yet. The main point is powering the atmega at 3.3 and changing the 3.7 lipo! possibly with less components as possible. I would appreciate some advise. thanks
Thank you. I need the resistor for biasing circuit for my ldo. Could you tell me how to make resistor from transistor?
for example:
Hi all: I wish a OPA for a ldo and the OPA operation voltage is 5~20V. For high voltage, I use LDMOS to design the OPA, but I found there isn't have vdsat parameter in my pdk. Do you have any suggestion or solution to know the LDMOS is in saturation region or not? Thanks for your reply. mpig
in standard cmos process . how to working in na current ? I ever try use mos current mirror when bias cureent less < 0.1ua some die have fail yield loss .. even simulation by hspice is ok , but real silicion have fail die how to design total 20na ldo ?? bandgap need current , OPA also need operation current
:grin:Hi all I am designing an ldo an I want to test its stability over the whole load current. How can I do that?. I thought of using a ramp for the load current does it work? Any help is appreciated Greetings
I have an ultra low noise ldo and filtering on the supply, decoupling is good, have a 100pF and 1nF everywhere necessary. The amplifier by itself works perfectly, its only when it gets the input signal from the LO that it does this - - - Updated - - - 1K resistor to ground?
Dear all, I design a Low dropout voltage(ldo) regulator recently. But I doubt that my design will work when I see the PSRR simulation result. The simulator which I adopted is Hspice. I set the supply voltage vdd with dc bias voltage plus ac singal (V_PSRR vdd gnd dc vdd ac=1v) After running the ac simulation,I probed the output termi
How about a simple 3.3v ldo? Available as a 3 pin SMD, so it cant get much lighter.
Yes, I agree with you, the application is noise sensitive, since it will be operating close to a 7500W SMPS, and I am craving to use the 0.01u ceramic!! The reason I am hesitant is that the LP2980 datasheet (pg 10, attached) suggests not using ceramic capacitors below 2.2 uF in the output, since low ESR values co
why not use for example ldo regulator with max 1uA quiescent current? For example TI series TPS782XX example 3V: TPS78230DDCR You have stable voltage in ENABLE pin for switching ON/OFF peripheral.....
Hi jsherman, I am not sure if I understood correctly, but your problem seems to be how to supply a 5V micro with a 9V battery, right? I think one of the easiest ways is using an ldo, like LM7805A (take a look at this document: The LM7805A o
Hello all i want to find out gain and phase margin of an in order to that i have done ac analysis by breaking the loop and placing inductor and Coupling ac to the + terminal as shown here93685. Is this the right way is my first question Yes - for my opinion, it looks good. [QUOTE=k
Hi kishore, ldo design is a wide theme, and I think this is not the right place to educate you - nor do I have the time to do so, sorry. There are a lot of papers available on all these subjects, study them! Run your simulations, stability and others, and come back with concrete questions, if you need help.
I am designing ldo with PMOS as pass transistor , It should support current upto 50mA. SO width of PMOS should be very very high. But in cadence maximum width i can give is 100u. :cry: i need ratio of 6m/1u W/L. How to do that in cadence?
The big pass device will leak, and that leakage has to go somewhere or the output will go out of regulation, high. This current can be taken up by the feedback network if low enough impedance. Some ldos have a sort of class AB output with a sink device (helps also with low-load transient response, keeping the "load pole" under control) and these w
No, you can't. The tolerance between 7805 will cause huge inbalances in current. That's the best case. Worst case is that the control loop goes nuts even though I assume that to be rather unlikely with a 7805? I'm not an expert here. In addition, depending on your application (ie input voltage), an ldo may not be a very good solution for a (...)
Paralleling ldos is not a very good idea. Minor differences in tuning/output voltage between the two will lead to great load imbalance. That said, you're already burning over 1,7W here. Maybe time to switch to a buck solution?