1000 Threads found on edaboard.com: Level Trigger And Edge Trigger
everytime we talk about positive edge trigger and negative edge trigger flip flop.
how do we design a postive edge trigger flip flop?
how do we design it to trigger at the 5th (...)
Analog IC Design and Layout :: 03-13-2006 10:37 :: surreyian :: Replies: 3 :: Views: 2141
1.How can I check the setup time and hold time for a timing path. the first FF is positive edge trigger, but the end FF is negative edge trigger one.
2. The hold time is still depended by clock frequency like normal?
ASIC Design Methodologies and Tools (Digital) :: 02-07-2012 03:53 :: liwei039 :: Replies: 3 :: Views: 1060
i am writing a protocol for 89s52 and using assemly in Keil. I want to use 89s52's external interrupts in edge trigger mode(by setting IT0 and IT1 ). But Keil ignores my edge triger setting, It still work as in level activated mode.
For example when i begin (...)
Microcontrollers :: 01-11-2005 17:05 :: volkan :: Replies: 5 :: Views: 977
manasiw2 u cant do that, if u tie the clock to the select pin using a single MUX then if become latch no DFF cause the output will change as long as the input is changing if the clk is still high.
It become level trigger not edge trigger.
I think kanagavel_docs have provide a good (...)
ASIC Design Methodologies and Tools (Digital) :: 11-06-2007 00:57 :: laststep :: Replies: 7 :: Views: 3134
That's pretty vague; could you be more specific? How fast? Voltage levels? One way is to use two flip-flops and an XOR gate.
Electronic Elementary Questions :: 12-10-2013 09:14 :: barry :: Replies: 2 :: Views: 165
It is the same.Looking at real parts reveals important differences.Mostly voltage supply requirements and hysteresis levels.
ASIC Design Methodologies and Tools (Digital) :: 09-16-2009 17:19 :: Prototyp_V1.0 :: Replies: 6 :: Views: 6229
H i Friends here is one more digital question any one tell me the solution
Design a square wave generator which takes only one positive edge trigger.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-29-2009 01:35 :: xorgate :: Replies: 0 :: Views: 918
The various Schmitt trigger buffers and inverters that are available have fixed hysteresis. The Schmitt trigger is a comparator that has positive feedback to provide its hysteresis (difference between the high and low reference levels). You can build a Schmitt (...)
Electronic Elementary Questions :: 11-02-2009 11:39 :: Kral :: Replies: 5 :: Views: 2955
What is the difference between normal Nand gate and Schmitt trigger Nand ?
Does it is interchangeable in an application ?
Analog Circuit Design :: 02-14-2010 07:07 :: vinodquilon :: Replies: 1 :: Views: 2137
For a design, if all clock domains are rising-edge trigger, shall I account for falling edge skew balance when CTS?
ASIC Design Methodologies and Tools (Digital) :: 05-24-2011 08:42 :: chris_li :: Replies: 0 :: Views: 705
How we can identify whether a communication (SPI/I2C etc) is level triggered or edge triggered w.r.t clock?
Electronic Elementary Questions :: 11-23-2012 08:53 :: myatham :: Replies: 1 :: Views: 408
There are few points to be note here....
1. Make sure that the interrupt is not masked. and note its priority!
2. Whats the nature of interrupt I mean level sensitive OR edge trigger or both??
3. You are using switch that mans you may need debouncing!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-06-2005 00:27 :: nand_gates :: Replies: 1 :: Views: 847
edge-triggered storage element is called F-F, and level-triggered storage element is called latch. Some puls-triggered F-F is used in dynamic logic circuits so as to save transistor counts, where the internal state of the F-F is changed (...)
Electronic Elementary Questions :: 04-09-2007 00:48 :: yjkwon57 :: Replies: 8 :: Views: 11903
I have got a situation where is triggering is continuous, i have to generate a 1 second pulse by triggering through a continuous high level voltage, there is no falling edge till the circuit gets reset. Not getting any clue.. :-|
Analog Circuit Design :: 02-27-2011 07:39 :: memustufa :: Replies: 1 :: Views: 1084
Free to download and try.
Pocket PC version:
MultiInstrument consists of a sound card dual trace oscilloscope, a sound card real time dual trace spectrum analyzer, and a sound card dual trace signal generator and can run them concurrently.
Software Links :: 09-13-2006 11:58 :: webhopper :: Replies: 0 :: Views: 657
Why the cell level DRC and LVS by the P and R tool insufficient ??
Electronic Elementary Questions :: 08-26-2007 08:48 :: mujju433 :: Replies: 2 :: Views: 685
Would like to know how to do system level design and simulation, and what kind of tools are popularly used?
Analog IC Design and Layout :: 10-08-2007 23:01 :: walker5678 :: Replies: 12 :: Views: 1291
Download PC version:
Download Pocket PC version: is a powerful sound card based multi-f
Software Links :: 12-24-2007 08:46 :: webhopper :: Replies: 7 :: Views: 2334
Creating PMLs Automatically
1. Draw a PML base object at the radiation surface.
2. Select the faces of the PML base object to turn into PMLs.
Select only external, planar faces and exclude faces defined as symmetry boundaries.
3. On the HFSS menu, point to Boundaries, and then click PML Setup Wizard.
The PML Setup wizard appears.
Electromagnetic Design and Simulation :: 08-20-2008 13:17 :: lkminz :: Replies: 0 :: Views: 851
what are level transistor and how they work and implemented,
NEED SOME URGENT HELP
Microcontrollers :: 05-06-2009 10:14 :: fastian :: Replies: 0 :: Views: 606
Yes. You had better complete P&R in block. and then in top level, all the blocks can be instanced as macros.
In general, the power planning for block is nothing in particular. You need only to give a power supply to them in top level, as the macros in your design.
ASIC Design Methodologies and Tools (Digital) :: 05-22-2009 18:45 :: semi_jl :: Replies: 3 :: Views: 1180
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EDA Jobs :: 03-12-2010 01:27 :: intersoft05 :: Replies: 1 :: Views: 3228
Can we calculate capacitances required for mosfet small signal analysis from berkley MOSFET models level 53 and 54. If yes please let me know how to do it.
Of course it is possible. See the BSIM manual how it is done. This i
Analog IC Design and Layout :: 10-30-2010 10:05 :: erikl :: Replies: 1 :: Views: 667
low level just means more detail. One persons low level might be someone elses high level.
Show your top level HDL code to a java person and they'll call it low level. ;)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-15-2012 09:39 :: mrflibble :: Replies: 4 :: Views: 499
I have worked on project of Water level sensor and Motor Control and successfully completed.
Now I want to further add features to it... Please tell me suitable features
Microcontrollers :: 05-09-2013 07:17 :: RONAK ALI :: Replies: 21 :: Views: 1009
Free to download and try. The price is at US$49.95
Pocket PC version:
It consists of a sound card dual trace oscilloscope, a sound card real time dual trace spectrum analyzer, and a sound card dual trace signal generator and can run them concurrent
Software Links :: 06-28-2006 06:34 :: webhopper :: Replies: 0 :: Views: 689
I want to add;
level trigger interrupt cannot recognize very short time pin signal .
on the other hand edge trigger can recognize any short duration pulse .
ASIC Design Methodologies and Tools (Digital) :: 11-15-2005 15:32 :: Davood Amerion :: Replies: 6 :: Views: 9914
I know that it is not advisable to use gated clock partly because of glitches caused by other changing signals.
I am curious to know if glitches can happen when I take the edge of a non-clock signal(let's say, output of combinational logic) to trigger some event. If there is a problem, how do I avoid it when using edge (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-04-2008 23:19 :: anthonius :: Replies: 1 :: Views: 505
My name is Martin, and I am not very experienced with electronics. I know what the different components do in theory (transistors, capacitors, resistors, diodes, ...), but going from that and designing a circuit is a big leap for me. This is why I am here. I am trying to design a circuit (not homework, just hobby), which has to do the followi
Electronic Elementary Questions :: 09-11-2012 09:43 :: ex.digital :: Replies: 3 :: Views: 569
I measured a moble phone test item "ORFS in receiver band"
One of the setup that I don't understand.
I connected 8960 "trigger out" to spectrum analyzer "Gate trigger Input".
and set it as trigger slot=7 & gate (...)
RF, Microwave, Antennas and Optics :: 03-02-2005 06:43 :: ajhsu :: Replies: 1 :: Views: 864
Only one. Otherwise, it's a buffer.
When level is high, latch gets whatever value coming in. When level is low, it won't latch new value (it stays at old value)
ASIC Design Methodologies and Tools (Digital) :: 03-17-2006 12:59 :: stevepre :: Replies: 10 :: Views: 802
edge trigerring is suitable if your system has
1- small noises
2- require fast response
level trigerring is the best if your system has
1- multi sources of noise (Long distances, noisy inviroment ,...)
2- require slow response
Other Design :: 01-30-2007 09:23 :: msadek_eng :: Replies: 10 :: Views: 1362
i am trying to modify an old synthesizer to accept a 0v / 5v or 15v trigger input to trigger a sample / hold circuit.
currently there is a slider that controls the sample time (frequency) of a sample and hold circuit. the dc output on scope after the slider/op amp circuit looks like a -13.5 / +13.5 v (...)
Analog Circuit Design :: 03-16-2010 12:15 :: ghostarcade :: Replies: 4 :: Views: 910
It's instructive to review the transistor or gate level schematics of usual edge sensitive flip-flops. You'll realize, that they are made of two level sensitive building blocks (latches). See the HC74 schematic from the TI datasheet. You can replace two transfer gates by a multiplexer, if you
ASIC Design Methodologies and Tools (Digital) :: 05-23-2010 04:55 :: FvM :: Replies: 9 :: Views: 1841
I have a question on scope?
==>If there are two signals need to measure on a scpoe, one is low frequency signal
and another is high frequency signal, why we need to choose the low frequency
signal as trigger source?
Professional Hardware and Electronics Design :: 07-11-2010 11:17 :: mpig09 :: Replies: 2 :: Views: 1232
You can configure a diode, capacitor and resistor to create a ramp effect which will either (a) extend a positive pulse by decaying gradually to zero, or (b) slow the upward transition of a pulse so as to cause a delayed high.
Then you can feed the ramp waveform to a schmitt trigger, and adjust the level (...)
Analog Circuit Design :: 06-10-2011 21:20 :: BradtheRad :: Replies: 1 :: Views: 557
I am using a logic analyser to measure a low frequency signal of period 2s.I am able to observe the signal but,I am not able to trigger on a rising/falling edge.The trigger point appears to be random.For much higher frequency signals I am able to do edge (...)
Electronic Elementary Questions :: 08-11-2011 07:19 :: nicky.r :: Replies: 1 :: Views: 322
I am Sudarshan. I amm new to Eagle software.
I need to use PTVS3V3S1UTR (Zenor diode - package - SOD 123W) and 74LVC2G14GW (pacakage - SOT -363). unfortunately I couldnt find them in the eagle library. So is there any way ?
Can I use another devices with same foot print/package ?. For example, my Schmitt trigger foot print is SOT (...)
PCB Routing Schematic Layout software and Simulation :: 06-01-2012 10:32 :: sudarshanliu440 :: Replies: 2 :: Views: 1839
Please excuse me, I didn't get you. actually what your doing there?
I guess you need two signals from op-amps (using two external interrupt.. please note it external interrupt is only a trigger like rising or falling edge of the signal).you wish to calculate time difference between both interrupt events. am I right friend? (...)
Microcontrollers :: 06-08-2013 14:13 :: Jinzpaul4u :: Replies: 7 :: Views: 350
Can any one tell me the transistor level circuit design for this truth table, let me know how to implement
Analog Circuit Design :: 11-19-2013 01:32 :: urimi :: Replies: 6 :: Views: 433
I gave the generic reasons for needing the option for both polarities, but if you still want more, I have to get into specific applications. OK, here is one. RS-232 serial communication is based on a signal that is negative in its resting state and goes positive when a character starts to be transmitted. The RS-232 signal is normally processed t
Electronic Elementary Questions :: 07-20-2014 16:10 :: Tunelabguy :: Replies: 14 :: Views: 352
What are the limits of the prf detector? If these are logic level pulses or can be converted to logic levels by a comparator you can use a counter which is reset periodically and then examine the count value.
Microcontrollers :: 05-07-2003 19:45 :: flatulent :: Replies: 7 :: Views: 1135
Look at the digital waveform out of your comparator to see if it is oscillating on the transitions.
To add the hystersis to your comparator circuit, put a large value resistor from the digital output to the non-inverting analog input. Then put a small resistor from the non-inverting analog input to ground. Apply the signal to me be measured to
Professional Hardware and Electronics Design :: 05-24-2003 13:44 :: flatulent :: Replies: 5 :: Views: 2321
you can debounce by software.
Normally slow signals can be triggered to with an interrupt. The moment when the trigger occurs is not precise to the edge of the signal any more. This can now drift by temperature etc.
One thing you can do is leave away your capacitor. when first receiving a rising (...)
Microcontrollers :: 10-16-2003 11:30 :: Aoxomox :: Replies: 6 :: Views: 1671
does somebody have 'drag and drop' asm library for decoding 1/3-2/3 pulses ?
bit 0 is 1/3 x total period logic level 0 and 2/3 x total period 1
bit 1 is 2/3 0 and 1/3 1
this code can be inverted, no matter
Microcontrollers :: 01-14-2004 11:16 :: tgq :: Replies: 3 :: Views: 1288
We know that vcs is based on event-driven. But what's the arithmetic ?
" = " assignments trigger events,and "<=" assignments trigger events,
how does vcs deal with then?
Thanks a lot!
ASIC Design Methodologies and Tools (Digital) :: 08-31-2004 09:18 :: zhangpengyu :: Replies: 2 :: Views: 828
Can you give a snippet of your source code? It's hard to tell without seeing what's wrong.
I guess that you have, for example, a level-sensitive register (i.e. level-sensitive latch) and you are trying to assign a value to it using an edge-sensitive declaration.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-03-2005 09:01 :: Big Boy :: Replies: 4 :: Views: 1209
The Simulink block "Variable Transport Delay" is found in 6.5 and 7.0 at least and could model a DLL.
The problem could be that the "Variable Transport Delay" uses a discrete time circular buffer. That is to allow logic, real and complex values to path at the input at a higher rate than the delay time. That limit time resolution to (...)
Analog Circuit Design :: 10-12-2005 10:47 :: rfsystem :: Replies: 5 :: Views: 3719
I have a 6MHz noise sine wave signal from an oscillator which I would like to rectify. What would be a suitable schmitt trigger? Can they use analog input signals at this frequency? If so, can someone suggest a part number please.
Analog Circuit Design :: 05-11-2006 07:11 :: svensl :: Replies: 2 :: Views: 1042
If your clock spike is not large and locate on high or low voltage level (not on edge), schmitt triger inverter is a good choice.
ASIC Design Methodologies and Tools (Digital) :: 09-11-2006 23:50 :: laglead :: Replies: 5 :: Views: 948