10 Threads found on edaboard.com: Library Tetramax
Look at the Customizing Simulation library for ATPG, on solvnet or TMAX online help.
ASIC Design Methodologies and Tools (Digital) :: 03-15-2013 08:31 :: maulin sheth :: Replies: 3 :: Views: 843
I have the following code for path delay test generation:
read_netlist ../../library/saed90nm.v -library
add_clocks 0 CK
ASIC Design Methodologies and Tools (Digital) :: 11-19-2012 11:01 :: samankiamehr :: Replies: 1 :: Views: 1001
tetramax uses Verilog library to build fault models.
Netlist Formats, Testbenches, and Test Patterns Interfaces
tetramax ATPG supports popular industry standards for netlist and test pattern formats:
ASIC Design Methodologies and Tools (Digital) :: 07-14-2011 06:45 :: kornukhin :: Replies: 3 :: Views: 1638
I need to generate test patterns for same circuit in different operation condition. I checked tetramax- and found out that it takes Timing libraries only in Verilog format.
I have just one timing library in verilog. How do I generate one library for different different operating conditions?
Thanks and Regards,
ASIC Design Methodologies and Tools (Digital) :: 06-09-2011 00:33 :: dhaval4987 :: Replies: 0 :: Views: 703
I use tetramax to write out pattern file in two kinds, stil and v,that is write_patterns -f verilog_single_file or write_paterns -f stil . Now I want to verify whether the generated patterns are right or not and I simulate it by adding the verilog_single_file ,dut module ,library module and spf file to Modelsim. And these are my quest
ASIC Design Methodologies and Tools (Digital) :: 04-28-2011 08:05 :: Hvyikey :: Replies: 1 :: Views: 775
You can synthesize your RTL, make formal verification and static analysis without any simulation. But I'm not sure about input file format for Formality (if it's not verilog nor VHDL you can use this flow).
But if you are going to make any simulation you need to ask your library vendor about any rtl (verilog or vhdl) files.
ASIC Design Methodologies and Tools (Digital) :: 11-15-2010 09:24 :: kornukhin :: Replies: 5 :: Views: 1108
If some one have tried using lsi_10k or other lsi libraries in synthesinzing design using synosys DC he might have faced the problem either dring the time of simulation using VCS or may be during the time of test pattern generation using tetramax.
I am facing the similar kind of problem while generating test unsing T
ASIC Design Methodologies and Tools (Digital) :: 06-06-2009 09:12 :: jayTudu :: Replies: 0 :: Views: 1038
we have license for
HDL Compiler Verilog
Physical Compiler Ad
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-29-2007 03:29 :: mariaR :: Replies: 5 :: Views: 1357
currently I encounter a problem regarding tetramax test simulation library, but I only have Mentor FastScan ATPG library.
could somebody introduce me how to model ATPG primitive for Synopsys tetramax especially Bidirection PADs.
-- or somebody could give me experience or example. how to convert FastScan ATPG (...)
ASIC Design Methodologies and Tools (Digital) :: 03-29-2006 04:41 :: cheelgo :: Replies: 1 :: Views: 1988
When i read in the library model netlist, it reports that there are unsupported construct. and then there are a lot of Unconnected module internal nets
What should i do with such problem? thx
ASIC Design Methodologies and Tools (Digital) :: 09-09-2005 02:54 :: zjwang :: Replies: 4 :: Views: 1678