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## Linear Feedback Shift Register |

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22 Threads found on edaboard.com: **Linear Feedback Shift Register**

Yes,
Implement a **linear** **feedback** **shift** **register** and make it your state **register**.
- - - Updated - - -
process ( LFSR ) is
begin
case LFSR is
when "000" =>
-- do something
when "001" =>
-- do something
when "010" =>
-- do something
when "011" =>
-- do something
when "100" =>
-- do some

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-24-2017 14:34 :: shaiko :: Replies: **1** :: Views: **261**

THe Pseudo Random-Bit Generator Source or PRBS is defined in CHapter 5 of the manual
There are many variables based on **linear** **feedback** **shift** **register** (LFSR)
Certain comibinations of taps and length of **shift** **register** are chosen for "maximal length sequence" (MLS) YOu may only be concerned (...)

Analog Circuit Design :: 06-19-2014 18:59 :: SunnySkyguy :: Replies: **4** :: Views: **839**

Can anyone help me understand that how does a LFSR (**linear** **feedback** **shift** **register**) implement division required for CRC (cyclic redundancy check) ?

ASIC Design Methodologies and Tools (Digital) :: 07-01-2013 04:43 :: e-bedlam :: Replies: **1** :: Views: **472**

Is it the same as the white noise which means the power is equally divided in the whole frequency range?
If so, how does it come? Any reference is preferred.
Now I've built a pseudo-random sequence using **linear** **feedback** **shift** **register**(LFSR), and I'd like to check its power spectral, is it possible to make it out using (...)

Analog Circuit Design :: 12-17-2011 11:07 :: bsaqycx :: Replies: **0** :: Views: **484**

The protocol specification usually defines CRC in hex or polynomial notation. For example, CRC5 used in USB 2.0 protocol is represented as 0×5 in hex notation or as G(x)=x5+x2+1 in the polynomial notation. This CRC is typically implemented in hardware as a **linear** **feedback** **shift** **register** (LFSR) with a serial data input

ASIC Design Methodologies and Tools (Digital) :: 11-30-2011 17:02 :: yura717 :: Replies: **3** :: Views: **968**

Usually, a **feedback** **shift** **register** is the answer **linear** **feedback** **shift** **register** - Wikipedia, the free encyclopedia

Hobby Circuits and Small Projects Problems :: 03-03-2011 19:46 :: FvM :: Replies: **4** :: Views: **2075**

For maximum length LFSR polynominals, see **linear** **feedback** **shift** **register** - Wikipedia, the free encyclopedia
If you want other than maximum length PN codes, you should tell a specification first.

Digital communication :: 11-14-2010 14:05 :: FvM :: Replies: **1** :: Views: **1085**

I have code for **linear** **feedback** **shift** **register**. It is not a random number generator in the strict sense. But must be useful in some cases.Download it from opencore.org:
LFSR-Random number generator :: Overview :: OpenCores

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2010 13:57 :: vipinlal :: Replies: **3** :: Views: **3204**

i want vhdl code for signature analyzer for built in self test circuit... i can use 8 bit **linear** **feedback** **shift** **register**(LFSR) na?i am trying using 8 bit LFSR

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-15-2010 06:16 :: divsec :: Replies: **0** :: Views: **1507**

Please help guys.. i need to perform the run and correlation property on a stream of bits that has been pseudorandomly generated.
I have used the following piece of code: e.g x= randn(10,1)>0.5 to generate random bits of 0's and 1's. Is this the correct way of doing it or do i need to pass through the **linear** **feedback** **shift** (...)

Digital communication :: 12-10-2009 15:33 :: dammadmin :: Replies: **0** :: Views: **1093**

Signal source is a (pseudo-)random sequence generator.
Oscilloscope must have external trigger input, use sequence generator clock as trigger signal.
To measure, hook up oscilloscope to end of transmission media (receiver side).
To implement a sequence generator in HW, google '**linear** **feedback** **shift** **register**" for (...)

PCB Routing Schematic Layout software and Simulation :: 08-08-2009 11:17 :: alenze :: Replies: **1** :: Views: **3188**

Hi All,
I have to write the scrambler code in verilog. The scrambler is LFSR(**linear** **feedback** **shift** **register**) based.
The 23-bit polynomial for the LFSR is G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1
The main problem I am facing is finding the value of LFSR after 8 serial clocks (1 bit advanced in each clock).
There are 2 (...)

ASIC Design Methodologies and Tools (Digital) :: 04-11-2009 11:10 :: aman_geek :: Replies: **6** :: Views: **10188**

The keword is LFSR (**linear** feeback **shift** **register**). A **feedback** expression can be selected to achieve a maximum sequence length, this means all possible codings in the **register** execpt the all zero case, corresconding to a 2^n - 1 pseudo random bit sequence length.
You can find e. g. VHDL code examples at (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-01-2008 14:41 :: FvM :: Replies: **1** :: Views: **1194**

Hi Neetin,
2. How we choose cherterstic polynomial for lfsr?
The characteristic plynomial is the LFSR connection which will give the maximum number of random values before it starts to repeat the values. Each LFSR will have a characteristic polynomial, which is pre-determined. There are equation to find that, which I don't remember just

ASIC Design Methodologies and Tools (Digital) :: 03-24-2008 09:20 :: vlsi_eda_guy :: Replies: **7** :: Views: **2631**

Good links to understand LFSR concept:

ASIC Design Methodologies and Tools (Digital) :: 05-22-2007 03:46 :: barkha :: Replies: **1** :: Views: **3685**

Hi All,
I am designing "Data Randomizer" in verilog in which i am using a polynomial.
G : x16 + x13 + x12 + x11 + x7 + x6 + x3 + x + 1
My Query is : On what basis we choose a polynomial equation and if we implement this equation using LFSR(**linear** **feedback** **shift** **register**) where to place tabs for output ?

ASIC Design Methodologies and Tools (Digital) :: 01-05-2007 06:38 :: kunal1514 :: Replies: **0** :: Views: **732**

random pattern?? -> use LFSR (**linear** **feedback** **shift** **register**)

ASIC Design Methodologies and Tools (Digital) :: 02-23-2006 10:26 :: eda_wiz :: Replies: **1** :: Views: **1237**

A **linear** **feedback** **shift** **register** (LFSR) is an easy way to generate a pseudo-random bit stream in hardware by using a **shift** **register** and XNOR gate. Here are a couple of Xilinx app notes, and HDL examples:

Digital communication :: 12-19-2005 08:30 :: echo47 :: Replies: **3** :: Views: **3190**

hi,
try to find this excellent book covering your questions: Solomon W. Golomb, **shift** **register** Sequences, Aegean Park Press, California, 1982.
XOR gates give, in the case of binary system, **linear** addition, which is needed to form a **linear**-**feedback** **shift** **register**s, (...)

Elementary Electronic Questions :: 08-09-2005 11:22 :: rfmw :: Replies: **3** :: Views: **1039**

I see this problem like this:
every tap (in your case x**14 and x**15) in LFSR (**linear**-**feedback** **shift** **register**) of your polynomial adds one additional error in the receiver. So the sum of all errors is three since original error plus two tap errors equals three.
I'm not sure about your code since I don't understand the (...)

Digital Signal Processing :: 07-15-2005 14:02 :: rfmw :: Replies: **6** :: Views: **5334**

I need Gaussian and uniform noise. I can’t use a function because I need to put it in a FPGA so I need to make it out of basic math (+, -, * etc..). I’ve used the MATLAB noise generators and they work great.
You can use LFSR (**linear** **feedback** **shift** **register**) to produce noise in certain band. For

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2005 07:00 :: Black Jack :: Replies: **5** :: Views: **2347**

in addition to the stuff from bartart:
xapp052 (especially this one), xapp217, xapp220 from Xilinx documentation.
These are LFSR (**linear** **feedback** **shift** **register**) designs that produce pseudo (careful!)-random sequences. This means that eventually they get repeated. But if you have e.g. a 32-bit LFSR producing a maximal (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-25-2004 14:20 :: the_penetrator :: Replies: **2** :: Views: **3661**

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