39 Threads found on edaboard.com: Linear Feedback Shift Register
Good links to understand LFSR concept:
ASIC Design Methodologies and Tools (Digital) :: 21.05.2007 23:46 :: barkha :: Replies: 1 :: Views: 2200
Can anyone help me understand that how does a LFSR (linear feedback shift register) implement division required for CRC (cyclic redundancy check) ?
ASIC Design Methodologies and Tools (Digital) :: 01.07.2013 00:43 :: e-bedlam :: Replies: 1 :: Views: 243
you can also look at :
linear feedback shift register &
cellular automata shift register
ASIC Design Methodologies and Tools (Digital) :: 08.08.2007 01:42 :: sree205 :: Replies: 4 :: Views: 686
2. How we choose cherterstic polynomial for lfsr?
The characteristic plynomial is the LFSR connection which will give the maximum number of random values before it starts to repeat the values. Each LFSR will have a characteristic polynomial, which is pre-determined. There are equation to find that, which I don't remember just
ASIC Design Methodologies and Tools (Digital) :: 24.03.2008 05:20 :: vlsi_eda_guy :: Replies: 7 :: Views: 1911
in addition to the stuff from bartart:
xapp052 (especially this one), xapp217, xapp220 from Xilinx documentation.
These are LFSR (linear feedback shift register) designs that produce pseudo (careful!)-random sequences. This means that eventually they get repeated. But if you have e.g. a 32-bit LFSR producing a maximal (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.06.2004 10:20 :: the_penetrator :: Replies: 2 :: Views: 2185
Search for linear feedback shift register (or LFSR)on google. This structure is basically a circular shift register with XOR gates between some of the stages, it produces a pseudo-random sequence when clocked...
ASIC Design Methodologies and Tools (Digital) :: 28.01.2005 20:28 :: eternal_nan :: Replies: 17 :: Views: 1714
I need Gaussian and uniform noise. I can’t use a function because I need to put it in a FPGA so I need to make it out of basic math (+, -, * etc..). I’ve used the MATLAB noise generators and they work great.
You can use LFSR (linear feedback shift register) to produce noise in certain band. For
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2005 02:00 :: Black Jack :: Replies: 5 :: Views: 1723
I see this problem like this:
every tap (in your case x**14 and x**15) in LFSR (linear-feedback shift register) of your polynomial adds one additional error in the receiver. So the sum of all errors is three since original error plus two tap errors equals three.
I'm not sure about your code since I don't understand the (...)
Digital Signal Processing :: 15.07.2005 10:02 :: rfmw :: Replies: 6 :: Views: 3503
My BS project was in LDPC. in some case of LDPC code, encoding is very easy. in this case LDPC code generate by just LFSR(linear feedback shift register) like cyclic code. In this case some kind of Geometry code (EG and PG) are LDPC.
But decoding ?
LDPC codes have 3 method for decoding.
1- using Majority Logic (...)
Digital Signal Processing :: 25.07.2006 04:07 :: m_llaa :: Replies: 9 :: Views: 4970
A linear feedback shift register (LFSR) is an easy way to generate a pseudo-random bit stream in hardware by using a shift register and XNOR gate. Here are a couple of Xilinx app notes, and HDL examples:
Digital communication :: 19.12.2005 03:30 :: echo47 :: Replies: 3 :: Views: 2442
random pattern?? -> use LFSR (linear feedback shift register)
ASIC Design Methodologies and Tools (Digital) :: 23.02.2006 05:26 :: eda_wiz :: Replies: 1 :: Views: 773
LFSR is "linear feedback shift register"
It is used to make pseudo random generator
I'm afraid that this circuit is not working properly.
all D output digital number is 0, it does not generate some codes
in additional to, in my thought, It does not generate random codes, just shift codes
Analog Circuit Design :: 04.04.2006 20:57 :: 020170 :: Replies: 5 :: Views: 7404
What version of Modesim are you using? The default resolution Modelsim uses is 1 picosecond, so any simulation of a minute requires an enormous amount of clock cycles. This resolution can be changed. Also, this will syntesize using a 25 bit counter, which can be hard to route with a 25MHz clock (depends on the device you are using). It may be b
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2006 06:48 :: MWind :: Replies: 6 :: Views: 1005
I am designing "Data Randomizer" in verilog in which i am using a polynomial.
G : x16 + x13 + x12 + x11 + x7 + x6 + x3 + x + 1
My Query is : On what basis we choose a polynomial equation and if we implement this equation using LFSR(linear feedback shift register) where to place tabs for output ?
ASIC Design Methodologies and Tools (Digital) :: 05.01.2007 01:38 :: kunal1514 :: Replies: 0 :: Views: 429
u can use LFSR (linear feedback shift register)
Digital Signal Processing :: 10.06.2007 01:25 :: m_llaa :: Replies: 4 :: Views: 3584
you can try LFSR, the diagram and its C code can be found in
ASIC Design Methodologies and Tools (Digital) :: 16.11.2008 12:51 :: linkfox :: Replies: 2 :: Views: 10023
I have to write the scrambler code in verilog. The scrambler is LFSR(linear feedback shift register) based.
The 23-bit polynomial for the LFSR is G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1
The main problem I am facing is finding the value of LFSR after 8 serial clocks (1 bit advanced in each clock).
There are 2 (...)
ASIC Design Methodologies and Tools (Digital) :: 11.04.2009 07:10 :: aman_geek :: Replies: 6 :: Views: 6389
Signal source is a (pseudo-)random sequence generator.
Oscilloscope must have external trigger input, use sequence generator clock as trigger signal.
To measure, hook up oscilloscope to end of transmission media (receiver side).
To implement a sequence generator in HW, google 'linear feedback shift register" for (...)
PCB Routing Schematic Layout software and Simulation :: 08.08.2009 07:17 :: alenze :: Replies: 1 :: Views: 2611
Please help guys.. i need to perform the run and correlation property on a stream of bits that has been pseudorandomly generated.
I have used the following piece of code: e.g x= randn(10,1)>0.5 to generate random bits of 0's and 1's. Is this the correct way of doing it or do i need to pass through the linear feedback shift (...)
Digital communication :: 10.12.2009 10:33 :: dammadmin :: Replies: 0 :: Views: 737
i want vhdl code for signature analyzer for built in self test circuit... i can use 8 bit linear feedback shift register(LFSR) na?i am trying using 8 bit LFSR
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.02.2010 01:16 :: divsec :: Replies: 0 :: Views: 853
Ouput of LFSR Properties that confuse me:
1. "Ones and zeroes occur in 'runs'. The output stream 0110100, for example consists of five runs of lengths 1,2,1,1,2, in order. In one period of a maximal LFSR, 2n − 1 runs occur (for example, a six bit LFSR will have 32 runs). Exactly 1/2 of these runs will be one bit long, 1/4 will be two bit
Digital Signal Processing :: 27.08.2010 11:33 :: jasonkee111 :: Replies: 0 :: Views: 561
I have code for linear feedback shift register. It is not a random number generator in the strict sense. But must be useful in some cases.Download it from opencore.org:
LFSR-Random number generator :: Overview :: OpenCores
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.10.2010 09:57 :: vipinlal :: Replies: 3 :: Views: 2076
For maximum length LFSR polynominals, see linear feedback shift register - Wikipedia, the free encyclopedia
If you want other than maximum length PN codes, you should tell a specification first.
Digital communication :: 14.11.2010 09:05 :: FvM :: Replies: 1 :: Views: 801
sir, i need a bist architecture for prbs generator using vhdl. i searched in website but ther's no file. so wil u plz help me :-?
what do you mean with "bist architecture for prbs generator"?
for a prbs implementation you can also google for lfsr
here some links for a prbs generator with vhdl
Electronic Elementary Questions :: 20.01.2011 07:29 :: qieda :: Replies: 1 :: Views: 2090
linear feedback shift register - Wikipedia, the free encyclopedia
ASIC Design Methodologies and Tools (Digital) :: 23.01.2011 23:09 :: lostinxlation :: Replies: 6 :: Views: 1140
Implement linear feedback shift register in C code instead of a typical gate level netlist.
Microcontrollers :: 27.02.2011 22:53 :: lostinxlation :: Replies: 3 :: Views: 778
Usually, a feedback shift register is the answer linear feedback shift register - Wikipedia, the free encyclopedia
Hobby Circuits and Small Projects Problems :: 03.03.2011 14:46 :: FvM :: Replies: 4 :: Views: 1632
can anyone please send me the study material explaining the concept of linear feedback shift register(LFSR) and how it is applied for built in self test(BIST)
ASIC Design Methodologies and Tools (Digital) :: 21.04.2011 11:17 :: avinashch :: Replies: 7 :: Views: 593
as mentioned above, there is not a single galois field equation. not a single one per size of galois field. wikipedia has some. you can extract them from the taps given LFSR Reference -- M-Sequence, linear feedback shift register, Feedbac
ASIC Design Methodologies and Tools (Digital) :: 08.07.2011 21:45 :: permute :: Replies: 3 :: Views: 635
In SAR ADC, clock for both comparator and the controller should be same if you are going to design synchronous SAR. Each clock has positive level and negative level. Generally at positive edge controller plugged the capacitor and positive lever time is used to settle the voltage. for all this time comparator is in reset mode, so any hangup problem
Electronic Elementary Questions :: 30.09.2011 12:48 :: rongo024 :: Replies: 2 :: Views: 652
The protocol specification usually defines CRC in hex or polynomial notation. For example, CRC5 used in USB 2.0 protocol is represented as 0×5 in hex notation or as G(x)=x5+x2+1 in the polynomial notation. This CRC is typically implemented in hardware as a linear feedback shift register (LFSR) with a serial data input
ASIC Design Methodologies and Tools (Digital) :: 30.11.2011 12:02 :: yura717 :: Replies: 3 :: Views: 478
if you r talking abt PRBS(Pseudo Random Binary Sequence) generator, u should specify how many bits or the length . If u want n- bit PRBS generator ,then it can give u 2^n-1 binary sequences.
For PRBS FPGAsRus PRBS which are usually implemented using an LFSR(linear feedback shift register) i.e shift regi
ASIC Design Methodologies and Tools (Digital) :: 13.12.2011 07:34 :: antaryami.mt.er09 :: Replies: 4 :: Views: 1958
Is it the same as the white noise which means the power is equally divided in the whole frequency range?
If so, how does it come? Any reference is preferred.
Now I've built a pseudo-random sequence using linear feedback shift register(LFSR), and I'd like to check its power spectral, is it possible to make it out using (...)
Analog Circuit Design :: 17.12.2011 06:07 :: bsaqycx :: Replies: 0 :: Views: 235
I am hoping that this is the right forum to ask this question. I am trying to synthesize the code for a linear feedback shift register. The code is below
input op; //defines the operation
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.06.2013 15:43 :: atifhashmi :: Replies: 2 :: Views: 388
Xilinx app note 052, "Efficient shift registers, LFSR Counters, and Long Pseudo-Random Sequence Generators"
Xilinx app note 210, "linear feedback shift registers in Virtex Devices"
Electronic Elementary Questions :: 10.10.2004 08:00 :: echo47 :: Replies: 4 :: Views: 2388
You can use a simple shift register with feedback from two or more points, or taps, in the register chain. The data input to the shift register is generated by XOR-ing or XNOR-ing the tap bits; the remaining bits function as a standard shift register.
ASIC Design Methodologies and Tools (Digital) :: 23.05.2005 04:52 :: svicent :: Replies: 5 :: Views: 3666
try to find this excellent book covering your questions: Solomon W. Golomb, shift register Sequences, Aegean Park Press, California, 1982.
XOR gates give, in the case of binary system, linear addition, which is needed to form a linear-feedback shift registers, (...)
Electronic Elementary Questions :: 09.08.2005 07:22 :: rfmw :: Replies: 3 :: Views: 730
The keword is LFSR (linear feeback shift register). A feedback expression can be selected to achieve a maximum sequence length, this means all possible codings in the register execpt the all zero case, corresconding to a 2^n - 1 pseudo random bit sequence length.
You can find e. g. VHDL code examples at (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.06.2008 10:41 :: FvM :: Replies: 1 :: Views: 728
Please visit following page ... it might help value can be generated by using a linear shift register with feedback and xor operation
ASIC Design Methodologies and Tools (Digital) :: 07.11.2007 00:21 :: abaidullah :: Replies: 2 :: Views: 560