Search Engine www.edaboard.com

30 Threads found on edaboard.com: Loop Xilinx
Hi bro. I have 2 questions, please answer me. 1-Why sometime for programming of microblaze in xilinx fpga use while(1) loop and sometimes dont? see below code for example... I want to generate a PWM signal using the Timer/Counter IP Core. Nothing shows up. What I did: Added the core, connected the PWM0 port of the core to an ex
Dear all please tell me is there any alternate for 'for' loop in verilog. i am using xilinx. please explain me how?
signal dff_chain : std_logic_vector ( n - 1 downto 0 ) ; process ( clock ) is begin if reset = '1' then dff_chain <= ( others => '0' ) ; elsif rising_edge ( clock ) then dff_chain ( 0 ) <= input ; for index in dff_chain ' range loop dff_chain ( index + 1 ) <= dff_cha
Assuming you're only simulating it - somewhere appropriate in the process. In simulation, processes without a sensitivity list loop forever in 0 time. You need a wait statement to make it wait to move the time forward.
Hi, I've got some errors by synthesize a verilog code. I've googled this errors but I couldn't find a solution. Can someone help me ? For the code block below, /*8by8'lik alt bloklarin uyum toplamlari elde ediliyor*/ reg sum_8by8_q; //There are four 8by8 sub blocks reg array_1D_sum_8by8 ; //2 rows reg
There are no line numbers in your listing, which makes it a little difficult, but here are a few comments: 1) Don't use IEEE.std_logic_arith.all, use ieee.numeric.std instead 2) (0 downto 32) is wrong, what you mean is (32 downto 0) (or maybe (0 to 32) But your main problem is that the for-loop has to be inside a process.
the state machine is most appropriate, or wait till the counter counts down to 0, or up to 5 (depending on which way you want to count). VHDL loops are not appropriate here.
i am using the multiply and accumulate IP core from xilinx ,the operation it performs is first multiply the two inputs a and b and give prod= a*b then it subtracts the previous output from Prod s=s-prod problem: i m not able to see the s(present) output as it is loop back. in chipscope one of my input is 30Mhz (12 bit samples) and other one is a
hi friendz... i am newer to verilog desgin.while simulation of my verilog code in cadence it find the infinte loop design. so that i couldn't get the simulation result .but in xilinx i got the result for that design..... can you help me for the same...
Does xilinx XST support VHDL textio library for synthesized code? Most likely not. P.S.: If it's for a simulation test bench, the sequence would be for i in ar'range loop readline(f, inline); read(inline, ar(i)); end loop;
run trce with the correct FROM-TO constraint? keep in mind that you might need to pass PVT conditions to trce to get the min/max delays. the LUT's don't have the same closed-loop calibration that the IODELAY's have.
HDL attempts to generate hardware. You have defined a combinatorial loop. eg: assign x = x +1; makes no sense as a combinatorial circuit. It will work as a sequential circuit. eg: always @ (posedge clk) x <= x +1;
You can also think about using some tools integrated in Matlab, as xilinx System Generator, that allows you to get your hardware in the loop. Working in this way your can use Matlab for data injection, your HW for running the algorithm and once again Matlab for collecting data output and performing the validation. There is a JTAG connection bet
hi,i'm working with that hw in loop co_simulation in matlab xilinx system generator and i encounter an unacceptebale error that"s (("Illegal Period, This blocks attempts to set period that is a non-integer multiple of the system rate Error occurred during "Block Configuration" Reported by: 'figgg/puls/puls'. .that is not a non _ integer mult
Thats what I was expecting, glad you stated it explicitly! Assuming you'll be targeting xilinx devices. It has what you call Delay Locked loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. xilinx core generator will take parameter like multiplication/division factor (...)
hi, Spartan3e starter kit has JTAG USB interface for fpga programing, and debugging.... I want to use it for high speed data transfer interface from PC to Board... reading big data buffers....RS232 would be to slow. i found this System Generator for DSP: Performing Hardware-in-the-loop System Gen
If it is during development that you need to communicate, then use MathWorks MatLab Simulink with System Generator. Then use 'hardware-in-the-loop'. Some document about this:
Hello. I'm working on a "all digital" PowerLineCommunication (PLC) project. Destination chip is xilinx Sparan 3 FPGA. This is my first (real) communication projekt and I'm a little stuck :( I searched the internet for all Costas loop information available. But most of them just provide basic information about the loop (basic (...)
Yes 'while', 'for', and 'repeat' are synthesizable in some tools (they work in xilinx XST), however the synthesizer usually limits the loops to constants known at compile time, as FvM described. Remember that these are compile-time loops that create multiple copies of logic. They are not run-time loops that do things (...)
FOR i in (WIDTH-1) TO 1 loop where WIDTH is INTEGER :=5 The loop does never terminate... write (WIDTH-1) downto 1 instead of (WIDTH-1) TO 1 i'll give you small process to check it... process begin for i in 5 downto 1 loop report "this is " & integer'image(i) &"iteration"; end loop; report "i got out
modelsim is so primitive it is hard to beleive why it is so popular. (microsoft ?) what mentor does today is just to take this old software and criple it to se, pe, xe , starter, xilinx , altera versions. the only thing they do is put loop delays inside. every new version they come up with force you to compile all your files and packages.
I think you are talking about VHDL, yes? Maybe you aren't using the 'for' loop correctly. Remember that 'for' loops in HDL work differently than 'for' loops in a software language such as C. If you can show us an example of the code that isn't working for you, maybe someone here can help you debug it.
Some big designs do take a long time to synthesize. How much FPGA utilization does it report? Be sure your computer isn't running out of memory. Check your operating system's memory monitor. I sometimes see extremely slow XST performance if I use a Verilog "initial" block with a "for" loop to initialize a block RAM.
That warning message means your design has combinatorial logic with an output feeding back to the input, forming a loop. The result is usually a latch or oscillator. Most FPGA designers want to avoid such things, so the synthesis tool warns you.
Hi. Does anyone know the taps to make an LFSR with a loop length of 5 or 10 clock cycles? Thanks in advance.
Guys, any one can explain briefly on how the protocol of LVDS data transfer works in xilinx FPGA Development Kit? In the board they have the LVDS transmitter and receiver ports, can we just loop back the transmitter to receiver using a ribbon cable ( to connect the transmitter and receiver ports), or any extra work needed? And how to convert a digi
Your "always" block doesn't do any useful work except set pwm_out to 1, so maybe everything got optimized away. If you are trying to generate a pulse 256 cycles long, you need some sort of counter, not a "for" loop.
how to use bufgdll of Spartan2 fpga ? when i use u1: bufgdll(clk_in,clk) ; there errors !!! how to use BUFGDLL ? thanks First of all: how do you expect to get an answer if you don't post the error? Secondly: have you read the xilinx Application Note "Using the Virtex Delay-Locked loop XAPP132"? Go to support.
The attributes in the following Verilog snippet cause fatal syntax errors in ModelSim 5.8. Is this my fault, or a ModelSim bug? xilinx XST accepts it. If I rewrite it to eliminate the 'generate' loop, ModelSim accepts the attributes, and correctly ignores them. (The attributes are for xilinx ISE.) input inp, inn; wire tmp; out
loopback tx to Rx in the test bench code