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20 Threads found on Low Offset Comparator
Most resistor values are off feasible resistance range, the circuit can't work with the given dimensioning. You need particularly to consider available output current of LM124 and LMC3702. Also the input offset network is apparently not correctly calculated (besides too low resistance values). - - - Updated - - -[/
The OP07 opamp you're using as a comparator is not very fast. Its main claim to fame is the low offset. I expect an SR flipflop will more than be able to keep up with it for speed.
.....But from my circuit i think that pull up resistor (at output of opamp) make the output 4V while inputs are not given. Am I right ?? no. The comparator has an input offset voltage that could be positive, negative or zero so the output could be high or low or oscillating.
Hi helna! Actually, kickback noise can make offset to your circuit as u mentioned. To remove it, you can read some techniques in some following papers (i think they are the best for your circuit): 1. Kickback Noise Reduction Techniques for CMOS Latched comparators - Pedro M. Figueiredo. 2. A low-Kickback-Noise Latched (...)
It's likely you did a post-layout without Monte Carlo. This makes 1mV of systematic offset, which is very bad. I would assume that you have a low comparator gain. Usually systematic offset is in the 100uV range, and random offset is in the mV range per sigma.
Hi All, For an op-amp which will be used as open loop comparator, How do we simulate and judge the performance of the op-amp which include the following items: 1. Input voltage range 2. Output High voltage Vs Output low Voltage 3. Output current source and sink capability 3 Input offset voltage 4. Frequency (...)
Just use comparator to compare the two input signals for LDO error amplifier (output feedback voltage and reference voltage). If Vfboffset, comparator outputs a signal to pull low LDO power PMOS. Also another comparator (Vfb>Vref+offset) can be used for overshoot suppression.
Dear all, I need to design a 2 stage comparator that consumes low current. vdd = 1.4V and idd = 250nA, process is 0.25um cmos The comparator should work in a "slewing" condition. Can someone suggest a document or circuit for this ?? Thanks in advance.
Can anyone suggest how to design a comparator for SAR ADC, aiming to achieve ultra-low power but with moderate speed?
I am constructing an IC tester for functional test of IC now. Currently I use window comparator to test the output voltage is within the range of testing or not (0 - 5V or higher). This is to feed into microcontroller for a High or low pulse signal. So, how i construct the circuit to test an op-amp is function or not? The test I may need to do
hi, all, i want to get this paper. pls uploaad it if you have. many thanks! A low Input offset Voltage comparator with Wide Common Mode Input Range and Small Delay Title; A low Input offset Voltage comparator with Wide Common Mode Input Range and Small Delay Author;YAMADA (...)
hi, all, now i am designing a high precision, low offset cmos comparator in continuous-time applications. the comportant requirement of this comparator is very low offse, and Vos < 2mV must be met in my application, and the other features is loose. pls recomment me some resources or (...)
VT = Av/sqrt(W * L) x3 ==> 3 sigma I have worked with the comparator for 0.25um technology and also had the spec of 2mv offset luckily one sigma.. for this design i used large area device w=80um and l=2um .... and the next stage is my cascode stage ...followed by two differential stage and the conversion from differential t
sine wave output? then filter it and you'll have a nice sine wave square wave output? differential input single output amplifier/comparator can do it. if your input is symmetrical, and the amplifier/comparator is low offset/noise, 50% duty cycle is ensured.
hello all, i am designing a 10 bit ADC, and i need an architecture for a comparator that can achieve a resolution of 1.6mV. any ideas, papers, books, references? many thanks Use a low-gain amplifier folowed by a latch comparator, and output offset compensation. Bastos
Let's say the SAR to be designed is of 8-bit, what are the important specifications for the comparator? I would like to know how to calculate how low the offset of the comparator should be, the settling time accuracy, slew rate etc. Please give me some references. Thanks
Hi. 1.73 - 1.65 = 80 mV 80mV is not very low but this really depends on the comparator offset. As you said, comparators work well, but if S/H stage introduces just a little bit error to the held voltage, this difference may become less and your comparator may not recognize this difference due to its (...)
You will have to use a high side or low side shunt and amplify the small signal with a low offset amplifier and fallow it with a comparator. the output of the comparator can be monitored by the PIC to protect your motor.
Perform transient MC simulations as with s fixed input voltage which you sweep from say -20mv to 20mV in steps of 5mV. Then for each input voltage, you perform a comparing cycle. So, at the end of the simulation you will be able to determine the input range for wich your comparator allways gives a HIGH or a low on its output. Once you determined th
In some power IC design need detect power mos Vds volt and this volta is very small 20~30mv (Rds * current) and who to design small volt comp ? becuase < 30mv maybe OPA have large offset .. and if I use series Comp hi-resolution but will low speed ..