173 Threads found on edaboard.com: Map File
The exported map file from Encounter is wrong, so how to modify it to be able to get the correct layers in Virtuoso ?
Here is streamOut.map file from Encounter:
metal1 NET 1 0
metal1 SPNET 2 0
metal1 PIN 3 0
metal1 LEFPIN 4 0
metal1 FILL 5 0
metal1 FILLOPC 6 0
metal1 VIA 7 0
metal1 VIAFILL 8 (...)
ASIC Design Methodologies and Tools (Digital) :: 03-05-2017 19:45 :: oAwad :: Replies: 0 :: Views: 243
I want to export my design from encounter to virtuoso given that I don't have the map file. So how can I transfer the layout ? and what are the difference between GDSII, DEF and OA ?
You can let encounter generate a map file for you, it will be wrong, but you can then open the file and modify it by hand. (...)
ASIC Design Methodologies and Tools (Digital) :: 03-01-2017 15:43 :: ThisIsNotSam :: Replies: 3 :: Views: 253
I'm trying to open my GDS layout in Virtuoso after exporting it from SoC encounter. In the export I merged the GDS files of all std cells as well as the map file.
When I streamIn in Virtuoso, I attach the std cell library which was used in encounter. Then I get the complete design in virtuoso but in drawing with no metal fill at all (...)
ASIC Design Methodologies and Tools (Digital) :: 02-21-2017 14:04 :: oAwad :: Replies: 2 :: Views: 276
I have written tcl file for one simple circuit including library path which keep all instances.
my source file contain this line: assign out = (~a & b & c) + (a & ~b & c);
it synthesis fine by taking gates from library but when i do like this in source file: nand2 g1 (a, b, out1); then it does not (...)
ASIC Design Methodologies and Tools (Digital) :: 02-20-2017 14:24 :: sarfaraz.ahmed :: Replies: 2 :: Views: 263
I made a Place&Route in Encounter and got netlist+SDF for simulation.
Possibly, for simulation of design with gated and multiplexed clocks needs an Clock Tree building, i.e. post-map simulation is not required..
I think, solution is place&route or verilog/sdf modification (as mentioned by ThisIsNotSam)
ASIC Design Methodologies and Tools (Digital) :: 12-27-2016 09:02 :: alphus :: Replies: 3 :: Views: 393
I have created an application in C and compiled using GHS compiler to generate the .ELF output. I use this output on iSystem emulator to debug the code on target.
I have observed that the output (object files, map files) prefix the respective file path in a random format to the symbol/variable/function. Due (...)
Microcontrollers :: 07-08-2016 17:20 :: Roobaroo :: Replies: 0 :: Views: 292
while doing power estimation after synthesis. i am getting not-annotated nets. How can we exactly map the names? How to solve this annotation problem?
The saif file is generated using Modelsim and synthesis file from design compiler.
ASIC Design Methodologies and Tools (Digital) :: 05-02-2016 17:12 :: sajjad.hussain :: Replies: 3 :: Views: 554
can anybody suggest me the steps to import the Advanced Design System 2011 GDSII file into Cadence Virtuoso 6.1.4 UMC65nm.
I imported and I gave layer map file also but it is showing an error of " ERROR (XSTRM-74): Target library 'IND' is attached to the technology
library 'umc65ll'. Therefore, technology (...)
PCB Routing Schematic Layout software and Simulation :: 02-12-2016 06:14 :: Sri Harsha :: Replies: 0 :: Views: 465
Also, the imported gds file looks 2D, and I'm not sure whether it's fine. Was I supposed to add a layer map or technology file or something to make it look 3D?
Yes, you will need layer map file and also the technology data (thicknesses and materials). Don't forget the silicon substrate and its conductivity, thi
Electromagnetic Design and Simulation :: 01-21-2016 07:04 :: volker@muehlhaus :: Replies: 2 :: Views: 671
1. Run TQRC - it will automatically generate mapping between LEF & tech - you can check the log to find where it gets created.
2. You can keep following CCL command option - which can be used in Signoff-QRC run :
-technology_auto_layer_map true \
BTW, Free advise.. <filename>.tch is too old ( older (...)
ASIC Design Methodologies and Tools (Digital) :: 12-01-2015 14:08 :: sat :: Replies: 2 :: Views: 510
I am using Synplify Premier H-2013.03-1 as synthesis tool. At the last step map & Optimizations, it reported me that " @E:MF320 ： | c_ver failed generated Verilog file ", but i do not know how to solve it., pls take me a support, thank you.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-19-2015 03:34 :: bhliuliu :: Replies: 0 :: Views: 660
i think u need to map it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-09-2015 13:26 :: aruipksni :: Replies: 1 :: Views: 594
I am trying to import a design from cadence to HFSS for simulation. I figured that I have to define a layer-map file for the design to be imported in 3D and I did that. The problem I have is that dielectrics don't show up in the GDS file nor in HFSS. Do I have to define and draw them manually ?? is there a better way to do it ?? (...)
Electromagnetic Design and Simulation :: 07-15-2014 17:50 :: Bahaa Radi :: Replies: 1 :: Views: 1830
If you noticed IBIS file, there are multiple pins that map to same model definition. The model type may be Input, output or IO.
Suppose pins 1 to 5 map to model "xyz".
The translator would create one model for "xyz" with 3 pins (assuming it is IO type).
You would need to use this model 5 times in your design for the 5 pins.
Hope this clarifies.
PCB Routing Schematic Layout software and Simulation :: 06-05-2015 15:02 :: mvaseem :: Replies: 10 :: Views: 951
I've just finished my design and sent to PCB manufacturing house.
They have build the PCBs, but at pick&place time they are having some troubles with placement.
I sent a placement.txt file, exported from: file -> Export -> Placement.
This seems to be not enough, as they are asking me a 'topographical map with polarities
PCB Routing Schematic Layout software and Simulation :: 05-26-2015 07:08 :: yolco :: Replies: 1 :: Views: 551
Hi, everyone, here is the problem, i used spice in of IC615 to convert the spice netlist to schematic, it says successful, but the width of mosfet is not correct, it is all 2u,which is obvious not right, but the total width of mosfet is exactly property in the netlist.
I set the reference library and map file, so does anyone know this problem?
Software Problems, Hints and Reviews :: 05-08-2015 12:36 :: sundd :: Replies: 0 :: Views: 892
What are Extraction Tech file and LEF-Tech map file used for generating power grid library? Can I generate these files manually? Can anybody please provide sample Extraction Tech file and LEF-Tech map files?
Thanks in advance
ASIC Design Methodologies and Tools (Digital) :: 03-19-2015 06:04 :: biju4u90 :: Replies: 2 :: Views: 1153
The bitstream is used to map the internal connections of the device, and is quite far removed from the HDL. There is no direct connection between the two; HDL code is not "converted to bitstream", there are several intermediate steps-synthesis, mapping, placement, routing.
Power Electronics :: 02-27-2015 16:06 :: barry :: Replies: 1 :: Views: 309
You do not have error messages?, only warning?
well you need to fix the map file used to map the layers between the LEF/GDSand DEF files.
ASIC Design Methodologies and Tools (Digital) :: 02-23-2015 13:52 :: rca :: Replies: 5 :: Views: 1308
There is no direct way to translate verilog A to spice.
You need to use behavioral devices (E,F,G,H devices) and map the behavior from Verilog A to pspice.
Software Problems, Hints and Reviews :: 11-18-2014 08:40 :: mvaseem :: Replies: 1 :: Views: 2043
Any solutions guys? I don't have the hardware, it is at customer end. I can't debug properly. Source code i have and i can send them to customer to test it. Newly created hex file is still not working. And old Hex file working perfectly. What it could be? Can i see anything from .map or .lst file? or project settings save
Microcontrollers :: 06-27-2014 16:10 :: horace1 :: Replies: 11 :: Views: 1115
CPU company provides hardware and compiler.
the memory handle is provided by the cpu company as well. They also need to provide the image map file.
There also have hypervisor mode in the cpu, the map translator need to provided by the hardware.
The rest of the work can provided by the operation system, correct?
Can anyone (...)
Digital Signal Processing :: 05-29-2014 17:36 :: liletian :: Replies: 0 :: Views: 511
It is very easy to make the library. Just create a new library and add symbol and package and make a device. Then open ic package library and copy 40 pin DIP package and then come back to your new library's package and paste it. Then make symbol and then map the pins and finally add symbol and package to device. Then create a new project and add sc
Microcontrollers :: 05-05-2014 20:05 :: milan.rajik :: Replies: 2 :: Views: 1025
I'm trying to map a design generated low frequency clock of khz range to clock port of ILA core in chipscope PRo (.cdc) file. When I program and run the bitstream in fpga, it flags the message "Waiting for Core to be armed, slow or stopped clock".
When I tie the clock port to on board system clock or DCM clock, it's fine.
Kindly advise how to hoo
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2014 09:53 :: asicdesigner2014 :: Replies: 0 :: Views: 482
I successfully installed board station on Windows 7 and the XE tools working fine. But I have some C-Shell script to invoke DMGR and have some map files already mapped to call on the file location.
When I ran the script through C-shell, I got badly placed error on the C-shell.
PCB Routing Schematic Layout software and Simulation :: 10-31-2013 12:15 :: arunrajendhar :: Replies: 0 :: Views: 632
you could change the name as you want.
to generate the GDS, encounter used a map file between the name you want "ME1" or "totoME1", to the layer number used in the GDS, something like this "61:0".
You only need to have the technology LEF file and all std-cell/macros LEF file align to use the same name for the same layer.
ASIC Design Methodologies and Tools (Digital) :: 10-28-2013 07:47 :: rca :: Replies: 5 :: Views: 600
i hope you no need a layer map file to generate a lef file it is needed only when you you work a GDS file..
ASIC Design Methodologies and Tools (Digital) :: 10-23-2013 04:17 :: vimalraj205 :: Replies: 5 :: Views: 1073
Hello, I keep getting the above error when attempting to run Assura DRC on a simple layout of an inverter. I am using IBM 90nm technology.
Additionally, here are some of the errors in the Cadence terminal:
*No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found.
*No rule sets can be created because there are no defined Assura technologies
Software Problems, Hints and Reviews :: 09-24-2013 00:21 :: colinm09 :: Replies: 0 :: Views: 1959
how library file is added with my project source file after compilation?
Usually a library contains compiled relocatable code. It's linked into the project binary, not added to the source code.
You get information about linked code in the project linker map. The library source code might be available or not. You'll need it to tra
Microcontrollers :: 07-25-2013 08:02 :: FvM :: Replies: 1 :: Views: 410
question is not clear... by the way study flow to design a vhdl project.. you have to simulate for functionality ,synthesis to generate bit file which is used to map a real time logic on board
Hobby Circuits and Small Projects Problems :: 05-31-2013 05:53 :: achaleus :: Replies: 2 :: Views: 907
I have created a compiled library using
vhdlan -w xilinxcorelib -f xilinxcorelib/xilinxcorelib_compile_order.do
When this library is compiled with a verilog file list
(i.e. the verilog file list includes +vhdllib+)
vcs -f file_list>
I get :
Error- Missing library map
Previously analyzed de
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-12-2013 10:11 :: meir :: Replies: 0 :: Views: 1552
.libs have global as well as cell level atributes
Global attributes like
voltage map (0.9 1.2)
Cell attributes like
power or signal pin
timing for specified arcs
ASIC Design Methodologies and Tools (Digital) :: 02-11-2013 13:36 :: vasaroopak :: Replies: 4 :: Views: 1299
Go to DXF import option
Browse the file u want to import
select edit/view layers tab
map to the layer where u want to import
close the tab and click on import option...
PCB Routing Schematic Layout software and Simulation :: 02-05-2013 06:36 :: sivamani :: Replies: 10 :: Views: 1558
i run synthesis in command line ( linux ) . the .ngc file is created , the report is :
Total REAL time to Xst completion: 1864.00 secs
Total CPU time to Xst completion: 1854.77 secs
Total memory usage is 1218896 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2819 ( 0 filtered)
Number of infos
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-13-2012 03:08 :: gunnerunbeaten :: Replies: 1 :: Views: 885
I willing to save Mnemonic map of simvision to some directory.
But i'm not know how to save such as something file.
Is there way to save "Mnemonic map" of simvision?
Also, how can i load?
ASIC Design Methodologies and Tools (Digital) :: 10-25-2012 02:29 :: u24c02 :: Replies: 0 :: Views: 704
I have made my system needed memory in memory compiler, then I used component & port map in my .vhd file to use the memory.
But there is are some problems which I can not solve.
1- In MC output file some libraries are included :
but when I run modelsim to generate the saif (...)
ASIC Design Methodologies and Tools (Digital) :: 09-15-2012 19:07 :: sea_mist :: Replies: 0 :: Views: 523
I am trying to import GDS file exported from Cadence into HFSS14. For this purpose, I have created a tech file to map thickness and elevation but HFSS ignores elevation info and takes only thickness I think because when I try to overlap some layers and leave some space between layers, HFSS ignores elevations and abuts all layers to (...)
Electromagnetic Design and Simulation :: 09-15-2012 17:48 :: mustafayayla :: Replies: 1 :: Views: 1635
I import a GDSII file in IBM 7RF technology and while streaming in I specified the Layermap file (cmrf7sf.layermap) but while I try to do Calibre DRC it shows me the following error message:
Starting DRC on top cell in window:3...
Unable to find valid layer mapping (...)
ASIC Design Methodologies and Tools (Digital) :: 08-11-2012 23:38 :: jghasemi :: Replies: 0 :: Views: 1214
I have the following problem.
My map file, gotten from the foundry, isn't allow mapping gdsII correctly. Actually, I use SoC Encounter and after a few seconds after beginning of mapping it quits by itself.
Initially, map-file had the following structure:
#Layer Name (...)
ASIC Design Methodologies and Tools (Digital) :: 07-06-2012 07:00 :: kopern1k :: Replies: 0 :: Views: 1130
The easiest way is to transfer your via holes as another Gerber file.
Then, you can map that layer as a via layer for the EM solver.
Electromagnetic Design and Simulation :: 06-07-2012 09:12 :: volker_muehlhaus :: Replies: 5 :: Views: 1250
I am trying to load an srec file into to a byte-addressable memory in Verilog
The memory has to be one megabyte and has to have a 32-bit address input
- I am running into the following issues
-according to the srec format I have to load data into specific addresses. how to map hex addresses to a Verilog memory like this one
reg [ horizo
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-16-2012 03:40 :: Hassan Munir :: Replies: 1 :: Views: 1018
I have been asked to use CSRSpec in creating Address map for an entire chip. I am actually new to this and don't know how to use it and what are options that are available in CSRSpec and to be used for the same. I also want to know about the tool that can compile and run this file. Kindly help me as it is very urgent for me.
ASIC Design Methodologies and Tools (Digital) :: 05-15-2012 15:50 :: sakthikumaran87 :: Replies: 1 :: Views: 625
Hello every one,
how to we differentiate between behavioural, post-translate,Post map and Post-route simulation
Which one is called perfect timing simulation among the later 3...
I performed behavioural and post-route for my 'dynamic timing analysis'. Is it to be called the Timing simulation....!
Also what is simprim & SFD files...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-02-2012 14:43 :: syedshan :: Replies: 1 :: Views: 1560
I am a newbie for FPGA. Somebody generates an XDL file and wants to turn it into HDL.
I can only convert it to NCD. I want to build a post-map/PAR simulation model in ISE. However, the input can only be NGC, NGD or EDIF.
Can it convert the NCD file back to the types mentioned above? If yes, would you please tell me how (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-20-2012 08:16 :: cymerzhang :: Replies: 1 :: Views: 714
I've used this site in the past:
As long as your co-ords are in a standard csv file, then it can be uploaded, and it will display them as points overlaid on the map.
I don't know if it draws lines, but it can certainly draw points, and you can assign the points names too.
PC Programming and Interfacing :: 04-08-2012 23:13 :: sky_123 :: Replies: 1 :: Views: 1329
file IO in VHDL is only for testbenching (ie. for simulation).
file IO does not map to any appropriate logic. For this you need to create a controller for whatever device you are using (and its likely to be extreamly complicated in the case of a hard disk). Its easier just to let a micro controller handle a file system. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-22-2012 08:25 :: TrickyDicky :: Replies: 12 :: Views: 1294
Hi friends, I need a clarity in generic mapping in VHDL. I have a situation where the top file writes 19-bits into the entity named RND where the generic delcaration in entity is only 8-bits
This RNDcomponent file is instantiated two times in a Top file, as like this
mod1 : RND
Generic map ( g_tap1 (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-20-2012 08:47 :: xtcx :: Replies: 21 :: Views: 1137
I am trying to read JEDEC fuse map from ispLSI 1032E but i get JEDEC file with all fuses set as 0.
Chip ID is correct.
Has anybody had this kind of problem.
I am using LPT download cable
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2011 17:06 :: wapayk :: Replies: 2 :: Views: 1198
The problem is that you've put in two entities into one file.. and are trying to instantiate one entity inside the other one. I think what you wanna do is declare one of them SSRAM_16x8 as a component in the SSRAM_16x8_A entity and then just port map them..
or use a configuration to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-27-2011 08:00 :: vlsi_whiz :: Replies: 5 :: Views: 6404
ddis, I would just stream in the inductor. Cadence would assign any layer to your inductor metal etc. Then just go in to it and change layers as they suppose to be ba hand,. For inductor it is not so difficult. Way easier than figuring our the layer map.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-30-2011 18:07 :: Teddy :: Replies: 9 :: Views: 2571