299 Threads found on edaboard.com: Master Design
First of all this should have been posted in the ASIC design Methodologies and Tools (Digital) forum.
Start with the ARM AHB spec first and understand it.
A two master and two slave scenario is relatively simple. You must 1st understand how an arbiter (the arbiter decides which master has control of the slaves) and address decoder (th
ASIC Design Methodologies and Tools (Digital) :: 01-04-2017 09:56 :: dpaul :: Replies: 4 :: Views: 514
Hello every body,
I'm a master's student i need to design a MicrostripPatch antenna which worked in 60 GHZ.
I can't find any tutorial about the millimeter bande 60 GHZ.I find just many articles.
I need a tutorial which help me to design this type of antenna and to add all the dimensions of : Patch
and Feed line and substrate and (...)
RF, Microwave, Antennas and Optics :: 09-06-2016 12:17 :: mirou :: Replies: 0 :: Views: 4
AWID, ARID, BID, and RID are used to distinguish transfers form each master.
From the AXI spec
C9.4 Multiple Exclusive Threads
The protocol can support more than one Exclusive-capable master for each interface. This permits multiple masters
to use the same interface for Exclusive accesses. In this scenario the interconnect must
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-02-2016 15:19 :: ads-ee :: Replies: 3 :: Views: 355
MDK could mean Mentor design Kit or MOSIS design Kit, FDK may be Fraunhofer Desi
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-18-2016 20:17 :: erikl :: Replies: 4 :: Views: 822
This can achieve if your master Slave interconnect (AXI Interconnect Bridge) design supports it.
ASIC Design Methodologies and Tools (Digital) :: 07-11-2016 11:45 :: imbichie :: Replies: 2 :: Views: 544
I am going to pursue my master degree on Microelectronics and being specialized in design VLSI. I do not know which country I should choose to pursue my master Degree there. Which one is bether, USA, Canada, Germany, or Netherland.
Any help would be appreciated
EDA Jobs :: 06-30-2016 05:34 :: nmb :: Replies: 0 :: Views: 1244
i want to make a design for AMBA 3 AHB-Lite Protocol i have the design for master and slave but i have a problem when i make the test bench the value of the HRDATA is do not care ,on the other hand the slave design return the correct value for HRDATA but the master does not, is there a special method to (...)
Microcontrollers :: 06-08-2016 12:05 :: fatimaazzam :: Replies: 0 :: Views: 1086
Mblaze is a master not a slave. The DMA can be a master for doing memory to memory transfers it is only a slave for the control interface. If you need to have the DMA transfer data to memory that the Mblaze has exclusive access to, you would use a shared memory for that, so both Mblaze and DMA are masters.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-24-2016 05:56 :: ads-ee :: Replies: 2 :: Views: 357
I am master's student of micro/nano systems in Germany. My course is focused in Semiconductor technology and application. During studies I also did a student job in a company where I developed skills in EDA and design automation. I also have interest towards Analog/Mixed signal design, but I have basic experience with it. (...)
Education :: 05-12-2016 16:51 :: farhan89 :: Replies: 3 :: Views: 3647
Obviously, these devices are not intended to be connected to multiple paralleled SPI interfaces. It's not even simple to implement by the way, would involve one interface in master and three in slave mode. Furthermore, who has 3 spare SPI interfaces in his ?C design?
The devices are clearly intended to cooperate with dedicated QSPI interfaces, l
Microcontrollers :: 05-05-2016 08:39 :: FvM :: Replies: 6 :: Views: 387
I used to think alike when I was new to this domain.
But real world digital designs are huge and maintaining something which you have described almost becomes impossible. So this is rarely done. Don't worry you'll get used to it (an I2C master is a relatively simple design).
I generally use the word-highlighting feature of Notepad++ to (...)
Software Recommendations :: 04-18-2016 08:49 :: dpaul :: Replies: 4 :: Views: 28
Urgent! I am looking for APB master design verilog code. Someone please help me to find the code? It will be a great help. Thank you!
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2016 00:03 :: Naveen199289 :: Replies: 1 :: Views: 455
You need to do pretty much what HFSS is telling you to do: ensure that the floquet port is touching orthogonal master/Slave boundaries. There are some good tutorials included with HFSS that explain how to use Floquet ports.
Electromagnetic Design and Simulation :: 04-07-2016 14:39 :: PlanarMetamaterials :: Replies: 1 :: Views: 673
100 cores of what?
Nios relies on the Avalon Bus - usually with the Nios acting as the master and other units connected via a memory mapped avalon interface.
This way you can have any existing IP or any other IP you chose to design yourself (as avalon is a straight forward interface, very similar to AXI).
NoC is usually a term used for Asic, not
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-02-2016 09:39 :: TrickyDicky :: Replies: 3 :: Views: 506
I have the same problem and indeed I am using master/Slave BC in HFSS with array tool. Do you know what the problem and how I could overcome it?
Electromagnetic Design and Simulation :: 09-10-2015 16:27 :: hussahussien :: Replies: 4 :: Views: 2192
2 wire must be half duplex with MUX switch and master slave control.
4 wire may be full duplex and no Mux needed.
Analog Circuit Design :: 08-02-2015 16:22 :: SunnySkyguy :: Replies: 5 :: Views: 855
It seems they really want to motivate you to learn how to design with PIC with 1973 design constraints.
I would create a master clock to derive all the output results being the lowest common multiple of all resolution , frequency and time constraints.
1. Measure period between pulses, T counting master clock pulses, fc (...)
Hobby Circuits and Small Projects Problems :: 07-01-2015 04:33 :: SunnySkyguy :: Replies: 18 :: Views: 1160
Here's the schematic of an ECL-master-Slave-FlipFlop: 116180
You can use the D inputs as R/S inputs. Probably the master part (Q1 .. Q7) is enough for your purpose.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-03-2015 13:10 :: erikl :: Replies: 8 :: Views: 1678
Using divided clocks is bad design practice, as said, but it doesn't cause problems for an isolated entity that doesn't interface with other design units as long as the divided clock is a glitch-free registered signal.
To work as a SPI master, your design should be supplemented with a slave select ("SYNC") signal, (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-23-2015 10:46 :: FvM :: Replies: 6 :: Views: 713
I want to design a priority based arbiter to be used in an AXI4 N-to-M Interconnect (shared access Mode) which as multiple AXI4-Lite masters and slaves.
In this env. one master will have the highest priority and this master will also enjoy default-grant.
My idea is to make use of the arvalid and awvalid output (...)
ASIC Design Methodologies and Tools (Digital) :: 03-19-2015 09:30 :: dpaul :: Replies: 1 :: Views: 673
It's really not a big thing to design an I2C master from the scratch, just based on the Philips/NXP specification.
Besides using this straightforward approach, there are many I2C Verilog designs available from the internet.
- - - Updated - - -
how to code this in verilog ??
ASIC Design Methodologies and Tools (Digital) :: 02-27-2015 09:28 :: FvM :: Replies: 3 :: Views: 1650
The master thesis doesn't propose a calculation method, it uses simulation to determine the antenna dimensions (without showing a systematical approach). Simply googling "meander antenna calculation" gives many hits, also at Edaboard. You probably noticed the "similar threads" indicated below.
I believe, things are rather simple. A meander is a
RF, Microwave, Antennas and Optics :: 02-12-2015 09:28 :: FvM :: Replies: 3 :: Views: 946
Looking for suggestion for master's Project in ASIC. I got interest in GPU design.
But I'm cool with any latest area of research/algorithm being implemented in my project.
If you don't have any suggestions about Project ideas, can you at least guide me how to get an idea for the project?
Any help will be appreciated, thanks.
ASIC Design Methodologies and Tools (Digital) :: 01-17-2015 08:43 :: xaptar :: Replies: 2 :: Views: 595
I completed my master's Degree in Computer Engineering from Texas A&M and have been working as a Physical design Engineer for 2+ years. I am looking for jobs in VLSI domain near Notre Dame, IN since my fiance will be moving there. Please advise which companies might be hiring in that area.
EDA Jobs :: 01-09-2015 00:34 :: shyamala_venkataramani :: Replies: 0 :: Views: 1603
I have a project in mind to build a simple but also as a capable DAQ as reasonable to interface to PC through microcontroller-USB connection, I intend to use SAM3X8E(32bit flash ?C, used in Arduino Due) as a master controlling and communicating with ADC/ADCs and DAC/DACs or instead of a DAC maybe a DDS chip.
Anyway, I want to aim at 16
Digital Signal Processing :: 11-28-2014 01:32 :: David_ :: Replies: 5 :: Views: 1223
In my design, the I2S clock doesn't come from the transmitter nor the receiver, but from a host processor.
The BCLK and LRCLK (or WCLK) is sent from the host processor to both the transmitter and to the receiver. How do I minimize skew in this topology? What do I length-match the dataline to?
Professional Hardware and Electronics Design :: 11-13-2014 20:51 :: tcheung :: Replies: 1 :: Views: 516
for what???for master's or bachelor's degree? there are lots of great projects, u have to choose which project you want to do.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-12-2014 04:41 :: nick123 :: Replies: 1 :: Views: 588
I want to make a master thesis, in electric power engineering.
The thesis must include a PLC, a microcontroller
And high power loads. The prototype of the design must also be executed.
Any ideas ?
Education :: 10-27-2014 20:55 :: KhaledOsmani :: Replies: 0 :: Views: 1055
If you are new. Start with temp sensor and master how Derivative is used to anticipate rate changes with latency on air to sensor and Integral is used to amplify DC error on closure and Proportional gain keeps the loop tight. Phase margin with BODE PLOT is the measure of stability, where 60 deg is good and 90deg is nearly impossible.
Analog Circuit Design :: 10-24-2014 18:46 :: SunnySkyguy :: Replies: 1 :: Views: 2781
why not use a simple PWM switch for each table from a central DC source such as battery & charger.
The regulator would cost same or less than one 4W LED.
A master brightness could then be used with a central power source with voltage from 11 to 14V. Each table should have PTC protection and EMI filter.
Then you can use my design for outd
Power Electronics :: 10-21-2014 12:35 :: SunnySkyguy :: Replies: 18 :: Views: 1139
Hi Abhinav. Reading the standard is good enough. It is not necessary to implement everything mentioned in the standard. Whatever you implement must be understood by both the master and the slave.That's it. It is just a bus interface which will be used by the master to send data to the slave and receive responses. Don't fret over few things which yo
ASIC Design Methodologies and Tools (Digital) :: 10-08-2014 14:58 :: sharath666 :: Replies: 8 :: Views: 2066
I am trying to design a SPI master Module, I used a existing one in our folders at work. The SPI Module clock is 12.5 MHz (for a 25 MHz external clock). We want now a 1 MHz clock for the SPI Module. I changed the existing clock, put a counter to generate my 1MHz clock but the design doesnt work anymore. No errors detected (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-23-2014 23:17 :: mrbigglio :: Replies: 11 :: Views: 1524
Well, in order to connect multiple PICs (One PIC must be a master and other PIC must be a Slave), you can use either SPI protocol or I2C protocol ..
Microcontrollers :: 07-24-2014 06:43 :: th3gr8 :: Replies: 4 :: Views: 744
I'm a master of Science student. I have to realize (design) a "smart-chip" which integrates CMOS transistors (to interface a sensor) and a flow sensor (it's an APV - acoustic particle velocity sensor).
I need to know if there are foundries or companies (like Europractice) that offer "CMOS processes + bulk micromachining" to rea
ASIC Design Methodologies and Tools (Digital) :: 07-13-2014 10:36 :: Leonardo888 :: Replies: 0 :: Views: 364
I want to design a simple yet robust serial communication protocol over rs485. There will be multiple slaves and one master. What I could not decided is how to determine the end of a message. I may do it like the one in modbus e.g. using a time-out technique but I want it to be more flexible. I may think to use a special end of message character(s)
Hobby Circuits and Small Projects Problems :: 05-24-2014 15:48 :: seyyah :: Replies: 6 :: Views: 1024
i am using master/slave boundary + floquet port, but by seting scan angle 'Theta' in Tab 'Phase Delay' of Slave boundary Properties there are some problems like the design does not converge and simulation stops at 11th pass. While without doing this change the convergence is done in 6 pases only.
Can you tell me the what problem is this ??
Electromagnetic Design and Simulation :: 05-07-2014 17:51 :: muhammad idrees :: Replies: 6 :: Views: 1470
I really like to find a good subject for my master thesis that's why I'm searching too hard. I would like to write my thesis about op amp design but i need help to find out which subject is better nowadays.
I look forward to you advice
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-30-2014 05:17 :: besa67 :: Replies: 3 :: Views: 438
At first sight, I don't even understand the need for "encapsulation" for the communication of a basic M-Bus master (a "mini-master" in terms of the standard). But if you need to add some out-of-band-signalling, it should work with simple escape sequences.
Analog Circuit Design :: 04-11-2014 06:49 :: FvM :: Replies: 2 :: Views: 737
If you are a newbie to using bridges and steppers you might want to master understanding of how it works before you attempt to design it. Understand the trade-off with torque, speed , current limit, heat loss, noise, vibration. also complexity, smoothness of of micro-stepping vs torque & speed.
Get the kit
Hobby Circuits and Small Projects Problems :: 04-07-2014 20:04 :: SunnySkyguy :: Replies: 11 :: Views: 1285
SS handling on the master side is O.K., on the slave side, enabling SS control as you did will assure byte consistency. But you can use it also to detect the start of a multi-byte frame, which isn't done yet.
The more important point in my post is about unsuitable delays in the slave code.
Microcontrollers :: 03-22-2014 15:07 :: FvM :: Replies: 6 :: Views: 2142
Can anyone help me to write a simple working vhdl code for I2C master write and read interface with FPGA ?
I am doing this project for interfacing AT24C01A eprom with FPGA.
Thanks in advance.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-12-2014 09:49 :: pulkit.vlsi :: Replies: 4 :: Views: 5868
Layout of complex boards (be it DSP or not) is a trade all by itself and will take a very long time to master properly. But chances are the manufacturer of your DSP IC will have some layout guidelines. In absence of that, you can check other DSP vendors (same principles will apply) or, per example, FPGA vendors (X and A) who both tend to have excel
Digital Signal Processing :: 02-07-2014 18:10 :: Ice-Tea :: Replies: 2 :: Views: 661
I am about to finish my master's in Electrical Engg with Digital Communications specialization in Canada. I have good knowledge of DSP, MATLAB, FPGA design using Verilog, Verification using System Verilog.
I have an experience of about six years (five years in Hardware testing and one year in ASIC verification) outside of Canada and I am lookin
EDA Jobs :: 12-29-2013 00:11 :: want2LearnVlsi :: Replies: 0 :: Views: 1287
The best approach is to read the datasheets and application notes very thoroughly.
Then purchase a demo board (if available) and start playing with it, making measurements, reading waveforms, sending simple commands.
"Discovering" how a new component works, is the very best part of design engineering.
Then, after you have mastered the de
Power Electronics :: 12-16-2013 16:25 :: schmitt trigger :: Replies: 1 :: Views: 388
M.S., I presume means master of science.
The post would make sense in the Analog IC design or possibly ASIC Forum.
ASIC Design Methodologies and Tools (Digital) :: 11-16-2013 12:07 :: FvM :: Replies: 6 :: Views: 529
For my master's thesis i need to do system level modeling of DLL in simulink to calculate jitter. Later on design has to be done in cadence.
I could not find any reference to implement DLL in simulink. I am stuck with modeling of VCDL(voltage control delay line). Please guide me.
thanks a lot!
RF, Microwave, Antennas and Optics :: 11-11-2013 09:41 :: r@dio :: Replies: 0 :: Views: 653
I have installed NCSU FreePDK45 design kit for Cadence IC615 but have problem instantiating device layout with the following warning.
*WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.
I can only see a (...)
Software Problems, Hints and Reviews :: 10-09-2013 18:02 :: Yikun :: Replies: 0 :: Views: 827
Could you please suggest for me 3-4 good research topics in analog design that are suitable for master degree?
Analog Circuit Design :: 10-06-2013 08:57 :: mysterious_man :: Replies: 3 :: Views: 524
I am studying AHB and want to implement a simple AHB2APB bridge without split/retry, I have 2 modules inside my bridge 1. AHB Slave + Address decoder and 2. the state machine for APB. i have no clue how to start with the ahb slave and what functionality to implement. it is a single master bridge so i wont be using Hselx signal, no hproct, h
ASIC Design Methodologies and Tools (Digital) :: 09-28-2013 12:48 :: Maulik Suthar :: Replies: 0 :: Views: 1273
I am a fresh master with specialty in digital circuit design.
Recently I am asked for an interview for the job below,
> My team is responsible for architecting and delivering a XXnm product
> with multi-chip integration capabilities. You will be part of this
> product execution team (silicon aspects). We are focused on chip and
> system in
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-20-2013 16:00 :: cxf54 :: Replies: 0 :: Views: 621