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123 Threads found on edaboard.com: Matlab And Vhdl
I must be really stupid because I can't seem to find the answer online after a long time searching. My system consists of ADC -> Decimation filter (matlab) -> DAC I got the ADC , DAC , clkdiv all working with relative ease but I'm having troubles with a simple step. The ADC / DAC is 12 bit , 2.048V reference . My filter accepts +-2V fixed po
Hello, I?ve got problem with my 3 Stage Filter Design in matlab (for a Delta-Sigma Modulator), it would be great if someone could help! The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz. So I decided to do a 3 stage Filter: CIC w. 1 Bit input (decimation factor R = 128), CIC Compensator (...)
Hello all, i am trying to use a FIR IP core 5 in spartan3. i designed and quantized filter in matlab and used core generator to create it. i want my system to work in 40MHz clock frequency and 10 MHz input sampling frequency. input and output should be 12 bit. i changed all the parameters but the output (...)
I must implement in vhdl a neural network capable of recognizing these characters: left arrow, right arrow, up arrow and down arrow. I need to use as a template matrix 7 * 5. I also to be and code in matlab for it.
I believe, the challenge in designing FPGA image processing algorithms is to organize the sequential processing of image elements, using internal or external RAM as data source and sink. I won't expect that a HDL coder has the intelligence to achieve this. The focus of the matlab HDL coder is particularly speeding up simulation code by utilizing
I did my research in Model Order Reduction for electronic circuits in IISc, Bangalore, India. I know C, C++, matlab programming very well, and vhdl basics+some more. B.Tech EEE. Not so much asking for jobs, as I want to know : should I even try in this market in India for an EDA job now?
Hi, I'm Electronic Engineer with 5 years of experience at the fields of DSP, FPGA and board design. Contact me if you need any help with your project, including matlab simulations, vhdl/Verilog codding and simulation, designing and modeling of communication systems, image processing. Shlomy.
I used libsvm for SVM classification in matlab, now after getting my result, i want use it for implement hardware, that i want use vhdl code in xilinx. All i know, i should use Support vector and some parameters that get them after classification, and used them in ROM for xilinx. But i know it just theoretical (...)
yes ofc its possible. Fir filter needs only DFF , adder and multiplier. In FPGA transponded fir architecture is widely used. Basically u can design wanted fir in matlab, export coefficient from it, change it to fixed values , and you can start vhdl implementation
sir,for what purpose we combine xilinx(vhdl/veilog) with matlab for particular image processing project. this is for speed or accuracy ?
This sounds like a setup issue. I wont be modifying the code for you as I really dont know matlab (or how easily it translates to HDL). But I do know you need to set the timing of the model to discrete stepped rather than variable. Also note that only a subset of matlab code is translatable to HDL. You're supposed to use simulink for HDL transla
Hi marinet, Here the issue is that matlab to HDL conversion is not easy ( mainly for synthesis ). The division in your algorithm is a major problem. Division algorithms are in fact not straightforward to implement in digital design. Basically you will not get division result in one clock cycle, and hence the problem. Thats why everyone insi
I should design a digital filter of first order ADC Sigma-Delta converter with 8 bits, an over sampling ratio of 64 (OSR = 64),and sampling frequency of 10.24MHz.I make it with matlab SIMULINK as shown in this
To start with, use Xilinx IP for FFT first and then you may try to create one yourself. Also as Tricky said, you should use matlab design side by side for design.
Hi, I am doing vhdl project using nexys2 board. I need to read the sensor readings using matlab through serial communication. My Code: nexys = serial('COM1', 'BaudRate', 9600, 'Parity', 'odd', 'Terminator', '', 'Timeout', 1); fopen(nexys); s = 's'; fwrite(nexys,s,'uchar'); scan_s1 = fread(nexys,1,'uint16'); t
Hi all,, i am jumadil, newbie at this forum... i have a problem with HDL coder.. i want to make a FIR filter with FDA tool (simulink matlab), and then i generate vhdl's code with HDL coder, but unfortunately that program didn't work.. how i supossed to do? is there any setting to configure the hardware's target? thanks for (...)
Hi vivo_m, Try the matlab !
Hello, I am triying to simulate fir low pass filter in vhdl test bench, I get square waves from matlab as txt document, and I use ip cores for filter which I produced in matlab in fdatool. I am using text-io in the testbech. I have two questions 1-Square wave is 100Hz but in txt there are only -1s and (...)
Hello All Do u have a link where I can download a HLS tool? I need a tool that takes a C or matlab file and transfers it to vhdl. I already tried the HDL in Simulink of matlab but it doesn't support many of functions so I need another tool, any suggestions?
This is not really a vhdl problem, more of an algorithm problem. You probably need to model the system in something like matlab and see what kind of error you can cope with.
Hi! I have done my Masters in Embedded Digital Systems from University of Sussex, United Kingdom. Passed out Sep 2012. My skill set include: FPGA design with vhdl, RTL design, synthesis and implementation ( have done a project in it), PCB design, Signal processing in matlab and Image processing in (...)
I want to implement a reconfigurable fir filter in fpga. i have designed a direct transpose fir filter using matlab and using system generator i have generated the corresponding vhdl code. now i want to implement reconfiguration code using microblaze and integrate it with the already generated vhdl code. (...)
I haven't used the Altera one as such. It was a filter generated using matlab's vhdl coder that caused a problem and was un-synthesisable. You'd better ask someone else about this. I have a much much older version of matlab. I doubt its supported anymore.
Hi I have developed a test bench for my vhdl code and I have generated input file in matlab. I have saved input file in project file,but simulator can't open it!! What's wrong?
Hi digital design, I suggegest that you store the matrix from matlab on a file text, next use this file as input for your testbench. to read and write text files on vhdl use the textio library. have a nice simulation
Hi Dear all How can I calculate the maximum element of a NxN matrix? I know how to find it by matlab or C or even by using "for..loop" and "if" statements in vhdl but I am not sure that, Does this kind of coding synthesisable or not? ( I mean I didn't design a circuit for it before start to write the code). So what is your suggestion? Do I (...)
thanks for your answering TrickyDicky. I compiled my counter.vhdl code by Quartus Altera . then I exported it to counter.vhdl Testbench, (counter.vht).then I started matlab and change the directory into the counter.vhdl testbench directory and I entered "vsim('socketsimulink', 4449)" (...)
What do you exactly have to do? Are you trying to prepare stimuli in matlab and then simulate the vhdl design with those? In this case, this is a general question on how to use input text files for stimuli creation, and there are already topics on this in this forum. Cheers
Hi suga I can possibly convert your design from matlab to vhdl. First I will hand code an equivalent C model and then automatically generate vhdl with my own high-level synthesis tool. PM me if you are interested in discussing this matter further. Best regards, the_penetrator ---------- Post added at (...)
I am doing a project on Image Encryption in matlab, now further I have to generate hardware for that matlab file(*.m) by using vhdl or any other HDL. I want help regarding how to work with images (taking input, operations on pixels, and output), in vhdl. If anyone can provide info regarding converting the (...)
Hello, I'm using acceldsp to convert a file.m to vhdl. I write this code on matlab: function Y=addto(P,z) switch(z) case(1) X=P+3; Y=P; case(0) Y=X+P; end end I will use the case z=1 only once time,after that I want to store X in ROM memory. Can any one tel me how to do that. Thanks
I'm using Xilinx 13.1 evaluation version.I'm trying to generate a vhdl code for the chain code algorithm written in matlab. **Error in port widths or dimensions. Output port 1 of 'untitled/Image From Workspace' is a matrix **Error in port widths or dimensions. Input port 1 of 'untitled/Gateway In' is a one dimensional vector with 1 elem
You can easily read in a matlab written tabulated waveform with Modelsim.
hai, I have designed a model for OFDM in matlab simulink , and i am finding problem in converting "FFT,and IFFT" simulink block into vhdl code using "HDL coder". so can anyone help me , please. its very important for me. when ever i am trying with HDL coder it is giving an error message of "cannot implement the (...)
I m doing project on low power design.. a battery model is made in matlab and a processor or embedded system is needed for power management, but i m not able to decide on the processor .. i mean modelling in matlab... else can i interface a model in vhdl with matlab?? please help me out with this .. thank u...
Hi All, I wanna describe the behavioral model of resistive ram, i have done some work but i m not sure cos since it is a very new technology it is difficult to find some reference design, it would be really great if you know how to do it in vhdl or matlab.
Hello everyone, I need to run the following Mathworks tutorial. Simulink and ModelSim Tutorial :: Linking Simulink to ModelSim (Link for ModelSim) The tutorial is simple. It simulates an inverter written in vhdl and compiled by modelsim, and the test patterns are generated us
Hi there, Im new here. Lately, I am now doing my final year project using matlab, System Generator and Xilinx Spartan 6 FPGA LX9 Microboard. In my project, I want to convert m-file to vhdl code in system generator and then program the vhdl code into the Spartan 6 FPGA LX9 Microboard. By the way, (...)
i hope this will do it. turbo_logmap_matlab.rar (456.9 KB) if any one can give me vhdl or Verilog for the same i would welcome...
Hi; i have a combine peoject with vhdl and system generator files in ISE and i want to simulate whole of project in modelsim. when in matlab analyze system generator files, in netlist i have almost 25 vhdl files that my overal portmap is not exist in one file. how can i use system generator files combine (...)
Hi everybody I developed Adaptive noise cancellation system using matlab and vhdl both. I calculated SNR of original signal and denoised signal. Can any body tell me how to calculate system efficiency using these SNRs? Thany you an advance. Pl. I need it urgently
i have written a matlab code for removal of salt and pepper noise... i want to convert it to vhdl.. i dont have acceldsp... please help..
I would recommend you output a text file rather than binary from matlab. Reading text is easy in vhdl, but reading binary is simulator dependent. Modelsim is the easiest to read binary in.
Is it possible to convert all the matlab files to vhdl/verilog file using any inbuilt functions in matlab??
I don't use Verilog for testbenches, but in vhdl testbenches , it's easy to read matlab generated files with general file I/O commands. I guess, it should work with Verilog $fread as well. It's particularly useful, when you want to supply a waveform to a signal processing algorithm, one sample per clock cycle. But you should be also able to (...)
Hello every body I am doing a project on FPGA based acoustic noise cancellation systems. I did matlab and vhdl coding for this.Now I want to implement it on FPGA spartan3 board I would be very much grateful to you if you can provide me guideline for this thanks
If you've never done any vhdl coding (and I suspect, any digital design before), this is quite a hard one to start with. But you will need sin and cos look-up tables generated in something like matlab. Your whole design should be fixed point (not floating). Why do you need to convert to std_logic_vector? why not keep it all (...)
Hi all, Well I have to design a base index generator. When I say base index it is nothing but indexing the output of a binary counter. Well let me explain it clearly. We have a 13-bit binary counter who outputs are quoting to 4096 locations on a RAM and we have 13 such stages which is like the counter should count to 4K for 13 stages. Now we
You can use the filter toolbox of matlab (make a search for this in matlab help) and after that you can take the coefficients created and put them in vhdl.
Look at my attachment... Here I want to transmit my voice over UWB and to receive at receiver end. For that, there will be one ADC to convert my voice to input binary data(not shown above). Opposite action takes place at the receiver to play my voice on speaker. Blue blocks should implemented on single FPGA IC using vhdl. White blocks form R


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