1000 Threads found on edaboard.com: Matlab And Vhdl
up to my knowledge .. u still can't get a good design if it's automatically generated ..
good designs need to be designed by a designer .. not only entering coefficients to a system level tool (like matlab) and press a button to get a corresponding vhdl .. and though this may work sometime .. it's not recommended for (...)
Digital Signal Processing :: 11-29-2005 21:43 :: omara007 :: Replies: 2 :: Views: 1383
what is the difference between labview and vhdl
vhdl is programming language for hardware say FPGA/ASIC.
where as Labview is higher lever language to design complete system. Labview project may contain some block with vhdl code also. It can be compared with matlab for instance.
ASIC Design Methodologies and Tools (Digital) :: 08-16-2006 09:22 :: mpatel :: Replies: 1 :: Views: 1017
Can anyone help me with a matlab/simulink/vhdl
GSM modulator and/or demodulator design?
I need to implement a basic GSM modem for my DSP project
and I need some help.
Digital communication :: 08-31-2006 17:55 :: SagSag :: Replies: 1 :: Views: 2888
I am a design engineer working on VLSI and vhdl.I am interested in learning matlab as it will be useful in vhdl programming.
Is there any particular area that i have to concentrate in matlab or should i learn complete matlab.
I heard that simulink and system generator (...)
Digital Signal Processing :: 05-18-2007 05:44 :: Tan :: Replies: 5 :: Views: 1249
I need to run the following Mathworks tutorial.
Simulink and ModelSim Tutorial :: Linking Simulink to ModelSim (Link for ModelSim)
The tutorial is simple. It simulates an inverter written in vhdl and compiled by modelsim, and the test patterns are generated us
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-31-2011 11:50 :: sameh_yassin99 :: Replies: 7 :: Views: 2570
sir,for what purpose we combine xilinx(vhdl/veilog) with matlab for particular image processing project.
this is for speed or accuracy ?
Analog Circuit Design :: 01-09-2014 05:55 :: velu.plg :: Replies: 2 :: Views: 271
Numerical Analysis Using matlab and Spreadsheets, 2nd Edition
TiTLE : Numerical Analysis Using matlab and Spreadsheets, Second Edition
AUTHOR : Steven T. Karris
PUBLISHER : Orchard Publications
iSBN : 0974423912
PAGES : 570 Pages
EDiTiON : January 23, 2004
LANGUAGE : ENGLISH
FORMAT : PDF
Mathematics and Physics :: 04-14-2004 12:20 :: henry :: Replies: 0 :: Views: 3233
My project use mixed-language in Modelsim. Now I can dump waveform for debussy. But I don't know how to load verilog(*.v) and vhdl(*.vhd) files into Debussy? It seems Debussy only accept one language at a time.
ASIC Design Methodologies and Tools (Digital) :: 06-09-2004 23:52 :: jamesyang1209 :: Replies: 5 :: Views: 3764
the problem with developing in mathlab is that matlab codes are not portable and it always needs matlab to work. this is not true with C++ since it can be ported easily to other tools and environments.
Digital Signal Processing :: 12-25-2004 02:18 :: rakko :: Replies: 64 :: Views: 17927
What is the difference between these two? which one is useful or popular?
verilog HDL means verilog or vhdl?
it might be a stupic question, but thanks for your answer.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2005 10:37 :: shiningblue :: Replies: 14 :: Views: 1566
I want to ask are there any softwares used to convert C program to vhdl code?
thanks a lot
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-03-2005 05:45 :: V :: Replies: 11 :: Views: 6155
I'm doing something so COOL! .That i can't tell you because then i have to kill you!
Ok i will tell you i want to map a fingerprint to a PIN NUMBER ..get it
now i will kill you !
Anyways i needed a way interface matlab and mathematica . Mathematica symbol manipulation is really great ! ,but matlab opens door to so many things
Mathematics and Physics :: 08-13-2005 12:40 :: eltonjohn :: Replies: 0 :: Views: 1755
I'm trying to program a simple pld using orcad express v 9.1
I've some problems when I work on a machine state system with more than one output: when I run "compile" command everything is OK, but when I run "build" compile I get an error.
I think the problem is in how I write the program in vhdl
Is there anybody who can help me in working
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-02-2006 07:00 :: whalua :: Replies: 0 :: Views: 899
what is the difference between verilog hdl and vhdl
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-07-2006 13:20 :: tjr :: Replies: 6 :: Views: 1366
i also need to know how to convert c to matlab and viceversa
Digital communication :: 06-08-2006 11:24 :: ypnayak :: Replies: 0 :: Views: 739
how to interlink matlab and ns2.
Network :: 09-02-2006 05:16 :: geetha :: Replies: 1 :: Views: 1018
I am new to this site.I want to learn DSP.
The main thing I wanted to know is, for what purposes matlab and Simulink are used?
As a beginner, how should i proceed to learn using DSP for Audio/Video processing?
Digital Signal Processing :: 09-13-2006 04:56 :: sureshk :: Replies: 8 :: Views: 2397
Can there be mixed verilog and vhdl code? and if possible would the compiler support it. If there is a possiblity can anyone give me a sample code.
ASIC Design Methodologies and Tools (Digital) :: 09-19-2006 10:26 :: altair_06 :: Replies: 4 :: Views: 994
Try superNEC it is numerical code for matlab and there is GA optimiser
RF, Microwave, Antennas and Optics :: 10-28-2006 17:52 :: elkimhoc :: Replies: 15 :: Views: 5525
well day before i attended a seminar on vhdl and Verilog Programming and their usage..........
in that discussion one person made a statement that "as we can merge Verilog and vhdl with respect to eachother..........."blah blah blah
i have this doubt of "Can we merge Verilog (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-05-2006 06:45 :: rakesh_aadhimoolam :: Replies: 5 :: Views: 1267
is it possible to build an interface link between matlab and STK codes?
I explain :
part the output from STK are given to matlab code. It elaborates them and gives a feed-back to STK that continues its iteration.
It's an iterative process.
Is available a program like that? Any idea?
Thanks in (...)
PC Programming and Interfacing :: 12-18-2006 08:54 :: Lupin :: Replies: 0 :: Views: 1622
Hello, i need a very quick tut on DSP in matlab and labview, if anyone has some links, please post them for me, thanks!:D
Digital Signal Processing :: 01-06-2007 22:08 :: jmay :: Replies: 3 :: Views: 1868
I need to link matlab and Spice in my project.
Is it possible to link matlab and Spice?
Please tell me the procedure.
Thanks in advance
Digital communication :: 03-07-2007 12:30 :: tarakapraveen :: Replies: 0 :: Views: 679
Check this books, they shoul help
Numerical Analysis Using matlab and Spreadsheets (2nd ed.) - KARRIS, S. T.(2004)
Digital Signal Processing using matlab v.4 (DSP)
let me know if they helped you.
Digital Signal Processing :: 06-29-2007 16:58 :: ultrabrains :: Replies: 1 :: Views: 715
i made FDTD program using matlab and C langs
i use PML and it gives me un symmertic fields i.e un equal reflections
can any one help me in correcting this problem
Electromagnetic Design and Simulation :: 07-13-2007 11:20 :: ahmedsk :: Replies: 3 :: Views: 1373
what is the different between labview and vhdl?
what is the benefits of both? and which better??
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-02-2007 18:51 :: moh_monem43 :: Replies: 3 :: Views: 891
I tried to convert this schamtics into vhdl code. with schmatics simulation it works fine. but vhdl code it gives wrong result in simulation.
can any one check if schematics and vhdl code are equilent ???
thanks in advance,
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2007 06:30 :: Mirzaaur :: Replies: 1 :: Views: 521
i have a final project about nonlinear active noise control using volterra filter,
is there anyone who knows to program volterra filter in matlab and program the C code in CCS???
Digital Signal Processing :: 12-14-2007 05:39 :: jalal_merhi :: Replies: 1 :: Views: 2502
not too much..both r simulation softwares....
But matlab is more rich in case of toolboxes...
Software Problems, Hints and Reviews :: 12-27-2007 02:12 :: rag_perfect :: Replies: 53 :: Views: 54855
Can someone tell me if we can synthesize Verilog and vhdl files together into a netlist in Verilog using Cadence PKS tool?
ASIC Design Methodologies and Tools (Digital) :: 03-10-2008 01:41 :: sujithchakra :: Replies: 0 :: Views: 544
I am designing a decimation filter for sigma delta ADC.
I have read some materials, and my design consists of 3-stages.
1 CIC filter, 1 CIC compensator and 1 halfband filter, with
oversampling rate 128, input bitstream (1 bit). The output will be 16bit.
I designed the filter in matlab, and with (...)
Analog Circuit Design :: 07-04-2008 14:08 :: gcj :: Replies: 1 :: Views: 3160
Is anyone out there expert in both verilog and vhdl?? i really need help!!
thx in adv
EDA Jobs :: 10-23-2008 03:53 :: brunokasimin :: Replies: 3 :: Views: 761
Digital Signal Processing Using matlab and
Added after 1 minutes:
Added after 1 minutes:
Digital Signal Processing :: 03-08-2009 10:10 :: Aya2002 :: Replies: 3 :: Views: 1225
I am working to realize HSP50110 / 50210 architecture, used for demodulation in matlab and FPGA. I started with matlab's inbuilt example "symbol timing recovery with fixed sampling" and extended the design for HSP50110. I tried to replace Squaring loop method with either Gardner or Early-late Gate algorithm, but (...)
Digital communication :: 12-02-2009 02:24 :: mpatel :: Replies: 0 :: Views: 578
I dropped this question in some other forum, but not in detail as I asked it as an extension to some other thread.
In altium, i want to do both circuit simulation and vhdl simulation together. The altium guys said it is not possible in altium.
I have a vhdl code. Is there any way I can convert it into equivalent Pspice (...)
PCB Routing Schematic Layout software and Simulation :: 12-10-2009 01:19 :: ssankurathri :: Replies: 1 :: Views: 2272
Could someone convert the boolean formula AB'+C into verilog and vhdl code for me?
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-05-2010 09:56 :: gtan :: Replies: 1 :: Views: 2007
i want to know vhdl coding of mac and vhdl coding of look up table.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-28-2010 10:03 :: apurva10 :: Replies: 2 :: Views: 1978
I have an SV interface definition. (Used both inside RTL as well as test bench top) (PS: this is only a tiny bit of the entire code)
interface bus_if(input clk, rst_n);
modport slave_port(input clk,rst_n,cfg_slave);
modport master_port(input clk,rst_n,output cfg_slave);
ASIC Design Methodologies and Tools (Digital) :: 10-08-2010 12:03 :: vlsi_mani :: Replies: 0 :: Views: 1017
i am new to matlab and wand to simulate communicatin system on it help me with this
Software Problems, Hints and Reviews :: 11-30-2010 22:49 :: dhruva :: Replies: 1 :: Views: 489
it sort of speed and easy to use trade off. for more check links below
matlab vs. C++
PC Programming and Interfacing :: 06-28-2011 14:39 :: hanif :: Replies: 1 :: Views: 714
The synthesized netlist from Cadence RTL Compiler is in Verilog whereas the library cell definitions (used for gate level simulations) are in vhdl.
Can cadence use both vhdl and Verilog files together?
ASIC Design Methodologies and Tools (Digital) :: 07-30-2011 09:48 :: chip-monk :: Replies: 1 :: Views: 696
I want to connect matlab with a plant in my Control System Lab. Anybody can tell me how I can setting in matlab and What kind of OPC which I can use to connect the matlab with the plant?
Software Problems, Hints and Reviews :: 09-27-2011 09:23 :: rendiebos :: Replies: 0 :: Views: 437
We are looking for someone who can program our new FPGA board with USB3.0.
Required skills are:
C/C++ and vhdl
Good understanding of Eclipse and Visual C++ IDE and ARM GCC
Good understanding of Xilinx Spartan 6 FPGAs and Xilinx ISE
Good understanding (...)
EDA Jobs :: 03-30-2012 04:13 :: ersinozalp :: Replies: 0 :: Views: 958
dear there are some methods avail able in matlab to solve differential equations please study following examples and demo of matlab
Digital Signal Processing :: 04-11-2012 00:51 :: shahbaz.ele :: Replies: 2 :: Views: 390
I have a model in Sysgen and another model in vhdl code. I need to combine both of them together as 1 entire Project. The vhdl inputs come from the Sysgen output. The eventual output is from the vhdl block. I need to clock my Sysgen at Ts, but clock my vhdl code at Ts/2. However, when I do this, I can't get (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-12-2012 07:13 :: babyeric :: Replies: 1 :: Views: 342
i have five samples of "zero" enunciated speech, i have taken all the sample of same word zero and find the MELCEPSTRUM analysis and each of the sample yield a matrix of dimension of 5499x1 (actually i have converted into a column matrix in matlab);
Now i am using neural network for pattern recognition:
now input is given as follows (...)
Heuristic methods, Machine Learning, AI, and Soft Computing :: 07-01-2012 12:13 :: dashkil :: Replies: 0 :: Views: 1320
In matlab you need FDATool. Type 'help fdatool' in matlab command window.
If the input to the created in fdatool filter will be 6x1 vector, this represents 6 channels and each of them will be filtered independently.
Digital Signal Processing :: 08-03-2012 04:40 :: Mityan :: Replies: 1 :: Views: 665
I design sigma delta modelator by matlab and hspice
but output of noise shaping not correct in hspice!!!
there are images of noise shaping outputs.
can help me?
Professional Hardware and Electronics Design :: 08-13-2012 06:44 :: hasanalmasi :: Replies: 0 :: Views: 311
sir i have an code of matlab of gender voice reconition. i want to change this code in vhdl language. plz any one help me.. m beginner in vhdl...
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-23-2012 01:01 :: er.sahilchawla :: Replies: 2 :: Views: 1393
Since I have a problem in my work (I work on matlab and ImageJ) I think it is because of a thing that I just spotted : It's the difference of intensity of a pixel between matlab and ImageJ.
Why is there this difference ? Is it normal ?
I work on bruker image format (This is a set of .tif images)
You can (...)
Digital Signal Processing :: 06-24-2013 09:04 :: YuriGagarin :: Replies: 0 :: Views: 330