305 Threads found on edaboard.com: Matlab And Vhdl
up to my knowledge .. u still can't get a good design if it's automatically generated ..
good designs need to be designed by a designer .. not only entering coefficients to a system level tool (like matlab) and press a button to get a corresponding vhdl .. and though this may work sometime .. it's not recommended for (...)
Digital Signal Processing :: 29.11.2005 21:43 :: omara007 :: Replies: 2 :: Views: 1298
what is the difference between labview and vhdl
vhdl is programming language for hardware say FPGA/ASIC.
where as Labview is higher lever language to design complete system. Labview project may contain some block with vhdl code also. It can be compared with matlab for instance.
ASIC Design Methodologies and Tools (Digital) :: 16.08.2006 09:22 :: mpatel :: Replies: 1 :: Views: 895
Can anyone help me with a matlab/simulink/vhdl
GSM modulator and/or demodulator design?
I need to implement a basic GSM modem for my DSP project
and I need some help.
Digital communication :: 31.08.2006 17:55 :: SagSag :: Replies: 1 :: Views: 2708
I am a design engineer working on VLSI and vhdl.I am interested in learning matlab as it will be useful in vhdl programming.
Is there any particular area that i have to concentrate in matlab or should i learn complete matlab.
I heard that simulink and system generator (...)
Digital Signal Processing :: 18.05.2007 05:44 :: Tan :: Replies: 5 :: Views: 1180
I need to run the following Mathworks tutorial.
Simulink and ModelSim Tutorial :: Linking Simulink to ModelSim (Link for ModelSim)
The tutorial is simple. It simulates an inverter written in vhdl and compiled by modelsim, and the test patterns are generated us
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.10.2011 11:50 :: sameh_yassin99 :: Replies: 6 :: Views: 2060
I have a data file of a signal I captured on my oscilloscope, the data contains time and voltage for each measurement. Is it possible to import this text file into matlab and create a DSP model that uses the data file as input and runs a filter algorithm on it and then somehow using SystemGenerator export (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.03.2003 21:30 :: Jayson :: Replies: 4 :: Views: 2179
The System Generator for DSP tool is one of the industry's most popular DSP design tools for FPGAs. It automatically translates DSP systems developed using matlab? and Simulink? from The MathWorks into highly optimized vhdl and IP cores for Xilinx? FPGAs.
Designers can design and simulate a system using (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.07.2003 01:15 :: Amuro :: Replies: 7 :: Views: 1455
how can i convert modelsim waveform data into matlab,
and simulate it with matlab?
another question is how can i convert decimal fraction into binary,my purpose is multiple two decimal fraction and output it finally with fpga.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2004 04:29 :: junchaoguo51888 :: Replies: 2 :: Views: 2644
you can generate white noise with matlab, and then transform it binary data, such as symbol function.
you can store these data and regard it white noise.
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.11.2004 20:32 :: Jackwang :: Replies: 4 :: Views: 4322
Well DSP requires a high level modeling usually done with matlab an ideal solution is ACCELFPGA wich is basically a matlab language compiler .
Otherwise .there are plenty of libraries of cores they produce vhdl most of the times and VERILOG too the HDL code produced by COREGENERATOR,SYSTEM GENERATOR .SYSTEMVIEW (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.01.2005 18:39 :: eltonjohn :: Replies: 9 :: Views: 1115
I implemented the gabor transform in matlab and there were satisfactory results compared to the DCT.I tried implementin them in vhdl and the effort was DSP implementation the only way to realise gabor or how can i implement in vhdl?
The problem i faced was in implementing the 4D ffts.
Digital Signal Processing :: 03.04.2005 13:07 :: dynamicdude :: Replies: 0 :: Views: 736
matlab is widely used in ON AIR Simulations for Communication chips.
ASIC Design Methodologies and Tools (Digital) :: 02.05.2005 05:17 :: spauls :: Replies: 18 :: Views: 1950
can anybody help me how to make PID controller fine tuning or using ziegler nichlos methods in matlab ?
Software Problems, Hints and Reviews :: 02.05.2005 07:00 :: nami :: Replies: 2 :: Views: 6994
Yes, There are at least three different ways
1. Accelchip +matlab
2. Xilinx systemgenerator +matlab
3. Altera Quartus +matlab
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2005 20:09 :: jimjim2k :: Replies: 5 :: Views: 1125
You have also Xilinx's System Generator. Test algorithms in matlab then
implement them in Xilinx FPGAs. I don't know if intermediate files are HDL or EDIF.
Digital Signal Processing :: 01.08.2005 14:46 :: Santa :: Replies: 19 :: Views: 3166
these are matlab codes for RS
Digital Signal Processing :: 05.08.2008 01:48 :: zahedi79 :: Replies: 4 :: Views: 4521
Your question is a bit unclear. matlab mabe pluged into your vhdl simulator.
You can eother use some commertial library that generates vhdl out of matlab, or
use simulator and matlab C API to connect both.
Electronic Elementary Questions :: 11.07.2006 14:36 :: cschneider27 :: Replies: 5 :: Views: 1399
Xilinx,Leonardo spectrum can generate schematics for vhdl code.
Even you can write the code in matlab and system generator will generate vhdl code for the written code.
from that you can generate schematics.
I hope i am clear to you.
ASIC Design Methodologies and Tools (Digital) :: 27.10.2006 04:47 :: Tan :: Replies: 5 :: Views: 1276
What about using Digital Filter Analyzer (DFA) from digitalfilter.com? It can generate vhdl for simulated filter design. Coefficients are stored in a ROM table and intermediate multiplication results are stored in RAM block.. then summed.
I had a question for anyone who had used it before. How is it compared to matlab R14 filter design (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.11.2006 07:57 :: nansity :: Replies: 1 :: Views: 588
Can a matlab code or a Simulink block be translated to a valid vhdl code?!?!
if yes, please tell me how to do it?
Thank you all in advance,
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2006 07:46 :: ahmad_abdulghany :: Replies: 4 :: Views: 783
and then implement this PLL using vhdl in FPGA design？
I am very intrested in it.
Added after 25 minutes:
sorry. add another question.
Which book is OK when start FPGA design using matlab?
Digital communication :: 11.07.2007 03:19 :: FPGAs :: Replies: 2 :: Views: 2466
you have to put the image in matlab and get the matrix then convert it to binary values in a file and then read from the text file with binary values into vhdl
Digital Signal Processing :: 14.07.2007 08:25 :: barath_87 :: Replies: 10 :: Views: 3493
i suggest using matlab for behavior, for circuit simulation, you can use hspice,spectre,eldo,etc.
Analog IC Design and Layout :: 04.12.2007 06:37 :: caosl :: Replies: 3 :: Views: 587
Can any body guide me on how to use vhdl to read data from matlab and write the data ouput in a text file. Pl. elaborate using simple example.
Digital Signal Processing :: 25.05.2008 12:15 :: smqasim :: Replies: 3 :: Views: 1030
I doing the RS (255, 191) now, and need implement it with the matlab code and vhdl code. Can any one upload Reed solomon Code(matlab code or vhdl code with explantion) for encoder and decoder.
p/s: I also dun understood how to get D^8+D^4+D^3+D^2+1, hope (...)
Digital communication :: 04.07.2008 00:47 :: shirley_chee :: Replies: 0 :: Views: 1144
matlab based, vhdl based projects etc will help you.
Electronic Elementary Questions :: 21.07.2009 07:12 :: visual :: Replies: 1 :: Views: 2343
Open matlab 7.8 , R2009a , and you will find a demo in simulink HDL coder describing an LMS filter , it is written in embedded matlab and convertable to vhdl.
see the demo help for more details ,
feel free to ask
Digital communication :: 29.09.2009 09:05 :: medra :: Replies: 5 :: Views: 4225
Good day everyone.
I'm having this project right now. I'm going to have an ADC simulation using matlab and honestly, I don't have any idea how to start it.
Below are the specifications:
Input Frequency: 21 KHz
Transition Band (Fstart to Fstop) : 0.3 to 0.4
Input Signal Voltage: 2.5 V
Ripple Voltage: 0.02 V
Main Clock Frequency: (...)
Digital Signal Processing :: 08.10.2009 03:16 :: allennlowaton :: Replies: 1 :: Views: 3166
is there any way to use the results of the simulation made with vhdl(-ams) codes in matlab???
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.10.2009 09:14 :: universeee :: Replies: 2 :: Views: 726
Hope this helps
Digital Signal Processing :: 10.03.2010 15:46 :: amraldo :: Replies: 1 :: Views: 872
I heard that is possible to use matlab to generate a vector file and use this vector file in testbench module for testing an FPGA module,,,
is that achievable and how to do that,,,
thank you in advance :-)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.05.2010 07:42 :: lorf_of_the_rings :: Replies: 5 :: Views: 1476
I'm new in vhdl
and I want to convert the following equation is written in matlab to vhdl
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.07.2010 15:02 :: Cutey :: Replies: 7 :: Views: 1598
Well I have to design a base index generator. When I say base index it is nothing but indexing the output of a binary counter.
Well let me explain it clearly.
We have a 13-bit binary counter who outputs are quoting to 4096 locations on a RAM and we have 13 such stages which is like the counter should count to 4K for 13 stages. Now we
Digital Signal Processing :: 20.09.2010 12:06 :: DEEPTHIPENDYALA :: Replies: 0 :: Views: 978
Hello every body
I am doing a project on FPGA based acoustic noise cancellation systems. I did matlab and vhdl coding for this.Now I want to implement it on FPGA spartan3 board
I would be very much grateful to you if you can provide me guideline for this
Hobby Circuits and Small Projects Problems :: 21.10.2010 05:22 :: Anuja Diggikar :: Replies: 0 :: Views: 1190
I don't use Verilog for testbenches, but in vhdl testbenches , it's easy to read matlab generated files with general file I/O commands. I guess, it should work with Verilog $fread as well. It's particularly useful, when you want to supply a waveform to a signal processing algorithm, one sample per clock cycle. But you should be also able to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.12.2010 17:38 :: FvM :: Replies: 21 :: Views: 6943
Is it possible to convert all the matlab files to vhdl/verilog file using any inbuilt functions in matlab??
Electronic Elementary Questions :: 25.01.2011 09:50 :: manoranjan sb :: Replies: 2 :: Views: 1004
I would recommend you output a text file rather than binary from matlab. Reading text is easy in vhdl, but reading binary is simulator dependent. Modelsim is the easiest to read binary in.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.03.2011 08:09 :: TrickyDicky :: Replies: 8 :: Views: 1719
I developed Adaptive noise cancellation system using matlab and vhdl both.
I calculated SNR of original signal and denoised signal.
Can any body tell me how to calculate system efficiency using these SNRs?
Thany you an advance.
Pl. I need it urgently
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.05.2011 05:10 :: Anuja Diggikar :: Replies: 0 :: Views: 448
Which software do you use to design and implement digital filters - any kind of filters (Audio, Images, Video, etc)?
I want to do a short survey, so please answer the following:
2- Software tool(s)
3- Hardware target (i.e. MCU DSP, FPGA, etc.)
4- Type of digital filters (FIR/IIR, 1D/2D..., Order, ...)
Digital Signal Processing :: 14.06.2011 22:30 :: dramoz :: Replies: 2 :: Views: 323
ya i saw those they are matlab and vhdl code.i want verilog code.please help.thanks>>>>>
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.06.2011 13:55 :: max420 :: Replies: 3 :: Views: 2029
i have a rom like this generated from matlab
manually i copy this vectors to vhdl and put them betwwen "" in a constatnt array
now, the problem that this rom become bigger i would like to do that with an easy method :)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.01.2012 04:55 :: Bustigo :: Replies: 1 :: Views: 447
I m doing project on low power design.. a battery model is made in matlab and a processor or embedded system is needed for power management, but i m not able to decide on the processor .. i mean modelling in matlab... else can i interface a model in vhdl with matlab?? please help me out with this .. thank u...
Software Problems, Hints and Reviews :: 31.01.2012 11:28 :: chd123 :: Replies: 0 :: Views: 284
can any one please solve me this error when a making "socket" connection between matlab and simulink.
I have the following error
Error reported by S-function 'shdlcosim' in 'bi_dwa/HDL Cosimulation/S-Function':
Failed to connect to server. Make sure the loaded HDL simulator library is using shared memory.
thanks a lot
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.05.2012 08:07 :: noura7 :: Replies: 3 :: Views: 645
I can possibly convert your design from matlab to vhdl. First I will hand code an equivalent C model and then automatically generate vhdl with my own high-level synthesis tool.
PM me if you are interested in discussing this matter further.
---------- Post added at (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.05.2012 11:54 :: the_penetrator :: Replies: 4 :: Views: 454
If your purpose is just generating vhdl code, matlab HDL Coder is suitable. However, it generates lots of files, and most of time result is not suitable for FPGA bitstream generation.
SystemGenerator is nice tool, it allows you to design your system with IPCores like designing in Simulink.
If you knew IP CoreGen, SystemGenerator allows you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.07.2012 08:49 :: Ilgaz :: Replies: 4 :: Views: 693
What do you exactly have to do? Are you trying to prepare stimuli in matlab and then simulate the vhdl design with those? In this case, this is a general question on how to use input text files for stimuli creation, and there are already topics on this in this forum.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.07.2012 07:03 :: kingslayer :: Replies: 15 :: Views: 902
thanks for your answering TrickyDicky.
I compiled my counter.vhdl code by Quartus Altera . then I exported it to counter.vhdl Testbench, (counter.vht).then I started matlab and change the directory into the counter.vhdl testbench directory and I entered "vsim('socketsimulink', 4449)" (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.09.2012 13:49 :: femtoronics :: Replies: 5 :: Views: 360
hi all, I want to implement Sgma-Delta ADC on FPGA altera board using verilog code; I want to design my circuit using matlab simulink and then use matlab HDL coder to get verilog code ; but i dont know how to design my circuit in matlab and HOW to start with matlab; any body have useful (...)
Analog Circuit Design :: 17.11.2012 09:14 :: membership :: Replies: 5 :: Views: 448
I would use neither.
I dont know labview, but matlab and simulink are just high level modelling environments and pretty poor FPGA development tools. The HDL code they generate is sub optimal. Its fine if you dont mind wasting a load of space in your FPGA, but to get the most out of it you need to hand code your design, which (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.01.2013 04:17 :: TrickyDicky :: Replies: 2 :: Views: 579
This is not really a vhdl problem, more of an algorithm problem. You probably need to model the system in something like matlab and see what kind of error you can cope with.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.02.2013 05:24 :: TrickyDicky :: Replies: 4 :: Views: 240