Search Engine

Max Plus

Add Question

61 Threads found on Max Plus
Hi, After routing in ic compiler an extraction using inbuilt rc tool,my net delays are not reporting.I am loading min and max tlu plus files also.Please help me fix this issue.
This LED strip is suited only to rated line voltage for the design which may be exceeded in your location. The design uses the ESR of each LED set plus the series resistor. LEDs cannot handle a wide range of current above the average DC rated current. Typically the ratio is only 2~3 for Peak/DC max The 4 diode bridge simply rectifies the 230Vac
you have *.max file( layout plus file) or *.brd file ( allegro PCB editor file)? for *.max you can save it as a template file and load the new netlist in to this template
A state machine with flip flops is simple to control these 3 states. plus Vbat present. Use a current sense R such as 75~ 100mV at max current. Use a band gap ref for controlling current , voltage and shutdown float, which is included in LM317, but using a linear regulator is very inefficient with heat sink required. Measure average current with
Hi I converted layout max file to allegro 16.6 using orcad translator, all components imported but rats not found can any one tell me how transfer netlist to allegro?. Reference destinator also different . Pls help me
Hello, sorry for my bad english.... I`m from Gemany.... I`m looking for a solution to read back the programm of my max 7128STC and copy it to a spare one. I use the max plus II 10.23 software and the ByteBlaster MV.... it all ready to go.... I`m able to to wirte a new programm to the CPLD , erase it .... examine it..... but how do I save (...)
Hi Folks, I'm running into some compiling/synthesis errors using the Mentor Graphics Precision RTL Synthesis software. I'm hoping there are some real Mentor Graphics Gurus out there that can shed some light on these errors I'm getting. I've been using Mentor Graphics "HDL Designer" and "Precsion RTL synthesis" for many years. Recen
Torque is converted to a linear force with the gears and wheels. The force to overcome includes the mass times acceleration, plus gear friction, not just be stationary mass. The surge current or stall current rating is generally 5-8x the average max current determined by Rs winding resistance will decline slowly until it reaches cruising speed. P
Actually I wouldn't like to use electromechanical relays as the one you suggested, since they are noisy and have limited switching capabilities (considering I'll be using a PWM). The approach I forgot to consider, and which might be the simplest of all, is to use a 250VAC/16A SSR controlled by a 3~32VDC/100mA.
I'm designing DC/DC converter for low power application of up to 50 Watt using MOSFET half bridge configuration. MOSFET will be supplied with 325V (dc) which I've to convert into 1.5v(min)-50 volts(max) at isolation step down transformer's secondary. Please suggest me gate driver ICs for 800V. plus any IC with inbulit isolation? Can you sug
i use orcad 10.3 now i have installed orcad 16.3 but i cant find layout plus, so i cant open the .max file so, how can i open my old layout design which i have made in orcad 10.3 please help..!!!!!!!!!
Hi, Have you locked the tracks at the top layer? If "Yes" upload your xyz.max file to help you out. Also check layer stack up. Hope this solves your problem.
From desired Vce(sat) you can (I expect) determine a "forced beta" operating point and from that and load (plus margin) determine the required base current. Hopefully this does not exceed pin ratings of the uC. Then your desired resistor is VOH(min)-Vbe(max@)/Ib. If you saturate it real hard then switching (off) delay will be compromised and if y
It'a a combinational adder, individual bits get different delay. Apparently you have a rather slow logic family, but basically it's normal operation. P.S.: Strict VHDL rules would require at least one input signal to be sign extended to 5 bit. Curiously the present syntax is tolerated by max plus.
for a start - max plus 2 is very very old. You should be using a newer version of Quartus. THe VHDL compiler in max plus 2 is pretty poor.
max+plus II VHDL implementation is known to have many problems. It can still work for simple designs, but a microprocessor is probably beyond it's capabilities. Quartus operation is even more intuitive than max+plus II in my opinion. An option to convert existing max+plus II projects had (...)
EVERY name-brand amplifier IC has a detailed datasheet. Why didn't you look at it?? It shows that the TDA7265 has an output into 8 ohms of only about 6W per channel when the supply is only plus and minus 12V. Then the power supply must produce 12W of sound and about 12W of heating which is a total of 24W and then the max continuous current
I'm surprized, because EPM7000E series has no ISP capability according to the datasheet. Apart from this point, are you sure, that the "Examine" (readback) feature works with max7000 and 9000 series? Did you try it with a single device? P.S.: I found in the Quartus Software Handbook, that "Examine" isn't supported for max7000S, which refers to a
Both Quartus II v7.2 and v9.1 support the EPM7128SQC100-15 with the USB-Blaster. Why use max plus II? Class requirements? Have you check your LPT port settings in BIOS? The ByteBlaster II is supported only in certain modes. ---------- Post added at 21:30 ---------- Previous post was at 21:17 ---------- [/COLOR
Dear All, I have a serious trouble converting a .max board file edited by OrCAD Layout plus 16.2 into Altium .PcbDoc using AD S09 or AD 10. During the converting I get multiply warnings like "Unterminated string at Line..." and there is only way to press Cancel button in order to carry on. At the end of the process I can get only few options: th
hi to all of you . i have got an example to design a circuit using the VHDL language by using the max plus 2 program , in text,, i tried to do it , i reach to apoint but i feel that im lost i need your help PS any one need the exercise please email me as i couldnt upload it in this site thank you
hi i am very new in using the vhdl by mas plus ii ,, and i have got and example which shows that i have to use the concurrent statment , the drawing is a combination of gates and i have to desing them in vhdl .
Hi, Please help me for the below mentioned doubts.. 1) I am new to ASIC methodology, I am currently evaluating an IP where in i need to take it through the DC Topo flow, i am able to invoke the shell in TOPO mode. I am giving the milkyway reference lib milkyway design library TLU plus max files TLU map file even the synthesis goes
I am designing a Boost DC_DC,detail: 1.VIN=2.5V,VOUT=25V; 2.L=10uH,C=2.2uF; 3.max current in the ind is 1.3A; 4.EA's inputs are reference and feedback;and the output is 0~1.2V,which is compared to the sample value of the ind current plus slope_compensation; If I ignore other Power loss,what's the value can I set the slope_compensatio
hello i want to lach signals from some input lines how its do ........? i also want to count the clock input and streach some signals in the input lines for some duration can any one help me giving the code for above in vhdl plz help ....... i am using max plus 2 get 50 points thanks
i found a Schematic on line that is a little confusing to me. is this Schematic telling me the capactents of the capactiors and is so what is the voltged. The very old circuit has a max supply voltage of plus and minus 38VDC. Capacitors connected to the supply voltages and connected to the output should have a volta
It is the correct method for a quick simulation, I would recommend to add the via models as well. If you want a more accurate (complex) simulation, you should try a Design Of Experiments (DOE), the ibis models have 3 types of wroking situations (min, typ, max), plus the transmission line has a tolerance (it depends on the vendor, typically ~15%), a
The questions they are asking seem straight-forward. The setup time must use the maximum delay. Since the max inverter delay is 1.5nS per gate with a cascade of three gates, that delay is 4.5nS. The flop itself requires an additional 3nS of setup time. The total setup time is the maximum total inverter delay plus the (...)
You can use max plus 2 FPGA board.
I think that under normal operation, Q93 doesn't do anything, since vin = vout. but if you were to bring vin high enough, the top branch of the circuit wouldn't be able to pull vout high enough since the max input voltage is something like 1 diode drop plus VGS-VT for the mosfet load. So I think they've added Q93 to allow the output to swing within
max+plus II Tutorial Manual - Version 3.0 download attachment
you can try out max +plus student is available wid a free registration
I am interested in working on IEEE 754 floating point. Unfortunately ieee VHDL87, 93 does not have a FP package. Has anyone ever tried floating point package on max plus 2 in VHDL? On internet I found one third party package, the VHDL 200x library. A compile script is there and i think it compiles with Model Sim. Address is: ww
Hello can i compile my verilog program to jed file with max+plus? how can i do? Thank you
I think, you can't avoid that in max+plus. I met the same problem. The hierarchy window shows everything indiscriminately. Why don't you use Quartus software? It represents project's hierarchy perfectly - no RPTs or POFs, just instances only. Regards, YUV
max plus 2, Quartus 2, OrCAD, PROTEUS, PROTEL DXP, Leonardo Spectrum
i'm trying to make a parameterized carry save adder and an array multiplier (among other things) using max+plus II and verilog HDL. However my code so far hasn't worked. Can anyone help me please? Some code example will be really helpful
Greetings one and all, I want to write code for and program some Altera EPM9560 CPLD's. I know they are old, but I'm just an amateur and they were cheap! I cannot find software to support them. Quartus II doesn't (from current back to version 3) and the latest max+plus 10.2 only shows the EPM9320 versions, nothing bigger, even though its docu
Hi! I am newbie in CPLD, so excuse me for strange question. I need to add small delay in max7000S output - near 50-60 nS. There are no clock logic there in my project. I was trying to add chain of simple elements - pairs of invertors, but seems compiler is deleting them during compilation/optimization. I am using max+plus II for (...)
If u r using max + 11 for simulating bidirectional pins, they will produce an input pin and an output pin of the same name.. Maybe u should try with Modelsim for the simulation of bidirectional pins.
how can i count No. of gates used in my logic in ALtera family FPGAs?? i used max plus II and ACEX1k ( EP1K30TC144-1) device.. but the report file is showing only percentage of resourses used.... can i count no of gates for my logic with the same tool ??
Hello all, my question is if i can fit my project in more than 1 devices manually or automatically? I think but i am not so sure that in max plus there is a possibility to do it. thanks in advance for the help
I did a simulation of a sample in my max+plus II 10.23 the sample is: bidir.vhd (Tri-state bus implementation) --************************ LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Dear All, Do you know if it is possible, or how to select a PAL or GAL device for state machine design in max+plus II. These devices are not in the list by default. Thanx NTFS
maxplus2 just support the chip of older series, quartus2 support the new series.
max + plus is an almost obsolete software. My suggestion is to download free versions of q u a r t u s and recompile. Question of minutes.
In Quartus I could not find how to change the memory initialization file during simulation without re-compile. :( As I remembered, in max-plus you just need to reload the new .mif file, no need to re-compile the project. Who knows how to do it in Quartus? Thx a lot.
In Altera maxplus, I have designed the following module. in wave editor, I use "Enter nodes from SNF". how can I initial "initCnt" as b0101, in stead of initial "initCnt0,initCnt1,initCnt2,initCnt3" individually? another question: may I initial initCnt inside module? like "initial initCnt = 4'b0101;" thanks odule test ( clk1, clk2, clk3, initC
Hello asic1984, you can download the actual version 10.2 from Altera as Freeware (Baseline) from their homepage By, cube007
Why these IDE won't support it! :x