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43 Threads found on edaboard.com: Memory Parameters
Good day everybody I am doing a project where I am using a 256 Kbit eeprom (Atmel 24xx256). I need to map the whole memory location to store various parameters in to it. My doubt is that what will be the maximum addressable location that we can use in that eeprom?. Is that 512Kbit represents (128 x 1024)/8= 32768 bytes? But when I implemented a
Cost can be measured in clock cycles for buffered texture memory to prevent overflow or cost of STA analysis which can be hours or days depending on constraints with iteration on cell parameters for a complex design. (e.g. ARM)
Other parameters to consider include, bit/byte write capability, BIST muxes, retention modes, dual or single port. 1. There isn't a Cadence memory compiler. memory compilers typically come from foundries or IP providers. They generate views that can be used in tools from Cadence. 2. memory leaf cell? Do you mean the bit (...)
in C function parameters are passed by value (a copy of the parameter is made and the function does have access to the original parameter). If a function needs to pass data to the original parameter one uses the & (address of operator) to pass the address of the parameter to the function which can then access and alter the memory allocated to the
I have written a SPI master in Verilog to write values to a PLL synthesizer chip. It works. I am now trying to clean up my code so that I can put all of the parameters for the PLL at the top of the file either as parameters or macro-style definitions. In a few cases, I have some values that are larger and need to be split in half to fit into the SP
I need to store some user defined values. I'm wondering should i go with external EEPROM chip or dealing with the IAP and write in "user defined" portion of Flash memory ?
The term "memory clock" seems at least misleading to me. The memory chip's clock input frequency is always half the data rate, as the name DDR suggests, for all DDR, DDR2 and DDR3 devices. From a user's viewpoint, the difference is only in internal operation and shows up in latency and burst parameters.
It's pulse oximeter right? What are the parameters you are going to find (i.e. parameters like heart rate, SpO2, relative SpO2, pulse transit time, etc.)? Mention the sampling frequency... - - - Updated - - - Do you need to store the all adc values in memory? then you need external memory but your sampling frequency will
Hi every on in forum... I want small information from u,i am doing my work on STM32 controller,So i am storing some important data(parameters) of 44 bytes in internal flash, my stm32 consists of 128kbytes of memory ,So my doubt is that 1. How many times(no.of cycles) can i write data on stm32 flash memory? 2. I am using internal flash (...)
Hello, I have two flawn Keithley multimeters:2000 and 2015THD. For the 2015THD I would need the content of the two memories of 27C020 ( U156 , U157 version B07 ). It starts when I put the memories from 2000 but i don't think it is working in the normal parameters...where could I find the memory content? I am willing to trade the Keithley 2000.
Sorry, I cannot remember and it will be Monday before I can check. My memory is of being able to specify something like DEV=50% LOT=2% on the DEVICE parameter line although I seem to remember being able to also specify a LOT name which allowed you to specify which parameters tracked (a bit like the LOT number in the clip you posted). It is a long t
While largely application specific, adaptive algorithms are often measured/assessed/compared on the grounds of: * Their ability to achieve the specified goal, * Accuracy and repeatability, * Numerical stability, * Rate of convergence, * Computational complexity, and * Resource (CPU, memory etc) requirements.
I am trying to locate a block of constants (e.g. a list of parameters with a defined value) in an absolute memory address in the Flash (I am programing noe for LPC12xx processor using IAR Workbench). Can anyone assist ?
File Extension COE - How to Open COE Files Check this link. Quoting the critical part: "The initial contents of the memory of DSP are provided by files with the .coe file extension, consisting of two parameters: the memory initialization vector, which is the so-called data ve
It's quite obvious, that the incremental realloc() will be basically slower. It's only advantage is not needing to estimate a file size. In a real world, the decision would depend on parameters like: - single or multi-tasking enviroment - maximum file size - static or dynamic (e.g. swapping) memory resources - performance objectives
A little update: The simulation succeeded after I turned off the adaptive mesh refinement and decreased the number of mesh cells. Maybe it was a memory based error... But -- now I have some ripples in the S parameters due to the high resonating structure. I postprocessed the simulation results with the AR-filter and r
What is the number of mesh cells that you are using for the entire problem? You may not have enough memory ram on you computer.
hi In Xilinx FPGA you can read write from one location simultaneously if you set some additional parameters, as I remember. Problems could occur, because you can read wrong data. And handled it you should create some additional logic around memory(controller) , of couse if your memory does not implement it already.
I assume you have a pretty good idea of the top level block diagram, isn't it? Try to devide these block into entities that you can estimate, i.e. UART, processor (if any), DSP functions, state machines, ... Then you try to find a device that has enough I/O's, memory, logic to cover all these blocks with enough head room. Now look at the migration
Hello. I am trying to set up a DDR SDRAM controller in my SOPC build in Quartus and am confused about a couple of things. The memory I am trying to create the controller for is a 512M Qimonda IC, 32Mx16: One problem is the column width. As I understand it:
want to know an authentic answer for the time required to transfer a block of 1 mb data from disk to memory given the following parameters: seek time= 8.5ms ratational delay=4.17ms controller time=negligible transfer rate=100MB/s need replies ASAP!!! Amy
virtual memory? this corresponds to swap space i assume.
Sorry have posted this again, can anyone offer any advice. Driving me crazy. When I try and compile the following with Ke*l C51, I get the following. Error C208 DS1302GetAll Too many actual parameters Seems to be line in Time function /* DS1302 RTC Drivers*/ #pragma SMALL // Small memory model #include #in
Hi Guys, I am running my Postlayout simulation in NCSIM. Is there a way to find the delay between any two nodes using Tcl commands?? Suppose, I have a memory library "mem" whose timing parameters are provided in the SDF file as below. (a portion of..) (IOPATH (posedge CLK) Q (1.6990::1.7609) (1.6980::1.8186)) Now
You have run out of memory. You will have to use Bank directives to tell the compiler where to put the variables.
Hello Sahara, the main parameters which you should consider for a digital oscilloscope are on board memory and max sampling frequency. If budget is not a problem then you should consider also other parameters as the number of channels (2/4), the availability of built in Logic State analyzer and built in SW options. One of the best (...)
Hi, Bros I want to do some SI simulations to the DDR2 memory with SO-DIMM slot. I do not know the target memory Stick information, I mean it end user would probably use any memory stick. And I do not have the SPICE, RLGC or S-parameters of the SO-DIMM connector. But I know the IBIS model of memory (...)
Hi wichayen, DMA is also used for fast data transfer between some peripheral and internal memory without utilization of cpu core. Usually core set up the DMA transfer /base address and size of data block and other parameters / and start it. After that DMA controller takes control until the transfer is finished. At this point an interrupt to core i
Hi, The 16F876 has 8k program memory, and 256 bytes eeprom and 368 bytes RAM, as well as meeting your other parameters. If you don't need the eeprom, then the eeprom, then the 16F76, or 77 should get it for you. See: Hope this helps, Robert
Why would we use Macros when normal subroutines are more efficient when it comes to memory use? Macro code is flexible. You can supply one or more parameters to change the actual appearance of the Macro. This could produce different code every time the Macro is called. Some functions can not be handled by normal subroutines. Think about
Hi, At first, the SMALL compile memory model is used, which of course the internal data is used. However since the memory space is not enough for current project development; the LARGE compile memory model is used. In order to enhance the code speed as much as possible, the memory type on the passing parameter is (...)
This is a typical configuration trouble. Check in project options and set correcty the parameters like cpu, memory model, etc. Gorkin.
You'd better avoid calling C function in ASM file, if need, only call the C function without input parameters, cause the input parameters are stored in registers or memory depending on the compiler. To call C function, it's usually call _func for func() routine, maybe you also should declare the function name in the asm file, depend on your (...)
it depends on what do you define the read an write time. you can refer some RAMs' spec generated by memory compiler.
I am trying to track down some recommendations about gate lengths to prevent shifts in nmos transistor parameters vs Vds for 0.25um & 0.35um. In the past I have come across tables from the foundry but I can't find any such information at the moment. From memory I think the effect is worst when Vds = max (Vcc) and Vgs = ~ 0.5*Vcc. thanks, R
You haven't mensioned the parameters which you set to generate regfile and memory. I guess you have generated regfile and memory for smaller depths. Generally for large storages more than 2k we use memory (size efficient )and for smaller upto 2k or less we use register file.
Hi To a single slot, it'll not take too much time & memory if set a λ bounadry. PML is good for pattern computation. If you only want S-parameters, ABC is accurate enough. Build a "virtual object" around the slot is a tradeoff way. thanks! XuQing
hi I simulated a microstrip antenna with ansoft designer v1 and v2. the simulation time and the memory used are doubler with designer v2. Why? regards
Can anyone tell me the difference between these 2 parameters. This is normally specified for I/O buffers. I am attaching a memory datasheet which uses these specs Thanks in adv
Hi realtek Answer for 1 is: Use MegaWizard Plug-In Manager from Quartus software to generate ROM. Only what you need are parameters of ROM memory. This is the simplest way to use parametrized LPM's without errors and problems. At the end of configuration, Quartus will generate code ready to instantiate. Answer fo 2 is: It depends on
Foundry usually provide the design rule, ET specification?. such as MOS parameters Vth, Idsat, Isub, W/L unit.. I want to know those parameters must be cared on designing memory and I/O pad?? May I calculate the MOS sink/drive current without use HSPICE? Thansk a lot
What do you mean by often? This behaviour normally suggest either a problem in your Voltage as you suggested or more importantly a problem in your timing? Try to capture in your scope or Logic Analyser or wherever a single access when is not reading back properly? Bear in mind that the problem could be in the read cycle or in your write cyc
Hi, I have a question when instance a memory(from artisan) in my design. Is my flow correct?? 1. write a empty model , ex: module A16x16(); 2. in my design, i instace the empty module 3. In DC, read my all design include the empty moule, set the link_library path to the actual memory A16x16.db 4. command > link, the DC link my