1000 Threads found on edaboard.com: Mirror Pole
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 06-29-2012 06:49 :: dinosaur078 :: Replies: 0 :: Views: 631
like the figure, the solution is a pair of conjugate pole and zero.
but I think it should be a mirror pole and an output pole. why ?
And when I plot the frequence response (bode plot) , the position of pole is only
the real part of it ,or the amplitude of complex number.
Analog IC Design and Layout :: 12-15-2009 21:30 :: wangkes9 :: Replies: 0 :: Views: 661
Active current mirror is used for increase the output resistance. So it will have higher gain. Also it will lead to lower frequency pole according to bigger output resistance. pole frequency is related to R.C. Here R is the equivalent resistance, and C is the total capacitance at the node.
Analog IC Design and Layout :: 01-30-2011 04:25 :: leo_o2 :: Replies: 9 :: Views: 2209
I'd say that the poles can be divided into two groups:
-poles in the opamp: Miller pole and mirror pole (that should be the non-dominant one)
-poles of the LDO: there are those cause by the opamp, the loading of the pass device on the opamp will create another pole, and (...)
Analog IC Design and Layout :: 12-13-2006 11:08 :: jonashat :: Replies: 6 :: Views: 929
note that what u need to compensate is the CMFB loop not the CMFB amplifier and as u say by increasing the load capacitance u push the dominant pole to roll-off earlier and the dominant pole of the differential amplifier is at the same time the dominant pole of the CMFB loop(assuming that the mirror pole (...)
Analog Circuit Design :: 12-14-2006 05:01 :: MSSN :: Replies: 3 :: Views: 1326
... but this one is more complicated than razavi
Sure. But you're supposed to understand the given method and be able to extend it to a more complicated circuit.
Hints: Razavi's examples Fig. 4.33 , 4.34 & equ. (4.53) as well as Fig. 9.21 , 9.22 & equ. (9.13) come quite close to your pb. Don't forget the gain enhancement
Analog IC Design and Layout :: 11-09-2010 08:06 :: erikl :: Replies: 6 :: Views: 1157
i have designed a low power beta multiplier refernce (70nA) as shown. The opamp is a 5T diff check for stabilit i broke the -ve feedback loop and plugged iprobe from analoglib in cadence. stb analysis shows phase margin of 20 deg and gain margin of 14dB with C=2pf. I m not able to achive better phase margin even after shifting the mirror po
Analog Circuit Design :: 07-08-2012 12:07 :: analog_ambi :: Replies: 1 :: Views: 378
It can be generated by current mirror in differential amplifier... also in the case of pole-zero cancellation, when components are not perfectly matched.
The effect of pole-zero doublet could be not clearly seen in the amplitude and phase response, especiaqlly if the case if they are closed together, but relativlly small mismatch can have (...)
Analog Circuit Design :: 06-22-2006 14:22 :: pixel :: Replies: 12 :: Views: 9285
The purpose of my suggestion was for you mainly to test the normal current mirror operation in your simulator. Have you tested it??
I agree with cellphone, that is also what I guessed: the diff. transistor pair do not get correct DC bias from V3! To check this, omit V3 and bias base 5 and base 6 via two separate resistors from V1, ok?
Analog Circuit Design :: 01-12-2007 18:50 :: unkarc :: Replies: 15 :: Views: 856
The gain of the current mirror OTA is low.This is the biggest disadvantage.
Analog Circuit Design :: 05-17-2008 19:12 :: kennyg :: Replies: 15 :: Views: 3985
you have 3 poles and one zero. The dominant pole is at the output - the only high impedance point in the circuit. The other pole is associated with the NMOS current mirrors and the third one with the PMOS current mirrors. The zero comes from the fact that the signal sees unequal paths to the input. One path (...)
Analog Circuit Design :: 08-10-2008 03:45 :: sutapanaki :: Replies: 2 :: Views: 1628
By lagging the feedback FET, you will add peaking / sharpness
to the rest of the mirror rack. This can of course be overdone.
Analog Circuit Design :: 06-10-2013 11:38 :: dick_freebird :: Replies: 3 :: Views: 667
Hello Analog guys
I designed a current mirror OTA with a partial positive feedback, the circuit is like the one I attached from Gregorian book, Figure Nr. 3.41.
After I finished the design , I have simulated the circuit with and without the positive feedback as shown in the first and second image respectively.
Here I have a couple of ques
Analog IC Design and Layout :: 02-04-2013 14:01 :: Junus2012 :: Replies: 21 :: Views: 990
The circuit on the right figure is not a current mirror. This kind of circuit is in fact used in fast symetrical OTA to bias loaded current sources. The resistors are used as local CMFB and if their value is lower than 1/gm of fets, then overall OTA bandwith is increased.
Analog IC Design and Layout :: 11-10-2014 14:54 :: Dominik Przyborowski :: Replies: 6 :: Views: 712
Normally you can´t go below the regulators reference voltage.....but.
If you use the same Vref. to create a negative mirror voltage you can now use this as your ground or minus output.
This is the idea.
Professional Hardware and Electronics Design :: 03-04-2002 18:17 :: OttoMan :: Replies: 2 :: Views: 2401
Please Show me the link to download DEMO CD of mirror Suite Software.
Software Links :: 09-09-2003 22:27 :: hoclv :: Replies: 0 :: Views: 468
In my new design I have to use current mirrors. I have one current with hundreds of nA, and I have to mirror it in 1:1, 1:10, 1:100 and 1:1000 ratios. Of course thermal compensated. I know it is simple with IC design - a few transistors, resistors, cascode etc., but I am looking for any IC or another solution I could use on my PCB.
Professional Hardware and Electronics Design :: 10-11-2003 02:35 :: KamW :: Replies: 6 :: Views: 2511
Layout is the most likely cause.
Also take into account transistor sizes. Remember that all "deltas" are divided by sqrt(W.L) So, to reduce the standard deviation of each component (Id and Vt) you must increase transistors sizes. Another point in which ALL TRADITIONAL BOOKS make a mistake is about the term (Vg-Vt) that divides delta Vt. Actuall
ASIC Design Methodologies and Tools (Digital) :: 12-10-2003 03:05 :: Humungus :: Replies: 7 :: Views: 2437
Can you guys help me with a design for a J-pole dual band antenna ( vhf & uhf ) that at leaqst can handle 250 watts input power. :o
RF, Microwave, Antennas and Optics :: 02-16-2004 15:04 :: Ricky761 :: Replies: 7 :: Views: 3700
I am designing a regulator. which uses a close-loop opamp and a bandgap to get double or high output voltage. But in my design, since output has accurate require, so the opamp open-lop gain must be enough high. So I use fold cascode (first stage) + PMOS+two resistors (second stage). But the main pole in the first stage output, so when i increase th
Analog Circuit Design :: 03-05-2004 08:05 :: rambus_ddr :: Replies: 10 :: Views: 1557
Hi I am looking for a CMOS single-pole double-throw switch which could
switch differential signals. The working frequency better to be up to 2GHz.
Is there any available topology for that?
Analog Circuit Design :: 03-26-2004 15:21 :: qqpei :: Replies: 3 :: Views: 1649
I am doing a research on the Opamp pole/zero design, would somebody
provide me some info abouth this topic? Paper or thesis ... All are welcome!
Thanks a lot! :P
Analog Circuit Design :: 04-28-2004 01:58 :: johnli100 :: Replies: 6 :: Views: 1987
Iss there any circuit simulator how can simulate poles and zeros of a circuit and give their values???
Software Problems, Hints and Reviews :: 05-20-2004 06:49 :: tavakoli :: Replies: 7 :: Views: 1916
I want to devlope an application in vb for Telephonic pole. How it is possible to connect a vb software to your dailup modem that if some one diall the number of your modem then the vb sofware response the caller a predefined voice message and ask to input pole number.
If some one have ideas how to implement this then please share..Also t
PC Programming and Interfacing :: 06-23-2004 07:40 :: dani :: Replies: 2 :: Views: 808
How can I determine the dominant pole of an opamp by hand calculation?
I am confused with associating each node with a time constant and things like that......where can I find good reference about that? I read Razavi's simply does all the calculation and I don't really get any insight of the circuits......any idea? Thanks a lot. :D
Analog Circuit Design :: 06-25-2004 02:20 :: Hackson :: Replies: 4 :: Views: 2677
on my avatar i show a self biased current mirror, i had been studing this circuit, but i have still one question, how, exactly, does it comes on estability.
Electronic Elementary Questions :: 06-29-2004 10:45 :: brain79 :: Replies: 4 :: Views: 1729
Hi.. any one know any technique which can be used to design a current mirror capable of providing 10mA with low voltage headroom (less than 0.3V for the transistor to operate, the signal swing takes about 2.7V with 3V power supply) and high output impedance (more than 5k)? Is it possible cascode current mirror can achieve such a low voltage headroo
Analog Circuit Design :: 07-05-2004 23:02 :: ericlps :: Replies: 5 :: Views: 3805
Hi! Any one have any articles, journal or ebook regarding current mode method for current mirror? If u have something regarding active feedback/ adaptive method on current mirror is warmly welcome too. Thx :o
Analog Circuit Design :: 07-08-2004 02:48 :: ericlps :: Replies: 2 :: Views: 1525
Is it possible to have the wideswing current mirror for bandgap circuit.
Does this work properly in silicon. Where do I need to have the start ups.
(please see the attachment for circuit)
thanks in advance.
Analog Circuit Design :: 07-18-2004 21:35 :: santhoshv78 :: Replies: 3 :: Views: 672
Here are few question
Gain, (how to improve gain?)
Bandwidth, (how to improve bandwidth?)
Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!)
Slew rate,(How to improve slew rate?)
Offset,(how to eliminate offset? Chopper stabilized circuits, autozero)
Noise,(what is thermal, flick, shot noise? What are
Analog Circuit Design :: 08-18-2004 04:11 :: gold_kiss :: Replies: 19 :: Views: 4036
Need the next MTT paper:
J. D. Rhodes and R. J. Cameron, ?General extracted pole synthesis technique with applications to low-loss TE011 mode filters,? IEEE Trans.
Microwave Theory Tech., vol. MTT-28, pp. 1018?1028, 1980.
If anyone has it, please upload.
RF, Microwave, Antennas and Optics :: 09-22-2004 02:59 :: borich_03 :: Replies: 1 :: Views: 1061
In analog Macro model, we can use the construction of resistence, capacitor, inductor to modeling the pole or zero.
Who can describe some detail for it ?
Electronic Elementary Questions :: 10-06-2004 11:07 :: zoujunjx :: Replies: 1 :: Views: 1152
Who can tell about mirror Bit flash memory of AMD?
I am a memory designer, and want to exchange some experience. thanks!
Analog IC Design and Layout :: 10-27-2004 06:46 :: beckwang :: Replies: 2 :: Views: 1092
I have designed a 4-pole gaussian BPF arround 455kHz with 10kHz 3dB BW. I have tested it response and found that the sharpness is good but the insertion loss is about 30dB.
I guessed this insertion loss was due self resonance of the 680nF capacitor, but i have tested it response and found the resonance frequency is equal to 3.5MHz.
Analog Circuit Design :: 10-31-2004 07:04 :: Circuit_seller :: Replies: 9 :: Views: 1142
After finished a DAC design, I found that the bandgap output voltage can not bias DAC directly. So I need a current mirror circuit to bias the current source array in DAC (current steering architecture) . This circuit can change the bandgap output voltage to current. A paper tell me this kind of bias method is more steady than voltage bias.
Analog Circuit Design :: 12-08-2004 04:51 :: Question :: Replies: 0 :: Views: 1150
have the ADS software support pole-Zero and transfer function simulation .......
Software Problems, Hints and Reviews :: 12-26-2004 06:54 :: tavakoli :: Replies: 0 :: Views: 915
Hi there, i've failed to bias wide-swing cascode current mirror properly using 1.8V supply. The circuit i used is Fig 6.11 from Ken Martin book. Is it impossible to bias 4 transistors in cascode because of 4xVdsat? I need high current so that i can reach high slew rate. Can anyone help me or give me suggestion? Thanks in advance!
Analog Circuit Design :: 01-02-2005 05:09 :: richloo :: Replies: 0 :: Views: 1740
most effective is to mirror the power pmos while not connecting the drain together.
what is the meaning, may you explain in detail, thanks!
Analog Circuit Design :: 05-19-2007 09:06 :: mists :: Replies: 32 :: Views: 8361
Does anybody have the experience using totem-pole output stage in RF design? Is it specify for digital circuit?
RF, Microwave, Antennas and Optics :: 01-10-2005 08:50 :: nxing :: Replies: 1 :: Views: 1458
I noticed that when we evaluate a digital filter, we always focus on the Zero/pole Diagram, but how to read such a diagram from a view of engineering?
The problem is, if I have a lot of digital filters to choose, can I choose one with the "BEST" Zero/pole Diagram, but how to determine it is the best from the diagram?
Is it poss
Digital Signal Processing :: 01-21-2005 09:30 :: davyzhu :: Replies: 2 :: Views: 3675
You can check the formulas but here is some intuitive explanation. Let's call the transistor on the bottom of the cascode transistor 1 and that on the top - transistor 2. If you have a simple current mirror (one transistor only) - both in cmos and bjt - the voltage at the output terminal of the mirror (drain or collector) can vary depending on the
Analog IC Design and Layout :: 01-29-2005 01:53 :: sutapanaki :: Replies: 2 :: Views: 3610
Try to use cascode structure. Since the effect of early voltage is reflect by the finite output resistance of current mirror, using cascode can boost your output resistance and thus equivalently reduce the effect of early voltage.
Analog IC Design and Layout :: 01-29-2005 12:19 :: terryssw :: Replies: 18 :: Views: 2340
I think there must be a error for the mirrored current for the current mirror.
In the BIpolar or Mos process, the relative error of mirror is improved by increasing the ouput resistance .
Analog IC Design and Layout :: 02-24-2005 05:04 :: jiangwp :: Replies: 9 :: Views: 1669
This is self biased current mirror configuration .
Vov=overdrive =50mV R approx is 60 ohms ,calculate W/l for pmos and nmos .
The bias current has resistor variations that needs to be accomodated in design .
Analog IC Design and Layout :: 03-09-2005 09:37 :: mady79 :: Replies: 11 :: Views: 2211
low input offset and also low offset drift. The stability issue, since the paristic capacitance from PMOS current mirror is going to locate a new position of your pole.(especially for two stage opamp with miller compensation)
Analog Circuit Design :: 03-02-2005 09:43 :: cliffj :: Replies: 25 :: Views: 3008
Thank you all for the replies!
Dear Alles Gute,
What is this miller effect of Cgs5 you talk about.
I have never observed it.
Next, I hope u have smaller lengths for PMOS connected to supply so the would have lower parasitic capacitance. I suggest lower lengthe as their Vds would be small which is dependent on your bias volt
Analog Circuit Design :: 02-26-2005 15:17 :: Alles Gute :: Replies: 17 :: Views: 2339
what's gaussian and single-pole exponential decay pulses?
which differences are there between them?
RF, Microwave, Antennas and Optics :: 03-04-2005 04:31 :: Valiant :: Replies: 1 :: Views: 1648
It is not desirable to have low output impedance. because the gain of AMp is reduced. the main reason that current mirrors are used is that we had a single ended amplifier which has high Gm.
Electronic Elementary Questions :: 04-19-2005 11:51 :: savadi :: Replies: 6 :: Views: 7879
You should not let M2 level saturation any time, or the shielding property of cascode current mirror will be vanished. That is, the current is variated siginificantly with the output voltage, some nonlinearity will occur.
Analog Circuit Design :: 04-10-2005 01:29 :: Lantis :: Replies: 4 :: Views: 1969
if you just want to see how the mirrored version looks like, just go to print, and set it there. i believe its in the preference. you can choose which layer to appear and which layer on the top.
PCB Routing Schematic Layout software and Simulation :: 04-14-2005 04:28 :: wwfieee :: Replies: 4 :: Views: 2164