40 Threads found on edaboard.com: Mirror Pole
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 29.06.2012 06:49 :: dinosaur078 :: Replies: 0 :: Views: 526
like the figure, the solution is a pair of conjugate pole and zero.
but I think it should be a mirror pole and an output pole. why ?
And when I plot the frequence response (bode plot) , the position of pole is only
the real part of it ,or the amplitude of complex number.
Analog IC Design and Layout :: 15.12.2009 21:30 :: wangkes9 :: Replies: 0 :: Views: 559
Active current mirror is used for increase the output resistance. So it will have higher gain. Also it will lead to lower frequency pole according to bigger output resistance. pole frequency is related to R.C. Here R is the equivalent resistance, and C is the total capacitance at the node.
Analog IC Design and Layout :: 30.01.2011 04:25 :: leo_o2 :: Replies: 9 :: Views: 2032
It can be generated by current mirror in differential amplifier... also in the case of pole-zero cancellation, when components are not perfectly matched.
The effect of pole-zero doublet could be not clearly seen in the amplitude and phase response, especiaqlly if the case if they are closed together, but relativlly small mismatch can have (...)
Analog Circuit Design :: 22.06.2006 14:22 :: pixel :: Replies: 12 :: Views: 8861
I'd say that the poles can be divided into two groups:
-poles in the opamp: Miller pole and mirror pole (that should be the non-dominant one)
-poles of the LDO: there are those cause by the opamp, the loading of the pass device on the opamp will create another pole, and (...)
Analog IC Design and Layout :: 13.12.2006 11:08 :: jonashat :: Replies: 6 :: Views: 863
note that what u need to compensate is the CMFB loop not the CMFB amplifier and as u say by increasing the load capacitance u push the dominant pole to roll-off earlier and the dominant pole of the differential amplifier is at the same time the dominant pole of the CMFB loop(assuming that the mirror pole (...)
Analog Circuit Design :: 14.12.2006 05:01 :: MSSN :: Replies: 3 :: Views: 1225
The purpose of my suggestion was for you mainly to test the normal current mirror operation in your simulator. Have you tested it??
I agree with cellphone, that is also what I guessed: the diff. transistor pair do not get correct DC bias from V3! To check this, omit V3 and bias base 5 and base 6 via two separate resistors from V1, ok?
Analog Circuit Design :: 12.01.2007 18:50 :: unkarc :: Replies: 15 :: Views: 787
What are the advantages of current mirror OTA ?
Could it be considered a good topology for LDO error amplifier -at least as a first stage-(I have saw it in some papers but without reasoning for its usage)?
What I know is that it has a larger output swing & 1 pole-& the other is at high frequencies- (although composed of 2 stages).Also, it can be
Analog Circuit Design :: 17.05.2008 17:25 :: quaternion :: Replies: 15 :: Views: 3633
you have 3 poles and one zero. The dominant pole is at the output - the only high impedance point in the circuit. The other pole is associated with the NMOS current mirrors and the third one with the PMOS current mirrors. The zero comes from the fact that the signal sees unequal paths to the input. One path (...)
Analog Circuit Design :: 10.08.2008 03:45 :: sutapanaki :: Replies: 2 :: Views: 1557
... but this one is more complicated than razavi
Sure. But you're supposed to understand the given method and be able to extend it to a more complicated circuit.
Hints: Razavi's examples Fig. 4.33 , 4.34 & equ. (4.53) as well as Fig. 9.21 , 9.22 & equ. (9.13) come quite close to your pb. Don't forget the gain enhancement
Analog IC Design and Layout :: 09.11.2010 08:06 :: erikl :: Replies: 6 :: Views: 1109
By lagging the feedback FET, you will add peaking / sharpness
to the rest of the mirror rack. This can of course be overdone.
Analog Circuit Design :: 10.06.2013 11:38 :: dick_freebird :: Replies: 3 :: Views: 546
i have designed a low power beta multiplier refernce (70nA) as shown. The opamp is a 5T diff check for stabilit i broke the -ve feedback loop and plugged iprobe from analoglib in cadence. stb analysis shows phase margin of 20 deg and gain margin of 14dB with C=2pf. I m not able to achive better phase margin even after shifting the mirror po
Analog Circuit Design :: 08.07.2012 12:07 :: analog_ambi :: Replies: 1 :: Views: 311
As a rather trivial fact, any change to the gain with otherwise constant parameters (pole locations) affects the phase margin, so does the shown cross-coupled current-mirror load.
Analog IC Design and Layout :: 04.02.2013 17:05 :: FvM :: Replies: 21 :: Views: 855
Normally you can´t go below the regulators reference voltage.....but.
If you use the same Vref. to create a negative mirror voltage you can now use this as your ground or minus output.
This is the idea.
Professional Hardware and Electronics Design :: 04.03.2002 18:17 :: OttoMan :: Replies: 2 :: Views: 2300
Here are few question
Gain, (how to improve gain?)
Bandwidth, (how to improve bandwidth?)
Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!)
Slew rate,(How to improve slew rate?)
Offset,(how to eliminate offset? Chopper stabilized circuits, autozero)
Noise,(what is thermal, flick, shot noise? What are
Analog Circuit Design :: 18.08.2004 04:11 :: gold_kiss :: Replies: 19 :: Views: 3884
most effective is to mirror the power pmos while not connecting the drain together.
what is the meaning, may you explain in detail, thanks!
Analog Circuit Design :: 19.05.2007 09:06 :: mists :: Replies: 32 :: Views: 8175
low input offset and also low offset drift. The stability issue, since the paristic capacitance from PMOS current mirror is going to locate a new position of your pole.(especially for two stage opamp with miller compensation)
Analog Circuit Design :: 02.03.2005 09:43 :: cliffj :: Replies: 25 :: Views: 2883
I also want to a high UGB opamp to design opamp RC filter. My filter bandwidth is 20MHz, so my opamp UGB is about 2GHz. I try 2 test opamp circuit.
1. two stage
since the opamp need be used with close loop, so need a 40 degree PM. when i use nulling resistor miller compensation, the miller cap is 250f, so gmI is about 1.5m, and my loading is
Analog IC Design and Layout :: 05.08.2005 11:58 :: rambus_ddr :: Replies: 13 :: Views: 1869
I think there's misunderstanding the cap for bandgap output.
Cap at bandgap output is JUST use for bandgap purposes. There's nothing deal with LDO. The bandgap output connects to LDO -ve input of the error amplifier and the resistive divider output will connect back to +ve input of error amplifier and completes the LDO operation. The cl
Analog Circuit Design :: 24.03.2007 06:51 :: email@example.com :: Replies: 11 :: Views: 1288
This buffer is long time known as selfbiasing buffer. It is used for buffering signals and consume significant current only if the reference voltage is different from zero. So if Vref is a bandgap voltage activated by switch the buffer consumes only power if Vref > Vth,n. The current mirror loop gain made of p1,p3,n3,n4 should be 2. That is because
Analog Circuit Design :: 03.04.2006 04:32 :: rfsystem :: Replies: 6 :: Views: 847
1) First, what is the intent of your main circuit? You have the input at gate of NMOS differential pair tied to gate of an NMOS load (positive feedback?)
2) You have shorted the output with a resistor (Why?).
3) For stability analysis, you have to keep Rc in place - the second picture shows that one of the Rc is missing.
4) In your
Analog Circuit Design :: 16.05.2006 08:13 :: tsb_nph :: Replies: 11 :: Views: 2283
For conventional two stage opamp
First stage is standard active current mirror as load, diff pair and tail current source
Second stage common source amplifier
Now for the stability analysis, I need to draw the bode's plot were X axis is logarithmic frequency and Y axis is MOD of loop gain , where A(s) is open loop gain and f(s) i
Analog Circuit Design :: 25.08.2006 02:27 :: bsrivastava :: Replies: 3 :: Views: 1353
what is the mean of mirror amplifier ? thanks!
Analog Circuit Design :: 04.12.2006 08:10 :: mists :: Replies: 16 :: Views: 1381
For the cascode transistors they need to match their Vgs so their W/L should be large, at the same time their ro should be large so as to make the fold node look like a low impedance towards them and most of the small signal current goes through them. The trande off is the noise performace.
why ro is large that make the f
Analog IC Design and Layout :: 13.11.2006 06:50 :: mists :: Replies: 20 :: Views: 2022
These are my observations:
1. R1, C1 to compensate the zero due to mirror T3-T4.
2. C4 creates pole as in the paper.
3. C3 compensates the zero due to T2 (it is almost like a capacitor from gate of T2 to drain of T1).
I am not sure about C5, and the role of T5 and T6 (some startup ?)
Analog Circuit Design :: 12.06.2007 12:33 :: panditabupesh :: Replies: 6 :: Views: 1786
I do not understand how the the freq. resp of one is better than the other. First order, your BW is determined by gm6 and the output cap that is present on the drain of M6 and M7. And, the gm of M6 is the same in config1 and config2. Could you please explain to me and tell me what I am missing?[/q
Analog Circuit Design :: 14.08.2007 09:46 :: hr_rezaee :: Replies: 12 :: Views: 1289
If your MOS transistor goes linear, it is going to kill your gain. Don't confuse it with a bipolar device where you want that to run in the active region(thus it has high gain). Saturation for a bipolar device is bad for gain. If you take a MOS cascode mirror and put the cascode device in its linear region your output impedance will significantl
Analog Circuit Design :: 19.02.2008 19:55 :: haff99 :: Replies: 5 :: Views: 1758
The formulas I got can be found in many textbooks. The way I get the 2nd pole is
short the input and output @ high frequency, or F2nd. The impedacne is 1/gm2 and the capacitance is around Cl+Cgs2. Then you can get F2nd=gm2/(2pi*Cl) if Cl is larger than Cgs2. For more details, you can go through slides named "Analog Design Essen
Analog Circuit Design :: 04.04.2008 09:34 :: yschuang :: Replies: 14 :: Views: 1391
I am desiging a LDO. And the Cout will be in a wide range from 100pF to 100nF. I am wondering how to do the compensation.
I would say it is better to make the dominant pole inside. However, the big issue comes when the load current is small and the Cout is large. So, I decide to use pole zero compensation. That is to say I internally
Analog IC Design and Layout :: 04.09.2008 21:58 :: taofeng :: Replies: 1 :: Views: 1240
1. If the opamp have some mV offset and the diff-stage act as a gm-cell you have a differential switched current.
2. If you crossswitch these differential current in synchronism with the input voltage switch to an output current mirror the offset of the mirror does not get chopped out!
Because of 2. you need after the d
Analog Circuit Design :: 07.10.2008 14:41 :: rfsystem :: Replies: 1 :: Views: 1741
This is the popular wilson mirror. This is negative feedback and can become unstable. Do a websearch to know more about it.
Analog Circuit Design :: 23.11.2008 23:15 :: saro_k_82 :: Replies: 4 :: Views: 732
Question 1: The impedance seen in N towards M7 is approx. 1/gm7. If M6 and M7 are identical, the gain from the gate of M6 to the drain of M7 is -gm6/gm7 which is considered to be close to -1.
Question 2: On page 357 the author describes the effect of the pole(s) of the current mirror as an overall zero in the input-output transfer
Analog IC Design and Layout :: 07.02.2009 00:44 :: ict_eda :: Replies: 1 :: Views: 925
If not then how can i acheive a stable current source? Current mirror?
Analog Circuit Design :: 05.06.2009 12:42 :: Hitotsu :: Replies: 4 :: Views: 1095
I design a linear battery charger.
There is a current overshoot when CC(constant current) to CV(constant voltage) mode transition.
The charger structure reference the LTC4062's datasheet. the CC amp and CV amp share one current shink.
When I test the charger, I find the current overshoot. but simulate cann't find this issue.
Analog Circuit Design :: 04.05.2010 06:00 :: jerryzhao :: Replies: 4 :: Views: 917
Thank you for your post. Actually the drain of the pmos input stage IS (not ARE) connected to the nodes between drains and sources of the BOTTOM nmos cascode. The first stage has its own current mirror load. It's two stages for sure.
From what you say, it looks like a folded cascode topology. Put in sim
Analog Circuit Design :: 23.05.2010 09:13 :: amriths04 :: Replies: 7 :: Views: 1358
I am running a pole zero analysis via cadence spectre on a two stage opamp which consists of the classical diff pair with current mirror load and as second stage the classical common source/inverter problem is that i cannot see the RHP zero that is created via the feedforward path of the miller compensation capacitor...All t
Analog IC Design and Layout :: 26.05.2010 11:33 :: jimito13 :: Replies: 0 :: Views: 1237
... My guess is that because of the longitudinal capacitance, the common mode Vref voltage doesn't reach the OpAMP input (in DC). What could the solution be to my problem?
Use an additional parallel DC path, s. the foll. PDF: 49211
And I think the paper from Jian Xu et al. "Low Voltage Low Power C
Analog IC Design and Layout :: 13.09.2010 11:11 :: erikl :: Replies: 7 :: Views: 1013
im designing an OTA telescopic wid certain gain enchancement modification architecture wid current mirror technique .018 technology...
i got my gain enchanced by 6 db bt my phase margin got very much decreased to 54 from 78.... what shud i do to bring pm to more than 60 ...i took currents as 200uA for the ota...suggest
Analog Circuit Design :: 26.06.2011 08:01 :: satyanitt :: Replies: 4 :: Views: 661
PM = 180°-arctan(ft/fdp)-arctan(ft/fndp1)-arctan(ft/fndp2)
ft --> unity gain frequency
fdp --> dominant pole frequency (cut-off/-3dB freq. of your opamp)
fndp1 --> non-dominant pole 1 freq.
fndp2 --> non-dominant pole 2 freq.
dp1 is much smaller than ft so try to move the ndp1 lot of times further than ft to improve phase margin.
In a (...)
Analog Circuit Design :: 25.08.2011 07:35 :: jimito13 :: Replies: 4 :: Views: 487
First of all, your Nmos and Pmos are connected locally within your amplifier. I would think this is a mistake because you will have to increase your area for the spacing of the Pmos in layout and you would need a triple well process for the Nmos... so I would first have all bodies of Nmos connected to ground and all Pmos bodies connected to VDD.
Analog IC Design and Layout :: 04.12.2011 04:10 :: jgk2004 :: Replies: 12 :: Views: 1357