11 Threads found on edaboard.com: Mirror Pole
As a rather trivial fact, any change to the gain with otherwise constant parameters (pole locations) affects the phase margin, so does the shown cross-coupled current-mirror load.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-04-2013 22:05 :: FvM :: Replies: 21 :: Views: 1903
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 06-29-2012 10:49 :: dinosaur078 :: Replies: 0 :: Views: 925
By lagging the feedback FET, you will add peaking / sharpness
to the rest of the mirror rack. This can of course be overdone.
Analog Circuit Design :: 06-10-2013 15:38 :: dick_freebird :: Replies: 3 :: Views: 1186
why not increase the load capacitors? You can also reduce the ratio of the mirror branch to the ota branch to reduce the capacitance at the NMOS cascode node - this is your non-dominant pole. You may also want to increase the gm of the NMOS cascode devices.
Analog Circuit Design :: 06-27-2011 05:42 :: sutapanaki :: Replies: 4 :: Views: 1600
Active current mirror is used for increase the output resistance. So it will have higher gain. Also it will lead to lower frequency pole according to bigger output resistance. pole frequency is related to R.C. Here R is the equivalent resistance, and C is the total capacitance at the node.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-30-2011 09:25 :: leo_o2 :: Replies: 9 :: Views: 3056
I am running a pole zero analysis via cadence spectre on a two stage opamp which consists of the classical diff pair with current mirror load and as second stage the classical common source/inverter problem is that i cannot see the RHP zero that is created via the feedforward path of the miller compensation capacitor...All t
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-26-2010 15:33 :: jimito13 :: Replies: 0 :: Views: 1706
like the figure, the solution is a pair of conjugate pole and zero.
but I think it should be a mirror pole and an output pole. why ?
And when I plot the frequence response (bode plot) , the position of pole is only
the real part of it ,or the amplitude of complex number.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-16-2009 02:30 :: wangkes9 :: Replies: 0 :: Views: 899
This is the popular wilson mirror. This is negative feedback and can become unstable. Do a websearch to know more about it.
i think shd be no problem because only have one inversion in the loop or one gain stage and one dominant pole.
Analog Circuit Design :: 11-24-2008 04:48 :: surianova :: Replies: 4 :: Views: 1015
These are my observations:
1. R1, C1 to compensate the zero due to mirror T3-T4.
2. C4 creates pole as in the paper.
3. C3 compensates the zero due to T2 (it is almost like a capacitor from gate of T2 to drain of T1).
I am not sure about C5, and the role of T5 and T6 (some startup ?)
Analog Circuit Design :: 06-12-2007 16:33 :: panditabupesh :: Replies: 6 :: Views: 2044
I'd say that the poles can be divided into two groups:
-poles in the opamp: Miller pole and mirror pole (that should be the non-dominant one)
-poles of the LDO: there are those cause by the opamp, the loading of the pass device on the opamp will create another pole, and (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-13-2006 16:08 :: jonashat :: Replies: 6 :: Views: 1179
It can be generated by current mirror in differential amplifier... also in the case of pole-zero cancellation, when components are not perfectly matched.
The effect of pole-zero doublet could be not clearly seen in the amplitude and phase response, especiaqlly if the case if they are closed together, but relativlly small mismatch can have (...)
Analog Circuit Design :: 06-22-2006 18:22 :: pixel :: Replies: 12 :: Views: 11650