11 Threads found on edaboard.com: Mirror Pole
Hello Analog guys
I designed a current mirror OTA with a partial positive feedback, the circuit is like the one I attached from Gregorian book, Figure Nr. 3.41.
After I finished the design , I have simulated the circuit with and without the positive feedback as shown in the first and second image respectively.
Here I have a couple of ques
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-04-2013 14:01 :: Junus2012 :: Replies: 21 :: Views: 1314
dear every body
could you pls tell me what is the physical meaning of the mirror pole and rezo ?
many thanks in advance
Analog Circuit Design :: 06-29-2012 06:49 :: dinosaur078 :: Replies: 0 :: Views: 780
By lagging the feedback FET, you will add peaking / sharpness
to the rest of the mirror rack. This can of course be overdone.
Analog Circuit Design :: 06-10-2013 11:38 :: dick_freebird :: Replies: 3 :: Views: 838
why not increase the load capacitors? You can also reduce the ratio of the mirror branch to the ota branch to reduce the capacitance at the NMOS cascode node - this is your non-dominant pole. You may also want to increase the gm of the NMOS cascode devices.
Analog Circuit Design :: 06-27-2011 01:42 :: sutapanaki :: Replies: 4 :: Views: 1383
can you tell me the differences between "the basic differential pair" and "the differential with active current mirror" ?
i know the latter increases a "mirror pole", i.e., it has worse stability.
what are the other advantages and disadvantages of the two circuits ?
plz help me, thanks in advance.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-29-2011 23:10 :: sevid :: Replies: 9 :: Views: 2568
I am running a pole zero analysis via cadence spectre on a two stage opamp which consists of the classical diff pair with current mirror load and as second stage the classical common source/inverter problem is that i cannot see the RHP zero that is created via the feedforward path of the miller compensation capacitor...All t
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-26-2010 11:33 :: jimito13 :: Replies: 0 :: Views: 1525
like the figure, the solution is a pair of conjugate pole and zero.
but I think it should be a mirror pole and an output pole. why ?
And when I plot the frequence response (bode plot) , the position of pole is only
the real part of it ,or the amplitude of complex number.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-15-2009 21:30 :: wangkes9 :: Replies: 0 :: Views: 780
This is the popular wilson mirror. This is negative feedback and can become unstable. Do a websearch to know more about it.
i think shd be no problem because only have one inversion in the loop or one gain stage and one dominant pole.
Analog Circuit Design :: 11-23-2008 23:48 :: surianova :: Replies: 4 :: Views: 868
These are my observations:
1. R1, C1 to compensate the zero due to mirror T3-T4.
2. C4 creates pole as in the paper.
3. C3 compensates the zero due to T2 (it is almost like a capacitor from gate of T2 to drain of T1).
I am not sure about C5, and the role of T5 and T6 (some startup ?)
Analog Circuit Design :: 06-12-2007 12:33 :: panditabupesh :: Replies: 6 :: Views: 1922
I'd say that the poles can be divided into two groups:
-poles in the opamp: Miller pole and mirror pole (that should be the non-dominant one)
-poles of the LDO: there are those cause by the opamp, the loading of the pass device on the opamp will create another pole, and (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-13-2006 11:08 :: jonashat :: Replies: 6 :: Views: 1018
It can be generated by current mirror in differential amplifier... also in the case of pole-zero cancellation, when components are not perfectly matched.
The effect of pole-zero doublet could be not clearly seen in the amplitude and phase response, especiaqlly if the case if they are closed together, but relativlly small mismatch can have (...)
Analog Circuit Design :: 06-22-2006 14:22 :: pixel :: Replies: 12 :: Views: 10105