49 Threads found on edaboard.com: Modelsim Versions
Hi all! I am experiencing a very strange and rather frustrating problem while trying to run the same backannotated simulation in two different versions of modelsim. In both cases I am using exactly the very same files for everything, and also the same compilation and simulation commands. The old version (modelsim 5.8b) simulates fine and (...)
ASIC Design Methodologies and Tools (Digital) :: 17.01.2007 15:12 :: lagos.jl :: Replies: 0 :: Views: 663
a problem in post simulation using quartus2 4.2 and modelsim se6.0.
I first creat a project in quartus2 ,and in quartus 2 "setting" ->simulation tab,"tool name " i select "modelsim(vhdl)", and turn on "generate netlist for functional simulation only", and compile the design get a *.vho file,and copy this file and it's testbench into (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.03.2008 09:08 :: pwq1999 :: Replies: 2 :: Views: 599
It looks like you need to include the library where your fifo is compiled. Or, you failed to compile the fifo.
So, if what I said above is correct, you need to use library statements and use statements to bring in the unbound object.
If the internal_memory: fifo is compiled in a library other than "work", you will need to add
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.02.2011 13:33 :: Sckoarn :: Replies: 3 :: Views: 2156
Which HDLSim tool is better(performance), like NC-Sim, VCS, modelsim ...?
Professional Hardware and Electronics Design :: 19.05.2001 12:57 :: wzj :: Replies: 12 :: Views: 2606
Yesterday I generate modelsim license using ef@licgen.
It can't works.
I changed pc's date backward and regenerate license.
Then change pc's date now.
modelsim works well.
I tested another pc. Same problem.
Anyone have the same problem ?
Sorry my bad English.
Linux Software :: 08.04.2003 21:26 :: DongSun Park :: Replies: 3 :: Views: 2106
can Mandrake 10 be used for LDV,modelsim,DC,PT
Have anyone tried .. which versions of these EDA u have tried?
which is the best mandrake version for these toools
Linux Software :: 16.07.2004 22:52 :: eda_wiz :: Replies: 1 :: Views: 747
I have been trying to update my simulator to modelsim SE 5.8c and modelsim SE 6.0 and I have not being able to run a simulation, when I add the signals to the waveform window, modelsim closes without reporting any error. I have tried the two different versions and in different PCs with W2K and Win XP and I did not succed. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.03.2005 08:40 :: zape :: Replies: 3 :: Views: 929
Help me! modelsim Error when Start Up
I can NOT start up my modelsim after I missed changing a setting in modelsim pe 6.0. I uninstalled the modelsim 6.0 and delteled the installation directory, reinstalled the modelsim 6.0, but I can not start up the modelsim too. Updating the (...)
Software Problems, Hints and Reviews :: 01.12.2005 04:16 :: mountain :: Replies: 1 :: Views: 877
Currently, I’m using ISE v7.1i with modelsim SE as the simulator.
Previously, I’ve synthesized my code with DC and verified it with NC-Verilog. No problem.
But now, I want to transfer my rtl into Spartan-II. In ISE project navigator, I ran a post-translate simulation. It showed this error in modelsim SE 6.0D:
# ** E
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.12.2005 04:43 :: no_mad :: Replies: 9 :: Views: 7143
which version of link for modelsim integrate with modelsim 5.8
Digital Signal Processing :: 20.09.2006 07:01 :: dsp_forall :: Replies: 4 :: Views: 671
As angelote suggested, Xilinx ISE WebPACK is free and contains a lite version "modelsim XE III Starter":
Mentor sells several more advanced versions. The full featured "modelsim SE" costs approximately $20000 US dollars.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.09.2006 04:33 :: echo47 :: Replies: 8 :: Views: 2290
Altera and Xilinx provide a "light" version of modelsim. It is fine for small projects, but it has some limitations and runs much slower than the full version of modelsim. However, modelsim PE costs around $5000, and modelsim SE costs around $20000 US.
More info on the Xilinx version:
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.02.2007 08:53 :: echo47 :: Replies: 4 :: Views: 615
hello, i got a problem recently. i use modelsim 6.0a before to do systemc work and it was ok. but recently i updated the modelsim to 6.2c version and it has problem.
when i run sccom command. it says:
# ** Error: (sccom-95) Your installation directory does not contain the appropriate GNU C++ compiler. Download and install the tarball from the
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.04.2007 15:50 :: fanqimeng :: Replies: 7 :: Views: 7762
can somebody tell me the differences between modelsim SE EE PE ?
And equally which of them is supirior.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2007 12:31 :: ddboy40 :: Replies: 6 :: Views: 3607
A couple years ago, Synplify Pro was about $20K (US dollars), modelsim SE about $20K, HyperLynx GHz about $47K. The lighter versions were roughly a third of that.
Xilinx stuff: ISE Foundation about $3000. WebPACK is of course free. EDK about $500. System Generator for DSP about $1000.
Yearly support is usually an unpleasant fraction of the pu
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.06.2007 21:10 :: echo47 :: Replies: 1 :: Views: 2700
Look at what versions of the modelsim program are compatible with your Altera libraries?
ASIC Design Methodologies and Tools (Digital) :: 09.10.2007 11:23 :: gliss :: Replies: 1 :: Views: 2094
I was wondering to hear opinions about aldec/modelsim.
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.01.2008 02:50 :: mImoto :: Replies: 3 :: Views: 2852
Are the latest versions of modelsim backward compatible with SE 5.8C ?
I'd like to see if designs made with later versions can be imported to this version.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.01.2008 14:42 :: Zeppelin :: Replies: 4 :: Views: 547
Some student versions will not allow to use complete set of of "option" switch while simulating. You can just check-out FAQs of modelsim for the simulation with encrypted verilog files. Pressumes that without encryption your design are getting simulated.
Try to do the verror number in your simulator also for finding out the root cause
ASIC Design Methodologies and Tools (Digital) :: 01.06.2009 02:18 :: paulki :: Replies: 11 :: Views: 3985
Everything you need to know is right here:
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.02.2010 05:19 :: Jack// ani :: Replies: 2 :: Views: 622
I have installed modelsim pe student edition and i got a license for it through mail. I have placed license in appropriate folder as per mail instruction. so does any of you have idea that why it is not working?
Software Problems, Hints and Reviews :: 20.09.2011 02:02 :: dhaval004 :: Replies: 3 :: Views: 691
I'm trying to use the hread procedure from std_logic_textio.vhd from synopsys in modelsim and I'm running into some trouble. Currently my vhdl testbench throws an error during compilation saying: "Unknown identifier "hread".
Here's what I have done:
1. I've added std_logic_textio.vhd to the Project in modelsim from C:\modeltech_6.5c\vhdl_sr
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.09.2011 21:38 :: RoldGold :: Replies: 5 :: Views: 2441
When compiling my program, the following error is being printed:
Library lpm not found.
Is there anything i can do to resolve that in modelsim?.....
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.04.2012 06:32 :: nehsr :: Replies: 1 :: Views: 449
since the modelsim official website has closed the download links of "modelsim v6.5 se", who can tell me where I can get it?if anyone who can send the software to me,I will be very grateful.
my email is email@example.com
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.07.2012 01:37 :: xungloo :: Replies: 2 :: Views: 470
Use only one initial block. Secondly does modelsim 10.1d PE support system verilog?
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.02.2013 15:07 :: tariq786 :: Replies: 6 :: Views: 677
modelsim eventually supported nested class declarations in versions after 10.1
But the example code you show here will never compile because there is a missing endclass. Even with nested classes, there needs to be a matching endclass for each class declaration. The error message is misleading because the intent was never to have an nested c
ASIC Design Methodologies and Tools (Digital) :: 01.03.2013 11:49 :: dave_59 :: Replies: 4 :: Views: 308
Early versions of modelsim do not support untyped mailboxes.
My recommendation is to always use typed mailboxes anyways - it is safer.
// parameter type T = bit;
mailbox #(packet) mbx;
function new(mailbox#(packet) mbx);
this.mbx = mbx;//(100);
task run(int count);
repeat (count) begin
pkt = new();
ASIC Design Methodologies and Tools (Digital) :: 22.05.2013 03:31 :: dave_59 :: Replies: 1 :: Views: 390
Is anyone here using modelsim 5.6a (or modelsim Altera 5.6a) ?
I have a few problems on running simulations.
My flexlm license.dat :wink: does pass the checking at startup. However, it saids "# ** Error: Failure to obtain a VHDL simulation license." everytime I try to run the simulation.
Can anyone give me a hand on this ??
Software Problems, Hints and Reviews :: 14.07.2003 05:31 :: cyu021 :: Replies: 6 :: Views: 1904
The xilinx Spartan III board is in fact made by Digilent, but is subsidised by Xilinx.
From the Digilent website their $89 board is loaded with a 50K gate device, as opposed to the 200k device on the $99 'Xilinx' board.
Evaluation versions of ISE 6.2i and modelsim 5.7g (xilinx edition) are also supplied with the $99 kit.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.07.2004 13:48 :: Beetroots :: Replies: 4 :: Views: 4047
If you can somehow scrape up only $99 US, you can buy the Xilinx High Volume Starter Kit. It includes a Spartan-3 board, a CPLD board, cables, manuals, and starter software:
Or you can simply download the free development software (ISE WebPACK). It i
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.01.2006 08:40 :: echo47 :: Replies: 2 :: Views: 729
Yes, I have ISE 4.2i, 6.3i, 7.1i, and 8.1i all installed. I simply change that XILINX environment variable when I want to switch between them.
Don't try to share anything between versions. Do full installations into separate folders.
I don't use Project Navigator. I build my projects using a command line makefile. That makes it really easy to
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.02.2006 16:52 :: echo47 :: Replies: 5 :: Views: 1511
Why can't you try modelsim or OrCAD. If the symbols are not available in their libraries, You can get them from the vendors by request.
Analog Circuit Design :: 13.04.2006 08:29 :: vishwa :: Replies: 10 :: Views: 5006
u down loas the max plus -2 from altera r modelsim for student version.
if is available on net
Analog IC Design and Layout :: 28.07.2006 05:15 :: manissri :: Replies: 9 :: Views: 749
SV is not a simulator,it is an advanced feature of Verilog.
Which can be used for System level design,Synthesisable RTL design and
can be used for Verification to interface C to ur Verilog or SV code.
Verilog95 ---> Verilog 2001 ----> SystemVerilog.
So any simulator which u are working earlier(modelsim or NcVerilog or VCS)
will be ok,provide
ASIC Design Methodologies and Tools (Digital) :: 21.03.2007 01:06 :: samuraign :: Replies: 8 :: Views: 1319
you can doenload it from the internet.
1. go to this link:
2. select modelsim se under windows
3. register using any name and press "request download"
4. new window will apear with username and password write it down
5. connect to that FTP
if you have
Software Requests :: 12.10.2006 12:28 :: rancohen_2000 :: Replies: 5 :: Views: 330
you cam download qurttus web edition from Altera website it is also including modelsim
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.02.2007 11:47 :: Iouri :: Replies: 3 :: Views: 613
use AES in modelsim
ASIC Design Methodologies and Tools (Digital) :: 15.06.2007 10:19 :: spauls :: Replies: 5 :: Views: 1526
There are many commercial EDA tools for simulating VHDL. On a PC running under WinXP :
modelsim from Mentor
ActiveHDL from Aldec
Are very good tools.
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.07.2007 17:43 :: Toki :: Replies: 7 :: Views: 666
Both Xilinx and Al.tera have *free* versions of their development software. You could download it today and try it out. Xilinx ISE WebPACK includes two HDL simulators: modelsim XE III Starter, and ISE Simulator Lite.
I'm not familiar with Al.tera's software:
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.10.2007 10:32 :: echo47 :: Replies: 8 :: Views: 1036
I used Clocking Wizard to initiate the DCM
when I assign the CLK2X_OUT to my OUTCLK port, I couldnt see anything when I simulate it in modelsim. But when I assign CLK0_OUT instead, I can see the waves... am I on the right track?
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.06.2008 21:46 :: Zhane :: Replies: 9 :: Views: 1333
I am writing VHDL code, i am using log2 function there. At the beginning of file i have the following declarations:
during compile in modelsim 6.1b i've got the following error:
** Error: C:/PROJECTS/models
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.09.2008 05:08 :: BlackOps :: Replies: 2 :: Views: 3033
hi , i know that modelsim is used for simulating vhdl codes , but i dont know waht is questa sim and what does it do and how it works ?
can any body help me ?
thanks in advanced
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2009 10:00 :: omidsht :: Replies: 3 :: Views: 7691
you can downld the student version of the modelsim or Icarus.
I have used modelsim but heard Icarus is good and free simulator.
You can start learning Verilog by the author Samir Palnitker.
ASIC Design Methodologies and Tools (Digital) :: 19.06.2009 08:19 :: haneet :: Replies: 4 :: Views: 986
I don't understand your question. You would simulate this using a simulator like modelsim, activeHDL, etc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.12.2011 07:50 :: barry :: Replies: 21 :: Views: 1073
hi guys, Has anybody downloaded or used Xilinx ISE 13.3 webpack edition recently which is about 4.9GB?. My concern is what are the current limitations offered in this webpack (like any device limitation\chipscope\ISIM\floorplanner etc) and I could not also find Xilinx modelsim version along with this package, why is that?.
If this is the case,
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.01.2012 08:01 :: xtcx :: Replies: 14 :: Views: 3306
don't forget to download software modelsim also to generate waveform for your coding....
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.05.2012 12:24 :: poad_87 :: Replies: 3 :: Views: 339
The following happens in modelsim :
signal noise : std_logic := '0' ;
signal stable_one : std_logic ;
signal x : std_logic ;
stable_one <= '1' ;
noise <= not noise after 100 ns ;
x <= noise , stable_one after 10 ms ;
I expected that signal 'x' will stabilize to a stable log
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.10.2012 11:16 :: shaiko :: Replies: 8 :: Views: 317
you dont need to compile textio, its already included in modelsim.
the standard_textio_additions is a VHDL 1993 version of the VHDL 2008 additions. A newer version of modelsim will support this by default (so you dont need to include it).
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.11.2012 11:32 :: TrickyDicky :: Replies: 8 :: Views: 737
modelsim 6.3f is very old. How about updating to 10.1?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.03.2013 04:07 :: TrickyDicky :: Replies: 2 :: Views: 241