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Hi all! I am experiencing a very strange and rather frustrating problem while trying to run the same backannotated simulation in two different versions of modelsim. In both cases I am using exactly the very same files for everything, and also the same compilation and simulation commands. The old version (modelsim 5.8b) simulates fine and (...)
a problem in post simulation using quartus2 4.2 and modelsim se6.0. I first creat a project in quartus2 ,and in quartus 2 "setting" ->simulation tab,"tool name " i select "modelsim(vhdl)", and turn on "generate netlist for functional simulation only", and compile the design get a *.vho file,and copy this file and it's testbench into (...)
snehanidhi, It looks like you need to include the library where your fifo is compiled. Or, you failed to compile the fifo. So, if what I said above is correct, you need to use library statements and use statements to bring in the unbound object. If the internal_memory: fifo is compiled in a library other than "work", you will need to add
Which HDLSim tool is better(performance), like NC-Sim, VCS, modelsim ...? Thanks!
Yesterday I generate modelsim license using ef@licgen. It can't works. I changed pc's date backward and regenerate license. Then change pc's date now. modelsim works well. I tested another pc. Same problem. Anyone have the same problem ? Sorry my bad English.
HI all can Mandrake 10 be used for LDV,modelsim,DC,PT Have anyone tried .. which versions of these EDA u have tried? which is the best mandrake version for these toools thanks whizzkid
I have been trying to update my simulator to modelsim SE 5.8c and modelsim SE 6.0 and I have not being able to run a simulation, when I add the signals to the waveform window, modelsim closes without reporting any error. I have tried the two different versions and in different PCs with W2K and Win XP and I did not succed. (...)
Help me! modelsim Error when Start Up I can NOT start up my modelsim after I missed changing a setting in modelsim pe 6.0. I uninstalled the modelsim 6.0 and delteled the installation directory, reinstalled the modelsim 6.0, but I can not start up the modelsim too. Updating the (...)
Can you show us a small example project that produces the error? Maybe someone can see the problem, or at least try it on different versions of ISE and modelsim. If you don't have the latest versions (7.1.04i and 6.1c), try updating them, especially ISE. My X_FF.v file doesn't have any $recovery statements. Maybe submit a Xilinx (...)
which version of link for modelsim integrate with modelsim 5.8
As angelote suggested, Xilinx ISE WebPACK is free and contains a lite version "modelsim XE III Starter": Mentor sells several more advanced versions. The full featured "modelsim SE" costs approximately $20000 US dollars.
BOth altera and xilinix are distributing modelsim .. Am i right ? Do Both the versions are equally good? Added after 19 minutes: One more doubt... why need to use modelsim along with quartus in altera designa.. i think quartus have enough tools... I am a newbie.. forgive me if i made a mistake... Plz repl
hello, i got a problem recently. i use modelsim 6.0a before to do systemc work and it was ok. but recently i updated the modelsim to 6.2c version and it has problem. when i run sccom command. it says: # ** Error: (sccom-95) Your installation directory does not contain the appropriate GNU C++ compiler. Download and install the tarball from the
can somebody tell me the differences between modelsim SE EE PE ? And equally which of them is supirior. Thnx
A couple years ago, Synplify Pro was about $20K (US dollars), modelsim SE about $20K, HyperLynx GHz about $47K. The lighter versions were roughly a third of that. Xilinx stuff: ISE Foundation about $3000. WebPACK is of course free. EDK about $500. System Generator for DSP about $1000. Yearly support is usually an unpleasant fraction of the pu
Hi all, Error: This version of the compiler is incompatible with library file "work/mt48lc2m32b2/_primary.dat". # child process exited abnormally # ** Error: Sub-invoking of C:\altera\61\modelsim_ae\win32aloem/vlog failed; return status = 1. # ** Error: (vsim-3171) Could not find machine code for 'work.mt48lc2m32b2'. # Operation not permitted.
modelsim is so primitive it is hard to beleive why it is so popular. (microsoft ?) what mentor does today is just to take this old software and criple it to se, pe, xe , starter, xilinx , altera versions. the only thing they do is put loop delays inside. every new version they come up with force you to compile all your files and packages.
Are the latest versions of modelsim backward compatible with SE 5.8C ? I'd like to see if designs made with later versions can be imported to this version. Thank You
Dear All, I've encrypted some of my design files using "vencrypt" (i've tried with +protect option also). After proper encryption, Ive used those encrypted files for simulations. But it is giving the following Fatal Error after running the VSIM command. Compilation (VLOG..) of those files were successful. ** Fatal: Attempting to load -n
Everything you need to know is right here:
Have you set a system environment variable LM_LICENSE_FILE? This should point to your license eg LM_LICENSE_FILE=c:\modelsim\license\license.dat or something like that depending on where you put the file and what it is called
thats not how it works. std_logic_textio is part of the ieee library, so in your code you just add the lines: library ieee; use ieee.std_logic_textio.all; secondly, if you did compile it into work, you would not add work.all; it would be work.std_logic_textio.all; Then you have access to hread. Including it in work means you wont get the
create the lpm library and map it to the pre-compiled versions as provided by modelsim-AE. You can download modelsim-AE from the altera website for free, and they contain all the libraries you need.
Request a trial for the current version, get an url to ftp server + a login, and download the older modelsim version from the same ftp server. At least that's how it used to be. Good luck!
Use only one initial block. Secondly does modelsim 10.1d PE support system verilog?
modelsim eventually supported nested class declarations in versions after 10.1 But the example code you show here will never compile because there is a missing endclass. Even with nested classes, there needs to be a matching endclass for each class declaration. The error message is misleading because the intent was never to have an nested c
Early versions of modelsim do not support untyped mailboxes. My recommendation is to always use typed mailboxes anyways - it is safer. class generator; packet pkt; // parameter type T = bit; mailbox #(packet) mbx; function new(mailbox#(packet) mbx); this.mbx = mbx;//(100); endfunction task run(int count); repeat (count) begin pkt = new(); voi
Hi all, Is anyone here using modelsim 5.6a (or modelsim Altera 5.6a) ? I have a few problems on running simulations. My flexlm license.dat :wink: does pass the checking at startup. However, it saids "# ** Error: Failure to obtain a VHDL simulation license." everytime I try to run the simulation. Can anyone give me a hand on this ?? Any
The xilinx Spartan III board is in fact made by Digilent, but is subsidised by Xilinx. From the Digilent website their $89 board is loaded with a 50K gate device, as opposed to the 200k device on the $99 'Xilinx' board. Evaluation versions of ISE 6.2i and modelsim 5.7g (xilinx edition) are also supplied with the $99 kit.
If you can somehow scrape up only $99 US, you can buy the Xilinx High Volume Starter Kit. It includes a Spartan-3 board, a CPLD board, cables, manuals, and starter software: Or you can simply download the free development software (ISE WebPACK). It i
Yes, I have ISE 4.2i, 6.3i, 7.1i, and 8.1i all installed. I simply change that XILINX environment variable when I want to switch between them. Don't try to share anything between versions. Do full installations into separate folders. I don't use Project Navigator. I build my projects using a command line makefile. That makes it really easy to
Why can't you try modelsim or OrCAD. If the symbols are not available in their libraries, You can get them from the vendors by request.
u down loas the max plus -2 from altera r modelsim for student version. if is available on net
SV is not a simulator,it is an advanced feature of Verilog. Which can be used for System level design,Synthesisable RTL design and can be used for Verification to interface C to ur Verilog or SV code. Verilog95 ---> Verilog 2001 ----> SystemVerilog. So any simulator which u are working earlier(modelsim or NcVerilog or VCS) will be ok,provide
Hi, welcom aboard, you can doenload it from the internet. 1. go to this link: 2. select modelsim se under windows 3. register using any name and press "request download" 4. new window will apear with username and password write it down 5. connect to that FTP if you have
you cam download qurttus web edition from Altera website it is also including modelsim
hello frndz, i hav a verilog code which i want to encrypt using modelsim so that the final file is in the format such as "1010.." so that the user doesnt know wht the code is but is successful in using the file in his application. thanks in advance
There are many commercial EDA tools for simulating VHDL. On a PC running under WinXP : modelsim from Mentor ActiveHDL from Aldec Are very good tools.
Both Xilinx and Al.tera have *free* versions of their development software. You could download it today and try it out. Xilinx ISE WebPACK includes two HDL simulators: modelsim XE III Starter, and ISE Simulator Lite. I'm not familiar with Al.tera's software:
I used Clocking Wizard to initiate the DCM when I assign the CLK2X_OUT to my OUTCLK port, I couldnt see anything when I simulate it in modelsim. But when I assign CLK0_OUT instead, I can see the waves... am I on the right track?
Hello, I am writing VHDL code, i am using log2 function there. At the beginning of file i have the following declarations: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; during compile in modelsim 6.1b i've got the following error: ** Error: C:/PROJECTS/models
hi , i know that modelsim is used for simulating vhdl codes , but i dont know waht is questa sim and what does it do and how it works ? can any body help me ? thanks in advanced omid sharifi
you can downld the student version of the modelsim or Icarus. I have used modelsim but heard Icarus is good and free simulator. You can start learning Verilog by the author Samir Palnitker.
I don't understand your question. You would simulate this using a simulator like modelsim, activeHDL, etc.
hi guys, Has anybody downloaded or used Xilinx ISE 13.3 webpack edition recently which is about 4.9GB?. My concern is what are the current limitations offered in this webpack (like any device limitation\chipscope\ISIM\floorplanner etc) and I could not also find Xilinx modelsim version along with this package, why is that?. If this is the case,
don't forget to download software modelsim also to generate waveform for your coding....
not really noise if it toggles like that ;) Anyway, I dont quite get it either, assuming that really is 10 ms (sure its not 10 us? ). Have you tried other versions of modelsim? have you raised a support request?
you dont need to compile textio, its already included in modelsim. the standard_textio_additions is a VHDL 1993 version of the VHDL 2008 additions. A newer version of modelsim will support this by default (so you dont need to include it).
modelsim SE 6.3f has option for system verilog files,but does it support its testbenches and verification.? Do we have free simulators for system verilog?