292 Threads found on edaboard.com: Monte And Carlo
I'm gonna use monte carlo Analysis to find standard deviation for input Offset of a latched Comparator using icfb 5.10.41_USR5.90.69. the goal is to plot it against a voltage value called Common Mode Voltage. It is to some extent a parametric monte carlo analysis. But it seams this version cant (...)
Software Problems, Hints and Reviews :: 03-26-2017 18:45 :: moammadhasan :: Replies: 1 :: Views: 643
Hi All, I have a question about the Cadence operation for the MC simulation for the BGR. Normally, we can specify a temperature and run the DC analysis of a BGR to get the historgram of Vref at this temperature. However, are we able to run the MC sim with different profiles at different temperatures at the mean time?
For example, this is a measur
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-25-2017 05:23 :: bhl3302 :: Replies: 2 :: Views: 618
After running some monte carlo simulations in a current mirror, I would like to compute the amount of mismatch in percentage.
To compute the mismatch in percentage I should do it taking into account the (3 sigma * std. deviation) or just the std. deviation?
For example I see people saying that the current mirror has 5% of mismatc
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-04-2016 18:51 :: CAMALEAO :: Replies: 4 :: Views: 616
MNA-MAT, a MATLAB based analog circuit simulation tool, uses Modified Nodal Analysis to reduce a SPICE netlist to a system of equations which yield voltage at and current through specific points in the network. monte carlo analysis adds further functionality by evaluating possible uncertainties in real-world working conditions.
Business, Promotions, Advertising :: 09-02-2016 14:15 :: nik1106 :: Replies: 0 :: Views: 791
I am running cadence virtuoso 6.1.5 and trying to sort out the monte carlo analysis for process variation and mismatch.
I want to plot the gain vs frequency plot of a single-ended amplifier for 10 runs i.e. I want to see the 10 gain-curves in a graph window.
The only option in EVAL TYPE in OUTPUT SETUP of the (...)
Software Problems, Hints and Reviews :: 09-01-2016 11:58 :: Debdut :: Replies: 0 :: Views: 573
I think studying the spice model in analysis process then set parameter in spice program to more practical and proper for purpose . Pspice has monte carlo analysis option , But no 3D graphics result shown .
RF, Microwave, Antennas and Optics :: 08-20-2016 11:15 :: phongphanp :: Replies: 3 :: Views: 923
I would like to make a small experiment regarding current mismatch in a current mirror for different transistors area (or sizes).
I know that we have to do that using monte carlo (or maybe the dcmatch can work, I don't know). But the thing is how should I do the calculation to get the mismatch? and should I use any kind of (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-03-2016 15:56 :: AMSA84 :: Replies: 1 :: Views: 455
It looks like you are making MC simulation with a normal lib.scs. You should add the monte-carlo lib.scs file to Model Files.
You can add the mc.lib.scs file as a new corner.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-28-2016 12:39 :: vadim888 :: Replies: 4 :: Views: 874
For an LNA design, the inductors used in the design were simulated in a simulation software separate from the spectre simulator used in cadence for the other components (transistors, resistors, capacitors). So we created a n-port file for the inductors in the design and made it point to the S-parameter file generated by the inducto
Software Problems, Hints and Reviews :: 07-19-2016 17:42 :: mzzim :: Replies: 0 :: Views: 522
I have designed too many op amps and none of them have any issue with a wide range variations of supply voltage , temperature , corners of process , worst case pvt circumstances , etc . but the problem is the monte carlo analysis by which my op amps are all totally devastated .I know the monte carlo analysis (...)
Analog Circuit Design :: 07-16-2016 16:11 :: kevin_microelecrronic :: Replies: 0 :: Views: 346
Hi! I am trying to model an Arbiter PUF in Hspice. You can google it if you don't know what that is. So I am trying to implement the delay differences in the multiplexers due to process variations. In order to do that I have to run monte carlo simulations using hspice and vary the oxide thickness and the threshold voltage of (...)
Software Problems, Hints and Reviews :: 07-04-2016 09:36 :: kanishk29 :: Replies: 0 :: Views: 761
Has anyone used BJT available in TSMC65? There are pnp and npn transistors in the library and can be used.
I wonder if any one has simulated monte carlo for those BJT. For MOS, one should replace "_mac" transistor and add "stat_mis" library. How about BJT? there is no "_mac" file to be replaced! (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-18-2016 00:38 :: vaah :: Replies: 1 :: Views: 477
I'm trying to solve a problem I was tasked with.
Basically I have to generate a 100k 16QAM inputs and transmit them over a AWGN channel.
With this I have to use the monte-carlo estimation to figure out the mutual information.
I was told to use this estimation:
So I generated the input vector, the
Digital communication :: 05-15-2016 17:02 :: knoluis :: Replies: 0 :: Views: 513
I am trying to run the monte carlo analysis of the offset voltage of a comparator.
For this, I am using the 'cross' function from Cadence calculator. The expression I use is the following one:
cross(VDC("/OUT_SF") 0.9 0 "either" t "time"),
where OUT_SF is the output of my comparator and 0.9 is my threshold value. Befo
ASIC Design Methodologies and Tools (Digital) :: 04-08-2016 10:08 :: evilella :: Replies: 2 :: Views: 1059
Im using Cadence 6.1.3 and Id like to do monte carlo simulation. I found out that "m" shouldnt be used in schematic or monte carlo might be errorous. source:
So I decided to test it:
ASIC Design Methodologies and Tools (Digital) :: 03-29-2016 19:22 :: Gornarok :: Replies: 1 :: Views: 560
It will likely work close to your simulation results if you follow proper design procedures such as a good layout, heat sinking, and supply decoupling, but no guarantee.
If you can, do some monte carlo simulation multiple runs to see how component variations (including supply voltage variation and offset) affects the amp (...)
Analog Circuit Design :: 03-20-2016 08:18 :: crutschow :: Replies: 14 :: Views: 1477
I am working on an SRAM cell for which I have to perform monte-carlo simulation.
During MC simulation in ADEXL window, we found a pop up window with the following error messages after 10 min, while the 6T SRAM cell was run for 100ns for 2 samples. Please help in this matter.
ADEXL-1921: failed to start new job afte
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-04-2016 05:39 :: akchetana :: Replies: 4 :: Views: 978
After many hours searching and reading the tutorials for offset calculation, I don't know what should I do.
here is my codes. please help me to complete it.I don't understand how to write codes for DCMATCH or monte carlo simulation and how to extract the information.
ASIC Design Methodologies and Tools (Digital) :: 02-23-2016 18:36 :: canarybird33 :: Replies: 2 :: Views: 1148
My file is below. I want to see the effect of aging on circuits with process variation. But I cannot append mosra and consider monte carlo sweep =3 (or any number) at the same time. Could yo please help me. Thanks
Also the manual says montecarlo works only with simmode=1 but fopr that I need to first use (...)
Electromagnetic Design and Simulation :: 01-06-2016 19:29 :: user_2015 :: Replies: 3 :: Views: 587
Perhaps this tutorial can be helpful: 123718
... in monte carlo analysis-> in analysis variation why do we have process only, mismatch only and process and mismatch. Can someone pls tell whats the actual difference.
See p. 15 of the above tutorial.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-02-2015 19:35 :: erikl :: Replies: 4 :: Views: 825
I have a question about hspice. I want to simulate a basic ring oscillator with variation block & monte carlo simulation in hspice, & this is my code:
*CMOS Ring Oscillator
V1 vdd 0 0.9V
V2 vss 0 0V
.subckt inv vdd vss in out
Mp1 vdd in out vdd pmos l=0.35u w=20.0u
Mn1 vss in out vss nmos l=0.35u w=10.0u
Analog Circuit Design :: 11-28-2015 12:59 :: lili94 :: Replies: 4 :: Views: 1396
Hello, As you know, PVT simulation is process, voltage and temperature.
About process simulation, you can use monte carlo simulation ( samples > 10). To voltage simulation, you will change voltage supply. For example, voltage supply is 3.3 V, you can run 3.2-3.4V and may be plus Vsin (noise). To temperature simulation, (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-26-2015 06:36 :: nguyenvanthien :: Replies: 1 :: Views: 1286
Could any one show me how to run monte carlo from command line.? I do not have ADE XL simulator.
Software Problems, Hints and Reviews :: 11-21-2015 04:44 :: twain :: Replies: 1 :: Views: 572
Hi I am designing a two stage OTA using CADENCE . Need to run monte carlo simulation for offset voltage. can somebody give me any user guide.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-30-2015 05:22 :: vinogunasekaran :: Replies: 1 :: Views: 859
What did you change as against the previous simulation?
Here is the monte carlo simulation for both process and mismatch variation for a 3-bit flash ADC. What do you conclude from this plot ?
Library I am using is L130E_HS12_V241_MC_CORNER.lib.scs
The ADC will not work over corners, process and mismatc
Analog Circuit Design :: 09-22-2015 14:49 :: erikl :: Replies: 19 :: Views: 1523
hi dear friend.
i have cadence 6.1.4.
how i to run parametric analyse in monte carlo simulation?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-01-2015 14:09 :: rey1991 :: Replies: 2 :: Views: 622
I'm working with TSMC 180nm and try to run Montre Calro Mismatch simulation.
I can see the parameters variation of Porcess Analysis but for Mismatch Analysis there is no variation in parameters.
I tried to check the variation of toxnmis or other parameters variation which are defined in mismatch section, but all parameters are 0 for all i
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-12-2015 13:39 :: m_mehri65 :: Replies: 7 :: Views: 1365
I am trying to setup a monte-carlo simulation given a spef file. In this spef file, is modeled equations which can be solved based on the command line parameters which i want to specify as inputs to monte-carlo as opposed to the analog components like voltage, Resistance and so on (...)
ASIC Design Methodologies and Tools (Digital) :: 06-05-2015 16:17 :: dmsp8 :: Replies: 0 :: Views: 571
What are the tolerances on the resistors? This will play a significant role and even more with temperature changes. You may have to do a worst case or a monte carlo analysis to see this.
Power Electronics :: 05-27-2015 17:58 :: E-design :: Replies: 15 :: Views: 1065
When I run monte carlo simulation it shows,
Warning 369: COMMand ignored: No LOT or DEV specification found
ERROR 26: No analysis specified
what does it mean?
Analog Circuit Design :: 05-27-2015 09:50 :: jayapraksh :: Replies: 2 :: Views: 740
Be neither obsessive nor a procrastinator, so to speak. Rather, be timely. Do it ATAP. So soon or late also has factors of probability of being wrong from tolerances and exceptions to mean, thus the precise algorithm must consider all potential variances and the probabilities to yield an optimal schedule. monte carlo (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-11-2015 15:57 :: SunnySkyguy :: Replies: 2 :: Views: 934
In general I would expect DRC and monte carlo methods will determine critical timing and path length issues. Critical path (shortest latency) results should come out of a manual or auto generated set of test vectors in combinational and sequential table and generate the results which could (...)
ASIC Design Methodologies and Tools (Digital) :: 04-28-2015 20:39 :: SunnySkyguy :: Replies: 2 :: Views: 692
I am in the beginning stage of my research and I am trying to reproduce the output for Arbiter PUF, which I am struggling at one point now from almost two months now. I would be very grateful if you can just give me a hint on it.
I am trying to implement the PUF on Cadence Virtuoso and Struggling with introducing process variation. My (...)
Analog Circuit Design :: 04-22-2015 20:50 :: jshital :: Replies: 6 :: Views: 879
To me it doesnt look that you are doing a monte carlo simulation: you can see this in the toolbar "Single Run, Sweeps and Corners". This should be monte carlo Analysis
Then on the error you are getting, it seems you are having a network/server error. Are you running the job locally?
ASIC Design Methodologies and Tools (Digital) :: 03-27-2015 12:35 :: chris.mourad :: Replies: 3 :: Views: 628
How to apply monte-carlo simulations to find optimum size of a circuit like flip-flop in HSPICE?
Analog Circuit Design :: 03-16-2015 13:49 :: electronics20 :: Replies: 1 :: Views: 634
Run a monte carlo analysis - if your transistor models include mismatch and/or process variance parameters - and display the delay measurement statistics ordered in your control file.
Analog Circuit Design :: 03-13-2015 12:40 :: erikl :: Replies: 1 :: Views: 469
How to achieve curve of "number of samples" versus, for instance, current in monte-carlo method and simulation for a simple MOS circuit? thanks for your helps.
Analog Circuit Design :: 03-13-2015 04:55 :: electronics20 :: Replies: 2 :: Views: 459
I am running monte carlo (MC) simulations for a big circuit in cadence and saw that mismatches would significantly affect the performance of the circuit. Now I want to figure out which part is more sensitive and redesign.
In ADEXl you cannot have direct plot to look at the voltage of each node (as far as I know), (...)
Analog Circuit Design :: 03-01-2015 17:31 :: mordak :: Replies: 5 :: Views: 716
Hi, Every foundry units research on reliability phenomenons like NBTI before developing suitable models. Hence I believe that doing corner analysis and monte carlo simulations would take care of NBTI effects as well. It may not be included in Typical performace models of MOSFETs. Thanks.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-01-2015 07:45 :: srinivasan_b1 :: Replies: 5 :: Views: 936
I had enough trouble from the stb analysis (coming up
with absurd operating points and giving way-bogus loop
gain) that I gave up on it and went back to old school
methods. You just can't trust it to work each and every
time, like you need to ever get through your monte carlo
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-14-2015 19:58 :: dick_freebird :: Replies: 1 :: Views: 1037
I want to do monte carlo simulation with Gaussian distribution for W/L (width/length) in HSPICE in 0.35um CMOS technology.
How much variation percent should I consider ? and why?
Analog Circuit Design :: 12-07-2014 17:42 :: an_82 :: Replies: 1 :: Views: 646
Please tell me how to decrease the mismatch and increase the yield of my designed Operational Amplifier, as during the monte carlo simulation for yield analysis, the open loop gain drops too large from the gain value it has been designed for. Any help would be highly appreciated.
Thanks in advance.[/QUOT
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-27-2014 01:05 :: BigBoss :: Replies: 6 :: Views: 1123
In transistor level circuits for smaller technology nodes, the on-chip process
variations causes many reliability issues. To find the probability distribution of circuit delay I would like to do
a monte carlo simulation by sampling channel length distribution of each transistor randomly and find the circuit delay for (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2014 14:06 :: arunkumarv :: Replies: 0 :: Views: 569
It depends on the tools and PDK. Some PDK's have different transistors in the library for monte carlo simulations. In other PDK's it's an option in the transistor properties.
In AdeXL you can also select which devices should be included in the monte carlo analysis.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-04-2014 17:54 :: beetwee :: Replies: 8 :: Views: 1825
monte carlo Analysis Histogram
Today at 11:34am Quote Modify Hi All,
I am designing a current conveyor and I am doing monte carlo Analysis(by varying width and length of transistor) for Current gain , voltage gain and Rx,Ry & Rz. I am using code as given below:
Vdd 5 0 (...)
Microcontrollers :: 10-13-2014 18:37 :: zulqar :: Replies: 1 :: Views: 655
I want to do monte carlo analysis of a circuit by varying its device width . I am writing the syntax as given below :
and the using sweep monte=30 in ac analysis. Everything is fine upto this point but when I rewrite the syntax as below
.param W1=gauss(2.072u,0.0667,3) (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-01-2014 19:11 :: zulqar :: Replies: 4 :: Views: 1213
If you have mismatch (Avt) parameters from the foundry/fab you can calculate worst case offset values for adjacent transistors, depending on their size. Or you can run a monte carlo analysis if you have the corresponding mismatch set.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-25-2014 13:37 :: erikl :: Replies: 2 :: Views: 600
--- > What is sigma value ?
The sigma value (σ) corresponds to the standard deviation of a distribution (or the square root of the variance). In monte carlo simulations the σ value often
Analog Circuit Design :: 09-22-2014 15:05 :: erikl :: Replies: 3 :: Views: 1560
I want to ask you EDA-board gurus for suggestions with HSIM Co-simulation and monte-carlo simulations.
I want to run a montecarlo simulation in a relatively large transistor-level circuit (imagine a microcontroller), but the caveat is that the environment to this circuit is very complex (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-07-2014 16:16 :: tadeoman :: Replies: 0 :: Views: 674
after the monte carlo run, say I ran only 2 runs, what are the different folders names '1' and '2' . Any idea?
Analog Circuit Design :: 06-02-2014 13:34 :: dkumar :: Replies: 2 :: Views: 2647