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21 Threads found on edaboard.com: Mos Adc
We are using atmel 89c51re2 ic. We want to use the internal SPI in this microcontroller ic. We have connected adc3208 ic which also support spi inteface. We have done pin conncetions for the above setup as below, 89c51re2 adc 3208 sclk(pin 2) sclk(pin 13) (...)
i design a cap type charge sharing sar adc , it needs to be dischage when each conversion cycle. please see the pic show as below , the node vx=0 when sampling mode , and it is pull down by N3. but when the hode mode , the N3 should be disable. but , since the vx will be negative voltage , the mos N3 body diode will flow to have a leakage
I couldn't figure this out as well, but my work around was passing my clock throw a comparator build with mos, then including noise only in the comparator. I then measured the RMS jitter coming out of the comparator then increased the noise scale factor till I had a RMS jitter of 20pS which i needed for my sigma delta converter which I could then s
Hi All, I have opamp spec as follows adc=100dB,UGB=900MHz,Supply=1.2V ,Tech=0.13u Cmos I have 1.2V mos devices with vthn=vthp~0.45V Could someone help me in deciding the architecture for above specs ? thanks
could someone attach the following IEEE paper for me , thank you very much. A.Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electronics letters, Vol.32, No.12, 6th June 1996. James L. McCreary, “Matching Properties, and Voltage and Temperature Dependence of mos Capacitors,”
I designed a sample/hold amplifier for 14bit 100Ms/s adc input. In typical simulation, the sample/hold amplifier shows good performance, which has 95dB SFDR. However, in slow corner(mos slow, cap slow, 120deg temp), the sample/hold amplifier shows bad fft results with 80dB SFDR。 I checked each part of my circuit, and found the opamp is t
Q(1) the loads of preamplifier and first comparator in this paper are diode-connected mos, what is the difference between the diode-connected mos load and the resistive load in flash adc? from the simulation, the preamplifier with diode-connected mos load will have lower output common level A(1) Resistive Loaded (...)
Hi, I am designing a flash adcwith cadence software using gpdk090. To perform handcalculations i want the value of threshold voltage, k, beta etc of the mos devices (from spice models). Can anyone provide me the datasheet of the gpdk spice models.
i think injection current is the terminology used to describe gate current of a mos...
Any reference for invoiding the charge injection. Use the mos Pair or only use NOMS W/L?
A good book is "Analog mos integrated Circuits for Signal Processing" by Gabor C. Temes Hi thanks in "chapter 7 : Nonideal effects in switched capacitor circuits" there is no discussion about this effect (just clock feedthrough). Can you tell me which page? thanks
I want to use serial adc #adc0831. I got it's datasheet but in that sheet, mostly written about adc0832-8 can any body tell me the routine in assembly of AT89C51?
Suppose the Cmos switch resistor and sampling capacitor is constant and driving voltage source is ideal. And this S/H is intended for adc. Then the only error source for Cmos switch sample-hold circuit is linear settling (let's just forget about charge injection or feedthrough). As long as above conditions are true, linear settling (...)
I don't think the mos capacitance fit for sample cap. if u use MIM or Poly to poly cap. you can lookup the mismatch form that from foundry. I think if ur adc not high speed or high resolution, and you layout better, their ratio can match to 0.1%.
Resistor mismatch is depends on a AR (%.um) parameter σ(ΔR/R) = AR / SQR(W*L) So, just as mos transistors, you just have to increase area to improve matching. However, matching parameter AR is given for closely placed devices. Thus 0.001% is not feasible on integrated resistors (maybe except those trimmed by laser). 0.001% is ba
In adc, I have knew that we can use mos switch at input stage to prevent kickback noise from latched comparator to preamp stage. But in reality when using mos switch, the clock feedthrough from the mos switch is more significant than kickback noise from comparator. How about you?
avoid charge injection, you can use cmos switch and two phase clock, which Q1 Q2 and Q2', said Q2' is little more than Q2. And you can referece some paper or book about adc
S/H switch use "dummy mos" can really reduce charge injection , I ever use 1/2 size dummy mos siwtch , but simulation sitll have charge injection maybe small switch W/L reduce , and reduce parastic Cap for reduce clock feedthrough
tsmc 0.35um Process ,, It is a little hard , We have implement 80M/12bit pipeline adc , We use 0.18um process , almost mos we use .35um , but in the critical part we use 0.18um mos , Like OTA . That OTA can get more high gain . high BW
G. Temes and R. Gregorian, Analog mos Integrated Circuits for Dignal Processing, 1986.
In aditional to capacitor mismatch, I think there should be other factors affect the resolution up to 12 bits . It may cause by operational amplifier or mos mismatch.