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1000 Threads found on edaboard.com: Mos Width Length
gain (gm) goes as W/L. Up to some point, front end gain is the most significant thing you can play with for low- overdrive differential amplifier speed.
Hi everyone, I'm trying to simulate a simple electric circuit using spice with a common mos insite (i.e. ZVN4424Z - SOT89 N-CHANNEL ENHANCEMENT MODE VERTICAL Dmos FET). The supplier Zetex ( ) give as the mos spice model. The question is: I'm quite sure (see in the follow) that the model doesn't consider the actual siz
Hi, By boss tells me that to get good matching in current mirrors they should be designed where L is large. My own understanding that as long as the devices are large in area and laid out well then they will match. So my question is length important or is making the area of the mosfet large sufficient? Thanks
Hi again, I have not got any replies. Obviously somehow the quote symbol did not show up correctly. The correct sentence follows: For example now as width/length values I have (5u/1u), but what I want is: (W=5u/L=1u). I also have encountered another problem. I have added another attribute: (nfing) for the number of fingers per mos (...)
Hi, friends: We can export the CDL netlist from Cadance, like: M*** d g s b PV W=10u L=2u M=1 R*** net1 net2 NumberOfsheet $ But CDL netlist can't be simulated directly using Hspice, we must find and replace. Does there exit method to export the Hspice netlist that can be recognzied directly by Hspice simulator with
Hi ! In my experience , The width of power ring ( core ring ) is as wide as possible but there must be have no wire-width violations ! All most my projects , I usually using maximum-wire-width rule in library for power coring !
echo47 Thank you for your reply . Yes it is 12.5MHz for the peroid 80ns, it is my error. Sorry I could not provide a schematic for you. In my project, I want to use a mos campacitor connecting one input node of the comparator to attenuate the noise from the other input node. So I prefer to minimize the mos width and (...)
Delay in a gate can be simplified as the amount of time it takes to discharge the load capacitance that the gate or fet is driving. I= q/t = C*V/t t=C*V/I 1) to the first order, delay (time) is inversely proportional to drive current. So, increasing the drive current will reduce the delay. 2) Increasing the mos width will increase its d
Hi guys, Im trying to design edge coupled filter on ADS momentum. i having trouble calculating the width and spacing of the filter although i manage to calculate the odd and even impedance. i also wanted to knw which parameter will change the resonant freq of the coupled filter is it the width, length or spacing? thanks guy
Because of the (W/L) which is the width over the length factor. You are changing P mos width rite? But the Kr changes. It will change the voltage transfer characteristic of the inverter. From there only,you can see the fall time and rise time.
May i know what % of variation could be expected while a device is fabricated. eg. say i designed a Cmos device with W/L as 100um/1um. Can i expect a variation of about 10% in the fabricated device dimensions i.e. effective W/L becomes 90/0.9 OR is the % variation lesser than this. Thanks a lot in advance!! Vijay
So, one of the interview questions goes like this: How do you size Nmos and Pmos transistors to increase the threshold voltage? How ... ? TIA
Where to define the V-I characteristics of a new created device\part. e.g., I have to use mos and I created my own part using ?NEW PART? in ?USER DEFINED PROPERTIES? i added new property width, length but where I have to give the characteristic equation which defines the relation of voltage, current, W/L ratio and other parameters.
Hi guy's, I want to know how can I find the Min/Max gate width/length for specific technology ( 0.18um for example). Are they deteremined in the tech. parameters sheet??,, because I am using TSMC0.18um in my design and I have very big transistors ( 40.5um/40.5um) is that acceptable for layout?? Thanks
I just want to know that what are the effects of increasing transistor width in Cmos on the power consumption and dealy.
Has anyone ever seen a filter program called GBCL, i downloaded it a few years ago. It calculates the width, length and gaps for edge filters. This software is based on a book by matai, jones and young. Now, you can manually work through the book to get the same results but the problem lies when you have to use a nonograph to get the w/h parame
There is not any MSTEP , Microstrip or Mcross but only resistor and NPN in my schematic,but to draw/design its layout,all of that must be added. so I don't know how to start? If I add microstrips in schem then optim it, maybe it's not fit for layout;If I draw the layout first, then change/calculate it to schem to re-analysis,it's far away from my
in ads simulations,i saw that two componts are connected by microstrip,but when i simulate a circuit,i only use a wire.i want to konw,how to represent the wire with a microstrip,how to choose the width and the length of the microstrip between two componts.thanks
Visit the Ansoft's web page: Download the materials related with HFSS 9. One among them: In this tutorial see the "Tutorial 3" which describes how to build a microstrip antenna with stripline and with a
LDO give same quantity as controller want, but if controller has short current loop, then current, requested from LDO, will be large . In this case there is LDO with short current protect built in LDO. LDO never , never give current more then you request from it. As a primer imagine a bottle with water standing on the table. Water don't l
I think that somehow desing process of analog ckts is similar to that of software. The schematic is sortof seen as the code. Below I take an example of design w/ Cadence. If I design a big ckt, first I divide the whole one into a few seperate blocks. Second, I begin to work on each individual block, I use design parameter to take place of t
I browsed almost all the papers of the IEEE of the gain boosted OTA, all mostly said about the same thing, just add a Op Amp to increase Rout, like the picture attached.... The problem is how to decide the bias and the width/length of the the added Op Amp. I used the Op Amp as same as the original one(the one needed gain (...)
all, I can create symbols of my schematics no problem in cadence, but how do I create a symbol so when I query it I can change the parameters (i.e. width, length etc). I want to make my own set of library cells, inv, and, etc. Any help is greatly appreciated. Texan1
What are the general rules for derateing resistors for pulse discharges? I have a 5 watt 22ohm resistor that I'd like to use as a load for a test circuit. It's a 300 volt 80u capacitor. But fully charged the capacitor will produce an average of 1000watts (5kw peak) over a 5ms period (A little over 4 joules) This is only 4 watts over a period of 1
hi, at first, sorry about my poor English. I got a problem with CADENCE "export netlist" I have defined CDF parameters of width, length, Drain diffusion area, Source diffusion area in schematic. But only width and length can be seen in netlist. How to make every defined parameters be showed in netlist. thanks.
Hi everybody How to realize hysteresis to a latch comparator? Any good methord or any good paper are welcome Thanks very much!
for a buffer without negative feedback, the minimum output resistance is about the reciprocal of the transcondance, so if you need to get a smaller output resistance, all you need to do is to increase the transcondance(Eg:increase the current and the width-length ratio,sometimes using nmos rather pmos due to mobility). (...)
the integrated inductor usually have very low Q from 3 to 7 , max is 10 what is the Q factor did u got ? most of the RFIC designs don't depend on the inductors supplied with the kit they develop , and optimize they own L's to fit in the design khouly
Can anyone please refer a clear document regarding trace impedance in routing, and how to keep trace length and width according to impedance, how to calculate etc.. I am a beginner and i need a good document which help me to learn the trace width length etc which helps in routing
Dear All, I just want to make electric dipole as a sourse for my simulation but I couldn't find any option for dipole in the fullwave program. Somebody help me??
Dear all, I have some questions. 1.I design swithing buffer need to add between nonoverlap circuit and power mos? 2.How do I decide power mos's length. 3.If I use one regulator and LDO in parallel. Sometimes LDO is on and Sometims SW is on. If LDO is on and SW nmos is off , is it ok? Which thing do I take care? 4.LDO (...)
Keep the current flowing in opposite direction far apart !!! That's the most important thing to know.
I'm simulating a patch atenna. It simple to use the optimizer for finding the feeding point for a perfect match at the resonance frequency. But is there a way of also optimizing the antenna for maximum bandwidth? If the antenna height and dielectric is chosen, then the bandwidth is proportional to the width/length ratio. So (...)
I have given area of a rectangle and I have to select the length and width of the rectangle in such a way that the perimeter of the rectangle comes out to be maximum. Area = 4.3475
At the first All you tranasistors must be in saturation. Non-lineriaty caused with changing output resistance of transistor. This occur even transistor in saturation. Because mos has length-modulation effect. As sad surianova, you mast use local feedback to stabilize operation points. Output stage added a lot of non-lineriaty.
hello i want to design a rectangular dielectric resonator antenna at 2.65 GHz so plz any one tell me what are the value of its length,width and height at this frequency. plz help me.
How do I generate a 4th iteration or higher iteration minkowski fractal curve using a software?Once I have the coordinates I can use it in ie3d.I want to make it fast.If i do the same on ie3d manually it will consume a lot of time maybe weeks.Please help and suggest a software.
in ADS MOMENTUM! how size(of sabstrate:width,length) is determined in practical applications? thank you for your attention!
hii guys, i have designed a meander line antenna but i dont know how they calculated the width ,length and no of turns...... i want to know whether there are any standard design equations for calculating the width ,length and no of turns... check out the papers which i uploaded
hi what is "Tau" ? few times I heard some people use tau instead of milimeter or micrometer or mil for trace width or dielectric thickness specification.
I looked into the Datasheet. I thinke you have to fit your model by hand, even if you know the correct W and L. The Vth can go from 0.8 V- 1.8V ! The model uses the nominal value 1.3V. I would try to measure Vth from the real mos to see if Vth is your problem.
I am trying to simulate RF power amplifier schematics to check for the influence of gate oxide thickness and/or channel width/length on the power output, or actually any output parameter. Basically what I am trying to do is design few RF PAs where everything would be the same, even the transistor used, the only difference would be the Tox of the tr
if the circuit R netlist has value and width , length at the same time , the hspice will default adopt width , length for simulation , instead of R value. how to alter the simulation option to let it sim by R's value instead of w,l ? if the R'value , w, l , display at the same time?
hi all! can anyone help me to design a 2.45 GHz three-way power combiner on a FR4 board with substrate permitivity of 4.7 and thickness 1.6 mm, loss tangent 0.0025, copper height is 0.04 mm. impedance is 50-ohm. I only have Ansoft and CST for simulations. i'm kinda new to this but i've already done some research and found out that's its very
Hi, I created ring oscillator simulation in Cadence Virtuoso . the ring is made of : INVERTER >>INVERTER >>NAND3>>NOR>>INVERTER I pull one of the NOR's gate input to gnd , and 2 of the NAND inputs to vdd so the gates will behave as inverters . I have some very weird problem with my design , I get the fastest oscillator when I use minimu
54926 Hi i am trying to design the differential ring oscillator at 3 GHz, pic is attached. So far what i have been able to do is to make it oscillate when the simulation time is 20nsecs, but whenever i increase simulation time the oscillator starts giving dc! The other problem is that i have not been able to find widths fo
Hi ,all since i want to transfer our design(schematic) from one fountry to another(both are 0.13um process,but obvious different pdk and models). if done by hand , it's a big job. someone told me use lib manager-->rename reference library. it works , but many parameters transfer worng(eg. width,length,fingers). so it seems need script
Hello EDA fellows, I would like to ask your advises about any buffer architecture that can drive/provide clock for a very large capacitor (1uF).I tried to use taper buffer but it's extremely big (the mos width reaches 20,000 already)... Thank you.
Good day everyone, if i have to match 2 transistors of a current mirror with W/L 9.6um/1um and 7.2um/1um .Now if i fold these transistors for interdigitation then do i need that all interdigitated transistors have equal widths or just symmetry is required. i.e ABBA | ABBA is required. but can A have width of 1.8um and B have width of (...)
Hello! I am working on a Third Order equiripple Low pass filter design suitable for Microstrip ( Distributed structure). The cut-off frequency varies from 400-800 MHz and the range of capacitnace values varies from 1-7 pF for the following setup :: SMA connectors at board edge to filter ports via 50 Ohm Microstrip, unspecified length. T