18 Threads found on edaboard.com: Multiplier And Shift And Add
below is a 8-bit shift and add multiplier code in vhdl.
u can take it as reference and design a 16-bit multiplier.
-- The multiplier (...)
ASIC Design Methodologies and Tools (Digital) :: 14.04.2007 00:52 :: kib :: Replies: 2 :: Views: 1928
You Are Also There:
Nobody Has Given A Satisfactory Answer For You.
May I Can Help?
First Of All I Need To See The
ASIC Design Methodologies and Tools (Digital) :: 18.07.2012 02:48 :: MrCarlos :: Replies: 3 :: Views: 1559
If any one of your operand is a constant one then there is an easy way like this:
Say if one of your multiplier operand is 11, then 11 can be represents in the power of 2 as 11 = 8 + 2 + 1 = 2^3 + 2^1 + 2^0
and if A is the other (...)
ASIC Design Methodologies and Tools (Digital) :: 15.07.2013 00:33 :: imbichie :: Replies: 5 :: Views: 1138
Well the concept of low power can be explained by factors such as
Switching, shortcircuit, leakage and static --
Keeping these factors in mind, i propose to design a VLIW processor which wud be under the Globally Asynchronous and Locally Synchronous technology(GALS) ,
First i have to design an ALU (...)
ASIC Design Methodologies and Tools (Digital) :: 29.11.2004 22:18 :: arunragavan :: Replies: 14 :: Views: 1906
A multiplier performs accurate arithmetic, Y = A * B.
A mixer simply combines two signals non-linearly, usually with the goal of creating new frequency products or amplitude modulation. A mixer can be as simple as two resistors and a diode. A multiplier is a mixer too, but it's an expensive solution if all you need are (...)
Analog Circuit Design :: 29.04.2005 22:35 :: echo47 :: Replies: 4 :: Views: 781
is there any body who khnow the circuit of below?:
i want this for logic circuits lab :
i want to make a multiplier with "shift & sum alghoritm",for example with shift register and etc...,if any body khnows,how can i make this , tell me immediately,plz
i will be thankful
Analog Circuit Design :: 25.06.2009 15:02 :: shazdek0ch0l0 :: Replies: 3 :: Views: 1693
Does anyone know how to write a 4x4 multiplier in vhdl? I would like to implement the code on a Spartan 3E board. Any help would be appreciated. Thank you.
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.03.2010 17:44 :: niten :: Replies: 3 :: Views: 2293
Are you using the graphical editor?
then use the LPM library from the mega wizard for multiplier and divider and make all the data paths the same length,
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.09.2010 05:52 :: TrickyDicky :: Replies: 6 :: Views: 1821
anyone want to help me with this? I'm having a bit of trouble with the control and resultant register block. Here is the code I have so far:
-- M x Q
--C A Q M
--bit(0) of Q => if 1 add and shift elsif 0 shift, A=A+M
--eight cycles register is 16 bits
--store M in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.04.2012 13:05 :: levez :: Replies: 2 :: Views: 360
Why is not it used in RTL for multiplication?
Generally speaking, it is used. Thus I don't exactly understand the question.
There may be reasons to instantiate explicite multiplier blocks instead of infering it from a "*" operator. It depends.
ASIC Design Methodologies and Tools (Digital) :: 08.05.2012 02:06 :: FvM :: Replies: 17 :: Views: 848
I am trying to implement a sequential shift and add 4bit multiplier as shown in the image.
I am having a separate module for the 4 bit ripple carry adder. I have tested the adder module and it works fine.
now i need to trigger (...)
ASIC Design Methodologies and Tools (Digital) :: 29.04.2013 05:29 :: hmms :: Replies: 0 :: Views: 258
Gate count is not indipendent from your target frequency (in some particular technology like .13um TSMC LP, not in general), your wire-load models, input/output delays.
For memory, you could look into Memory Compiler you use (if it supports 2 read and 1 write ports!).
All those blocks you mention are extremelly small (even multiplier) for (...)
ASIC Design Methodologies and Tools (Digital) :: 26.10.2004 00:31 :: andromeda :: Replies: 2 :: Views: 1080
what do you do with multiplier? this real question.
in the communication for multiply the carrierand message the MC1496 is very low cost. but dynamic range is small.
for high dynamic range the papular multiplier is AD633. that is low cost and can xproduce (XY+Z)/10
if ypu can specify (...)
ASIC Design Methodologies and Tools (Digital) :: 06.06.2005 12:43 :: carrier :: Replies: 6 :: Views: 930
I m a student of Mtech. I want 2 give seminar on multipliers .can anybody help me out regarding the study material of multipliers or about websites where i can find out relavant information about multipliers .
ASIC Design Methodologies and Tools (Digital) :: 19.10.2005 01:52 :: jayna :: Replies: 1 :: Views: 686
I have been trying to design a 4 bit ALU. I have designed it for some arithmetic and logical operations. Now I want to add the multiplication operation with my design. For that I am trying to design 4*4 multiplier. But the problem is it's giving me 7 outputs and the rest (...)
Electronic Elementary Questions :: 04.05.2006 11:19 :: amira :: Replies: 1 :: Views: 1429
Recently I was trying to write a Verilog Code for Multiplication by 3.
Condition-My Input is variable-Unsigned or Signed
My multiplier is fixed-3
So if i have -20 as input in binary my output should by -60.
and 20 as input my output should be +60.
I want to declare only one output that is product (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.11.2010 15:11 :: er.twi.fb :: Replies: 4 :: Views: 2028
hi everyone a student from Vietnam. i have a project and have to submit it to my teacher on the 20th of May . Can you guys here help me with this project. I would really appriciate your help^^^
the project is: design and test 4X4 bit unsigned multiplier using right shift (...)
ASIC Design Methodologies and Tools (Digital) :: 13.05.2011 21:29 :: Cucanh :: Replies: 2 :: Views: 333
In the past, I taught college labs for this problem. Some people will just understand how to do this, and others really never caught on. If you ignore the book's advice, you can actually get better results in less time. (it might have been the instructor's advice, I really only used the book for the specifications of the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.01.2011 01:14 :: permute :: Replies: 3 :: Views: 1030