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61 Threads found on edaboard.com: Multiplier And Verilog
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135472 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b);
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135474 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b); and(w,a,b
just out of curiosity, how do you guys do math in FPGA? Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add. As to other operations such as cordic...IPcore is my first choice... Multiplication I almost always do as a * b. It makes for
Hi, I am using Primetime to perform Voltage scaling, then i need to get timing and power change. When I use set_voltage, i can see changes in power, timing remains the same. I have a combinational multiplier design. No clocks in verilog code. I am trying to use set_rail_voltage, but i dont know clear way. I am trying to use the following (...)
Dear all I need to instantiate an Altera float-point matrix multiplier megafunction in my design, and plan to implement it with a one-hot state machine. The problem is that the filed generated by the quartus megafunction wizard have errors, such as in the .v (I use verilog) file there is Error (272006): MGL_INTERNAL_ERROR: Port (...)
i have this code and wanna to update it to multiply 4 by 3 bits any help :) thanx in advance // // // // // This file is part of the Amber project // // //
As vGootimes said the FPGA equivalent to the huge, un-maintainable mess of structural verilog, would be this: module multiplier ( input a, input b, output p ); assign p = a * b; endmodule But if you want high performance you'll probably want to add a clock and include some pipeline registe
Hey all, I was wondering if you could help me with my homework. I need to implement a 4-bit multiplier at the gate-level in verilog using and gates and adders I've drawn the layout, but I'm having trouble translating it to verilog. When I instantiate an and-gate, how do I extract (...)
can anyone help me build a 5x5 bit signed multiplier.. im a beginner and im trying to program it in altera Quartus II
I am trying to implement a floating point multiplier on spartan3E using verilog. and I want to display the result in LCD(spartan3E 16x2 LCD). How can we convert floating point to integer format in verilog? How can we display the floating point number in LCD? and also I wand to give input (...)
i need code and block diagram for implementation of 16bit multiplication using carry save adder urgently. Can someone please help me out.
I am designing (256x256)-bit multiplier using DSP blocks available on Xilinx FPGAs. I split operands into several chunks of 64-bits, using Karatsuba technique 256-bit multiplier can be constructed using 3, 128-bit multipliers each of which are further realized by 3, 64-bit multipliers. i have constructed (...)
how to calculate the total delay when no. of clocks are used in verilog code and help me out to write the code for 8 bit wallace tree multiplier in verilog
I am trying to build a ripple carry adder using a hierarchical verilog structure description. What I have is not working right... out puts are all messed up. My logic is messed up somewhere but not sure where. I grabbed the test bench from a 8 bit multiplier to use for the RCA and so I know I am overlooking something basic... any help (...)
Hi Arpkum, If any one of your operand is a constant one then there is an easy way like this: Say if one of your multiplier operand is 11, then 11 can be represents in the power of 2 as 11 = 8 + 2 + 1 = 2^3 + 2^1 + 2^0 and if A is the other operand Then A*11 = A*8 + A*2 + A = A*(2^3) + A*(2^1) + (...)
90236 I am trying to implement a sequential shift and add 4bit multiplier as shown in the image. I am having a separate module for the 4 bit ripple carry adder. I have tested the adder module and it works fine. now i need to trigger it from the multiplier module. so that it triggers on the 'add' signal. please help
Hello. I am working with QuartusII. My project is Serial Mutrix multiplier and I use verilog, but when i compile my project the following error appears.Can you help me? Internal Error: Sub-system: GDFX, File: /quartus/synth/gdfx/gdfx_slice.cpp, Line: 736 (*sgate_nodes) != NULL && (*sgate_oterm_coll) != NULL Quartus II Vers
i need to design a multiplier unit.. design idea: only binary inputs representation signed representation..can provide a sign bit input.. ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program
Hi, my code currently looks like this. Is there any way my code can accept non integer numbers (A=3.05). I read that my output has to be a reg type so how can we represent multiplication, division or addition using non integers? For ex. 3.05 + 1.07 or 1.06*5.01. If the output must be of type reg. I read online that there are very complicate
hi can u send verilog or vhdl coding of 4x4 bit braun multiplier and 4x4 baugh wooley multiplier
To my understanding: 1): If you want to synthesis that multiplier, you just write mul = a * b; will be ok. Then synthesis tool will synthesis this code to logic gates. 2): If you want to design a multiplier (design a multiplier architecture) with simple logic functions, such as add, OR, and, you may need (...)
I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I (...)
hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." (...)
i'm sorry, but i'm looking for 'structural' design type of 8*8bit multiplier So why did you ask for a verilog code? ... such as 8*8bit array multiplier... and why didn't you try G00GLE? Also look for G00GLE images! [QU
guys need some help regarding sequential multiplier
Is it possible to change the clock frequency or increase it based on some clock multiplier in the TB-model for different modes of operation ?
i have designed a high speed, low power multiplier. can i use it in decimation filter to lower the filter's power consumption and increase its performance?? if so can u plz suggest how to proceed with the same!!! thanks in advance
First, is it multiplication ? ur module name says its division ! if it is multiplication, y r u making so complicated ? keep it simple.... like the one below for(i=0;i<multiplier;i++){ temp_reg = temp_reg + multiplicand; }
I need a verilog code for a 128x32 bit montgomery multiplier for AES and public key cryptography applications pls.
Hi there, Recently I was trying to write a verilog Code for Multiplication by 3. Condition-My Input is variable-Unsigned or Signed My multiplier is fixed-3 So if i have -20 as input in binary my output should by -60. and 20 as input my output should be +60. I want to declare only one output that is product (...)
Hello, I have a VHDL multiplier design that I am trying to synthesize with Design Compiler. The output is correct and verified through simulation, but it is being broken up into different modules, with some of the modules making calls to the other modules. I would like to generate the verilog gate-level netlist with all of the code in (...)
Dear Sirs, I am trying to find out dynamic power consumed by my multiplier. So i want to generate a vcd file. I am using the following codes in my verilog test fixture initial begin $dumpfile("invchn26.vcd"); // Change filename as appropriate. $dumpvars(0, generator); $dumpall; $dumpflush; end But vcd file remains empty. Sometimes
does anyone have verilog code for booth radix-2 multiplier in verilog.i designed it,but it isn't fast and it have a lot of gates more than efficient.i khnow that for a faster booth multiplier i nedd to add CSA and compressor to it(or other adders like wallace tree),so does anyone help me (...)
hi thanks for ur reply, actually this is the help i'm expecting from ur people .. i have downloaded the pipelined 8*8 multiplier code from net, but while i simultaing that ,im not able to get simultaed result, and also i didnt know how to force the if u have any idea ,how to force the input for an 8*8 pipelined multiplier kindly expl
hi , sir please sent me to my mail ,i want: flow chart, algorithm, and code in verilog
Hi All, I am in need of a verilog code for multiplier or adder with latch function. (Neglect bit number and type.) If any one of you has the code, please upload it.
Hi, there. Have you guys ever developed the frequency multiplier for PLL using verilog? Input is going to be FREF, then it should be multiplied by M. Although we can see a divider easily, the multiplier cannot... Anybody is there to help me for this? Thanks in advance.
to build qpsk use divide and conquer divide the system into: 1-serial to parallel converter 2-mapper: map every 2 bits to corresponding i,q 3- sin,cos oscillator 4- multiplier 5- adder not that hard
Hi All, I am in need of a verilog code for a 32-bit multiplier. i have searched in but did not find the verilog code for 32 bit multiplier. If any one of you has the code, please upload it. Kind Regards
Use calculator and multiply the two signals if you are going to compare it with any other multiplier circuit or so. if not and you are going to use it as a part of circuit design then use verilog/VHDL - AMS models if you can make one.
HI, How to model a frequency divider or multiplier with verilog-A? I have an input clk signal and I want to write a verilog-A model that can output different clock frequency based on the input clk frequency and the multiplier/divider value that user input. I have been trying for (...)
Hello Friends, I need to design a 16 bit multiplier in verilog using wallace tree algorithm. Can anyone clearly explain me the multiplication using the algorithm. take 4 or 8 bit example. Please help me. I need to design it very urgently Thanks and Regards Deepak
hi i have simulated and then synthesised a verilog code for both 8-bit & 16-bit array multiplier using carry sav adders on Xilinx.8.2. the results i got are as follows. result for 16- bit array multiplication Minimum period: 19.961ns (Maximum Frequency: 50.098MHz) Minimum input arrival time before clock: 2.443ns Maximum output (...)
hi i have simulated and then synthesised a verilog code for both 8-bit & 16-bit array multiplier using carry sav adders on Xilinx.8.2. the results i got are as follows. result for 16- bit array multiplication Minimum period: 19.961ns (Maximum Frequency: 50.098MHz) Minimum input arrival time before clock: 2.443ns Maximum output (...)
An ordinary multiplier has two inputs and one output: Y = A * B Maybe you mean multiplexer instead of multiplier?
I will be using VHDL\verilog Code to simulate the function the datapath proposed in this paper "A New hardware Realization of Digital Filter" By ABRAHAM PELED and BEDE LIU IEEE Transaction on Acoustics,Speech and Signal Processing,DEC 1974 Here I attached the diagram of the datapath My question is 1)Is it appropriate to use (...)
Anyone knows about Booth algorithm? It's great help to hardware multiplier, here I got an example which can be your reference. Also, can somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate". Thanks! ------------------------------------- -- (...)
any has the code for Booth multiplier in verilog....or any other related material plz help me.................
Hello good-day, I am in real need of some help. Right now i'm at college programming using verilog. I need some assistance in programming using verilog, an 8bit * 8bit pipelined multiplier. In the design, I am required to use an array of CSA (carry save adders) and one CPA to find the final product. Can I have some (...)