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62 Threads found on edaboard.com: Multiplier Code Verilog
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135472 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b);
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135474 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b); and(w,a,b
just out of curiosity, how do you guys do math in FPGA? Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add. As to other operations such as cordic...IPcore is my first choice... Multiplication I almost always do as a * b. It makes for
Hi, I am using Primetime to perform Voltage scaling, then i need to get timing and power change. When I use set_voltage, i can see changes in power, timing remains the same. I have a combinational multiplier design. No clocks in verilog code. I am trying to use set_rail_voltage, but i dont know clear way. I am trying to use the following (...)
i have this code and wanna to update it to multiply 4 by 3 bits any help :) thanx in advance // // // // // This file is part of the Amber project // // //
I came across a verilog example of improving power consumption in a multiplier. The original code is reg Enable; reg A, B, DataOut, MultOut, AddOut; wire A, B; always@(posedge clock) if (Enable == 1) DataOut <= MultOut; else DataOut <= AddOut; assign MultOut = A * B; assign AddOut = A + B; The assumption
As vGootimes said the FPGA equivalent to the huge, un-maintainable mess of structural verilog, would be this: module multiplier ( input a, input b, output p ); assign p = a * b; endmodule But if you want high performance you'll probably want to add a clock and include some pipeline registe
please share the code for fft computation. We have written the code for 8 bit vedic multiplier(urdhva tiryakbyham).
Unfortunate the floating point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL. For the same reason, wr
i need code and block diagram for implementation of 16bit multiplication using carry save adder urgently. Can someone please help me out.
Do these operations in the OP state. shift one of the operands and add the other one to the product (don't shift the product).
Hi, what trouble u have to written this array multipliers, having a verilog code or concept, send your written-ed verilog code. Regards, Rajavel
how to calculate the total delay when no. of clocks are used in verilog code and help me out to write the code for 8 bit wallace tree multiplier in verilog
Are you asking about a parameterizable module, where the bit length of some inputs is defined by a parameter, or do you mean that the length is variable at runtime? A generate construct can only work for the first case. generate if (SIZEPAR == 8) // instantiate 8x8 multiplier else // instantiate 4x4 mutiplier endgenerate
The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time. The code can probably run in simulation if z_temp is cleared before the loop. Adding the multiplicator n times is also the worst way to make a multipli
please send me the verilog code for booth multiplier
I want a verilog code for computation sharing multiplier
Can any body help me in doing verilog code for generic multiplier ?
Hi, my code currently looks like this. Is there any way my code can accept non integer numbers (A=3.05). I read that my output has to be a reg type so how can we represent multiplication, division or addition using non integers? For ex. 3.05 + 1.07 or 1.06*5.01. If the output must be of type reg. I read online that there are very complicate
i really need to know if is possible to multiply a clock frequency in verilog or maybe someone can explain me how to delay a clock signal with a quarter of a period
To my understanding: 1): If you want to synthesis that multiplier, you just write mul = a * b; will be ok. Then synthesis tool will synthesis this code to logic gates. 2): If you want to design a multiplier (design a multiplier architecture) with simple logic functions, such as add, OR, AND, you may need rearch the (...)
hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t
Yes, there are more errors module mult8(p,x,y); output p; input x,y; reg p; reg a; integer i; always @(x , y) begin a=x; p=0; // needs to zeroed for(i=0;i<8;i=i+1) begin if(y) p=p+a; // must be a blocking assignment a=a<<1; end end endmodule P.S.: A brief co
try to use structural verilog... make code for multiplier first then connect all like this,,, : module multiplier_fn(inp1,inp2,product); input inp1,inp2; output product; assign product = inp1 * inp2; endmodule module activation_fn_2 (inp1,inp2,inp3,cin_low,cout1,out); input inp1; input inp2;
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please (...)
i'm sorry, but i'm looking for 'structural' design type of 8*8bit multiplier So why did you ask for a verilog code? ... such as 8*8bit array multiplier... And why didn't you try G00GLE? Also look for G00GLE images! [QU
Hi, I am new to verilog. I need to write verilog code for modified booth multiplier. How to write the code for padding 1 zero to LSB of a multiplier, let's say 4bits input? Thanks. Rgds, KK
does anyone have modified booth multiplier code in verilog or vhdl?
Google is your friend. you could find an example of 4x4 braun multiplier on this document: 2.4.1 Braun multiplier :-
Hi, I am presently stuck trying to figure out if I can even do this in verilog. What I have is a recursive instantiation of a module (gf_mult_pipe).. a variable pipelined Karatsuba multiplier. As seen in the code below, I am trying to figure out a way that the value for "PIPE_STAGES" can change depending on what it was previously. For (...)
guys need some help regarding sequential multiplier
Hi, Its a good start but there is a lot to improve on this. Please check the following. Its the best that i have seen so far. It generates verilog code for Galois Field multiplier, Hamming codes etc etc
With twos compliment, there is no need to worry about whether values are positive or negative. All you need to do is sign extend both inputs. You either need to instantiate an onboard multiplier or N adders, where N is the number of bits at input. lets take an example, -3 x 5 (1101 x 0101) 1 1 0 1 x 0 1 0 1
First, is it multiplication ? ur module name says its division ! if it is multiplication, y r u making so complicated ? keep it simple.... like the one below for(i=0;i<multiplier;i++){ temp_reg = temp_reg + multiplicand; }
I need a verilog code for a 128x32 bit montgomery multiplier for AES and public key cryptography applications pls.
Hi there, Recently I was trying to write a verilog code for Multiplication by 3. Condition-My Input is variable-Unsigned or Signed My multiplier is fixed-3 So if i have -20 as input in binary my output should by -60. and 20 as input my output should be +60. I want to declare only one output that is product and (...)
i need verilog code for the twiddle factor ROM multiplier for radix 2 butterfly module 128 point fft. please help me. pls pls ........... its very urgent
Dear Sir, I am simulating a multiplier in xilinx ise. I have written structural verilog code . Now i want to transfer the schematic to cadence. May I transfer it directly? I dont want to build schematic in cadence from scrap. Pls explain in detail since i am a novice. Secondly, i want to find dynamic power using xpower. But it shows (...)
does anyone have verilog code for booth radix-2 multiplier in verilog.i designed it,but it isn't fast and it have a lot of gates more than efficient.i khnow that for a faster booth multiplier i nedd to add CSA and compressor to it(or other adders like wallace tree),so does anyone help me with giving a fast (...)
hi thanks for ur reply, actually this is the help i'm expecting from ur people .. i have downloaded the pipelined 8*8 multiplier code from net, but while i simultaing that ,im not able to get simultaed result, and also i didnt know how to force the if u have any idea ,how to force the input for an 8*8 pipelined multiplier kindly expl
hi , sir please sent me to my mail ,i want: flow chart, algorithm, and code in verilog
Hi All, I am in need of a verilog code for multiplier or adder with latch function. (Neglect bit number and type.) If any one of you has the code, please upload it.
to build qpsk use divide and conquer divide the system into: 1-serial to parallel converter 2-mapper: map every 2 bits to corresponding i,q 3- sin,cos oscillator 4- multiplier 5- adder not that hard
hi.......... i need a verilog code 4 ....... 4 a 16 multiplier of signed numbers by implementing the technique of correction vector(use only one 16bit carry look ahead adder) plz help me out..
Hi All, I am in need of a verilog code for a 32-bit multiplier. i have searched in but did not find the verilog code for 32 bit multiplier. If any one of you has the code, please upload it. Kind Regards
guyz do u have any idea how can we write a test bench to test the 8*8 multiplier with all the possible cases without writing them manually... thanks,
hi i have simulated and then synthesised a verilog code for both 8-bit & 16-bit array multiplier using carry sav adders on Xilinx.8.2. the results i got are as follows. result for 16- bit array multiplication Minimum period: 19.961ns (Maximum Frequency: 50.098MHz) Minimum input arrival time before clock: 2.443ns Maximum output (...)
hi i have simulated and then synthesised a verilog code for both 8-bit & 16-bit array multiplier using carry sav adders on Xilinx.8.2. the results i got are as follows. result for 16- bit array multiplication Minimum period: 19.961ns (Maximum Frequency: 50.098MHz) Minimum input arrival time before clock: 2.443ns Maximum output (...)
Hello All, can i get a verilog code for 24*24 wallace tree multiplier?? i need this for my project. send me on pragya.laad@gmail.com thanks
I will be using VHDL\verilog code to simulate the function the datapath proposed in this paper "A New hardware Realization of Digital Filter" By ABRAHAM PELED and BEDE LIU IEEE Transaction on Acoustics,Speech and Signal Processing,DEC 1974 Here I attached the diagram of the datapath My question is 1)Is it appropriate to use two 2-bi