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Multiplier Design Using Vhdl

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8 Threads found on Multiplier Design Using Vhdl
Hello Can somebody help me with the vhdl code in the attachment. When I elaborate it on design vision, I get the error below. Does anyone know why so and can help out? Thanks 105323 library ieee; use ieee.std_logic_1164.all; entity mult is generic ( N : natural :=56 ); port (
yes ofc its possible. Fir filter needs only DFF , adder and multiplier. In FPGA transponded fir architecture is widely used. Basically u can design wanted fir in matlab, export coefficient from it, change it to fixed values , and you can start vhdl implementation
Hi, Does anyone know how to write a 4x4 multiplier in vhdl? I would like to implement the code on a MAX-PLUS II (ALTERA). Any help would be appreciated. Thank you.
Posting your code so others can see before I answer. Your code is as follows: --create of multiplier 4bit X 3bit library ieee; use ieee.std_logic_1164.all; --declaratio of the multiplier entity entity multiplier4X3 is port ( A : in std_logic_vector (3 downto 0); B : in std_logic_vector (2 downto 0); P : out (...)
hi everybody, actually i want to know that i m using 6 multipliers in my design..but i want to use the same multiplier to do the calculation how i cn do it...ny1 has ny idea?? thn tell me
you can use the xilinx coregen to produce a multiplier core.
why do u use an FSM ? what kind of multiplier do u want to do signed or unsigned? what kind of FPGA you r using?
How to design a floating point multiplier?