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102 Threads found on edaboard.com: Multiplier Simulation
I am designing a 2 quadrant multiplier and 4 quadrant multiplier (simulation purpose)based on translinear operation..could someone help me out with what is the difference between a 2 and 4 quadrant multiplier and how to apply it on translinear circuits?
Hi all, I want to design a 1GHz×5 SRD frequency multiplier use Agilent ADS. For a fresh guy, I don't know which simulation should I use (Harmonic Balance or Transient?) and which diode is better for my design? (ma44769 or HSMP3822? Somebody suggest 3822 for it's cheaper) What's more, the diode model is needed. Someone gave an address in this f
i need floating point multiplier VHDL code. if possible for 8,16 and 32 bit.
I do not know what is useable in Hspice but in most spice you be limited to a nonlinear cap. So the control voltage is the cap voltage themselve. I think you have to use an analog behaviour with an integration function and a multiplier or a function for the integration time constant.
Hello all, I am new to RF design and I am in need of some help. VSWR helped me do an amplifier design in Genesys but what I what to do now is make a multiplier. The overview is: Osc running at 25mhz > buffered > Filter/match to 50mhz harmonic > Buffer x2. I managed to do the amplifier opt/simulation with the help of VSWR, but I am unclea
I am trying to simulate a Phase Locked Loop in spice. I have created all the nodes and placed all the transistor, resister, etc. into the simulator. I am using the same setup as what is found on the spec sheet of the LM565 (pg 7 - top). I also don't have the multiplier in the cct. So pin 4 and 5 are shorted together, just to see if it works. Any
Dear all, I have a model. The Model is shown in the following link below. It has an 1) 8-bit Adder 2) a Verilog-A Module 3) Some VPWLF Sources which take "files" as inputs. Some facts: 1) I have to simulate it for 8, 12 and 16 bit adders.
I have designed a multiplier (Frequency Doubler),How will i Simulate it ?I am a beginer So Please answer in detail.
You still need the book "Computer-Aided Design of Step Recovery Diode Frequency multipliers" ?
Well, a mixer and multiplier are of same type of architecture. The function realized by a multiplier and the mixer are the same. So, you must be using Spectre for simulation which is fine. Usually people use single quadrant gilbert cell type.
Dear all I want to use(m) multiplier of bjt to optimise our design flow. but netlist file of schematic don't include m(only have area item) for MOSFET is ok, who can tell me how to set it. Thanks, rehty
Hi, Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz? Thanks
Ofcourse, the phase noise will be different at the Oscillator output and the multiplier output (due to change in frequency) and the difference depends on the Multiplication factor you are using. Ideally, if your multiplying by 2, the Phase Noise after the multiplier should be 6 dB higher than the phase noise at the output of oscillator. You
The simulation is no relation with process,because you have already known the substrate PNP can be done in the CMOS process.marth the is ok!
do anyone have sample of the ADS simulated frequency multiplier file? I would like to study some method on how to draw a frequency doubler schematic on the ADS.
Can anyone show me how to setup the simulation in AWR for a BJT frequency multiplier? I am using an Active biasing network also. Thank you, ks
hi i m designing 4 quadrent analog multiplier. there r four ip terminal in my strecture. i m giving V1+v1, V1-v1, V2+v2, V2-v2, signal at the input terninals, where V is D.C. bias and v is analog signal. i m gettin correct out put.but i dont know how can i do a.c. analisis of the circuit. i mean apply same ac signal at all the terminal with some
In spice: Scaling is controlled by the element parameters AREA, AREAB, AREAC, and M. The AREA parameter, the normalized emitter area, divides all resistors and multiplies all currents and capacitors. AREAB and AREAC scale the size of the base area and collector area. Either AREAB or AREAC is used for scaling, depending on whether vertical or lat
This paper is implemented using a W/L of 10/30 and now we are trying to implement it using 0.5 um AMI technology. What least value we can assign to W/L..? Please help...
I am going to design a W-band frequency tripler using the package ADS, in order to get better efficiency, the source impedance should conjugate match the input impedance of varactor diode, and the load impedance shoule conjugate match the output impedance of varactor diode. But I dont't know how to conduct the conjugate match. When I optimized the
Hi. I generated 1 sine wave (24bit output). In order to control the amplitude, the output multiply with a ratio(fixed point multiplier). for fix point multiplication, verilog declaration sin //zero pad ratio result_mult Asin <= result After the simulation, i realised that the THD+N is 74(-80db to
Hello, Yes, pspice is suitable for timing simulation as it has a transient simulation option where you get results versus time. It solves the time domain equations that belongs to your circuit components. For your special case, if you can convert what you want to a combination of circuit components and equations, you can do it. Pspice also e
hi i have written a code to run the multiplier MULT18X18 placed in the libraries of virtex 2. When i simulate the multiplier in modelsim i dont the output. there is always an unknown value shown at the output. i have generated a 1 us clock in the test bench. when synthsized there is a warning that appears at that time "The block MULT18x18 is a
What multiplier topology did you use? Could you upload an image of your circuit? Could you also upload your simulation results?
Hi, Currently i am using Proteus 7.4SP3 to simulate the AD633 multiplier. The two input is a trend of pulses and i want to get the output. The problem is that it occur 2 warnings which is then stopped my simulation. 1. DELMIN increased to 1.11022e-016 due to lack of time precision 2. TRAN: Timestep too small; timestep = 0: tr
hi guys i want to design a multiplier with the function of VOUT=K*(Vcomp-2)*Vin,in which Vcomp and Vin are two terminals of the multiplier. could anyone help me with the simulation of K when Vcomp equals to 3 and Vin equals to 1? thx
thanks for your reply,but i have initialized the registers,and its just a multiplier,it does not have multiple drivers Is it timing simulation? any violations?
hello friends i have to design gilbert multiplier ckt using mos and cmos structure. plz tell me hw will we design cascading of this ckt in spice code mixedmode simulation.and dc simulation i am doing work on silvaco plz tell me solution of this problem.
Hi, i am trying to implement a Booth multiplier in VHDL using ISE Webpack. I use a Nexys 2 500 board. This is my first project using VHDL (and FPGA in general) so there are some issues that i still do not understand. First, i completed the project and simulated it. It worked and all went fine. Then i tried to generate the programming file to mou
Hi , can you tell me why im getting UUUUUUUU for first value of product...and it seems like all the values of product are shifted right..... is it something to do with the clock? ive attached to testbench coding and simulation. THanks! :D
I want to make a frequency multiplier (60 Hz input frequency, output frequency of 120 Hz) using an FPGA (Spartan 3E). Can anyone help me with an example of whether or not you can do this. I already check that can be done with a DPLL but it is very difficult to implement.
The multiplier implements y = x*y and you set x or y to zero, what do you expect? If AC analysis should make sense at all, you have to set the other input to a constant DC level.
Hii all, I'm Designing a CMOS Four Quadrant Miltiplier using bias feedback techniques, the schematic for which is attached. I'm using Tanner for simulation. Also, i'm following 0.5 microns technology. The specifications for the transistors are as follow: * SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 19, 2011 at 13:4
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please help m
hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t
I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I am not able to view the correct (...)
Hai I am presently designing tree multiplier using spice.i want to analyze the power of the circuit can anyone help me to provide some test setup or how to analyze the power of the circuit using spice.
Hello everybody. I am experiencing problem in hardware co-simulation in spartan 3e board. I am designing a system that requires two consecutive multipliers. for single multiplier the system works fine. however, when both multipliers are there, during generation of JTAG block, towards the end of XFLOW it shows an error, (...)
Hi all; Please I need Good simulation program to test hardware implementation for QPSK modulator and demodulator ,,,,,,,, I used Circuitmaker and it gives errors ??!!! ,,,,,,,,,, and multisim does not have MC1496 as all Suggestions around the world worked as multiplier ???? Thank you for any help Rawan Ayyoub
hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; us
Thinking would help, there's a hierarchy of both parameters. You'll decide first about driver current and then about Vbe circuit dimensioning. I am a novice here mate. I really need a worked example to get my bearings so to speak. I have since found this web site containing a specific example: www.jopdesign.
What is your used a technique for designed rectifier ? u mean the rectifier type..? it is villard voltage multiplier. i copy the circuit directly from a paper but didnot get at least the approximate value for the output
That would prevent a latch from forming, but it does put a mux on the multiplier output which may be unnecessary. I dont understand quite why you need to "start" and "stop" the multiplier. Your design appears to just multiply two numbers. You could quite easily see these values on a simulation. You know when data is valid as the (...)
Hi I was trying to figure out this circuit but could not figure out its operation. I had done a simple simulation, it seemed to work as per intention, i.e. a DC voltage doubler/multiplier?.. Can somebody help me understand how it works and its circuit tradeoffs. BTW - this is not the typical flying capacitor/switching diodes circuit. its only
hi all, I was thinking of designing a 32 bit alu with vhdl.. I have coded with functionalites add,sub,and,or,etc....(no multiplication and divsion).. My doubt is i just wrote case (selectinput) when 001-> c<- a and b; likewise.. is it this much easy to design an alu.. or I am doing something wrong .. pleas advise.. also How would
hello, I am trying to do power estimation on a fairly complex design using Synopsys Power Compiler. So far I only set switching activities by hand. If I, e.g., set the switching activities for the inputs of a multiplier, will the power compiler estimate correct switching avtivities for all internal nets of the multiplier? If yes, how complex can
I have read some information about LUT in FPGA, but I wonder that How to use LUT in Verilog program for Altera chip. Anybody can load a simple program use LUT by verilog for me and compare the perfomance with the program without using LUT ? I am confusing about LUT definition and can not make it clearly. In addition, I try to design a fast
This is code to implement FIR by Verilog for FPGA. I have simulated it by Quartus 4.0 and find that the result is not corrected in the first cycle but corrected in the second cycle. I can not explain what reason ? I attach my simulation file and mark the error for two cycles . Anybody can help me ? //************************************
I assume the Xilinx tools will be marginally better, but that doesn't mean the Lattice tools are bad. They use Leonardo (migrating to PrecisionRTL) and Synplicity for synthesis, and Modelsim for simulation. At the back and the floorplanner and P&R is probably similar as Xilinx's. With regards to the hardware, I assume it is debatable wether EC/ECP
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