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# Multiplier Simulation

102 Threads found on edaboard.com: Multiplier Simulation

I am designing a 2 quadrant multiplier and 4 quadrant multiplier (simulation purpose)based on translinear operation..could someone help me out with what is the difference between a 2 and 4 quadrant multiplier and how to apply it on translinear circuits?

## SRD frequency multiplier simulation use ADS

Hi all, I want to design a 1GHz×5 SRD frequency multiplier use Agilent ADS. For a fresh guy, I don't know which simulation should I use (Harmonic Balance or Transient?) and which diode is better for my design? (ma44769 or HSMP3822? Somebody suggest 3822 for it's cheaper) What's more, the diode model is needed. Someone gave an address in this f

## floating point multiplier in VHDL code?

i need floating point multiplier VHDL code. if possible for 8,16 and 32 bit.

## One question of hspice/spectre simulation?

I do not know what is useable in Hspice but in most spice you be limited to a nonlinear cap. So the control voltage is the cap voltage themselve. I think you have to use an analog behaviour with an integration function and a multiplier or a function for the integration time constant.

## multiplier & filter/Match

Hello all, I am new to RF design and I am in need of some help. VSWR helped me do an amplifier design in Genesys but what I what to do now is make a multiplier. The overview is: Osc running at 25mhz > buffered > Filter/match to 50mhz harmonic > Buffer x2. I managed to do the amplifier opt/simulation with the help of VSWR, but I am unclea

## Help me with phase locked loop simulation in Spice

I am trying to simulate a Phase Locked Loop in spice. I have created all the nodes and placed all the transistor, resister, etc. into the simulator. I am using the same setup as what is found on the spec sheet of the LM565 (pg 7 - top). I also don't have the multiplier in the cct. So pin 4 and 5 are shorted together, just to see if it works. Any

## Automating the Simulation Process. (Spectre, Verilog-A)

Dear all, I have a model. The Model is shown in the following link below. It has an 1) 8-bit Adder 2) a Verilog-A Module 3) Some VPWLF Sources which take "files" as inputs. Some facts: 1) I have to simulate it for 8, 12 and 16 bit adders.

## How to simulate a multiplier (frequency doubler) ?

You can simulate a frequency multiplier (e.g. frequency doubler) nonlinear behaviour using harmonic balance simulation. Most microwave simulation and analysis programs, such as Agilent Advanced Design System (ADS), Appwave's Microwave Office (MWO) and Eagleware's Genesys has this feature. I have designed a multiplier (...)

## Step Recovery Diode (SRD) Multiplier

You still need the book "Computer-Aided Design of Step Recovery Diode Frequency multipliers" ?

## What is the difference between mixer and multiplier?

Well, a mixer and multiplier are of same type of architecture. The function realized by a multiplier and the mixer are the same. So, you must be using Spectre for simulation which is fine. Usually people use single quadrant gilbert cell type.

## diva LVS error ---diva don't recognize bjt m multiplier

Dear all I want to use(m) multiplier of bjt to optimise our design flow. but netlist file of schematic don't include m(only have area item) for MOSFET is ok, who can tell me how to set it. Thanks, rehty

## How to implement a 2x clock multiplier in digital logic?

Hi, Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz? Thanks

## The phase noise chaterstics at output of frequency multiplier

hi all, i have a oscillator followed by frequency multiplier, i wanted to know the phase noise chaterstics at output of frequency multiplier. i use cadence for simulation of my circuit, problem is chosing the oscillator i am getting diffrent Phase noise charaterstic when i choose 1)oscillator as oscillator 2)frequency (...)

## What PNP Bipolar modular to choose for bandgap simulation?

The simulation is no relation with process,because you have already known the substrate PNP can be done in the CMOS process.marth the is ok!

## [Req] frequency multiplier ADS demo

do anyone have sample of the ADS simulated frequency multiplier file? I would like to study some method on how to draw a frequency doubler schematic on the ADS.

## SIGE HBT BJT Frequency multiplier and AWR

Hello kosolson, AWR has standarad example on multiplier (FET & Diode) in the xamples folder... I think you can use FET multiplier example to see the setup for Nonlinear (HB) simulations which includes RF Source port, Biasing & Nonlinear measurements... To open this example go to your AWR Microwave Office (MWO) folder on your (...)

## How to do AC analysis of a 4 quadrant analog multiplier

hi i m designing 4 quadrent analog multiplier. there r four ip terminal in my strecture. i m giving V1+v1, V1-v1, V2+v2, V2-v2, signal at the input terninals, where V is D.C. bias and v is analog signal. i m gettin correct out put.but i dont know how can i do a.c. analisis of the circuit. i mean apply same ac signal at all the terminal with some

## bipolar device simulation parameter

what is the difference between device area and multiplier in bipolar device paremeter. in my opinion, device area is the emitter area coefficient ( for example : merged two 8*8 emitter area in a 8*16) and multiplier is the paralled device number?? whether that is correct???? thanks all

## CMOS Gilbert cell multiplier...

This paper is implemented using a W/L of 10/30 and now we are trying to implement it using 0.5 um AMI technology. What least value we can assign to W/L..? Please help...

## conjugate match of frequency multiplier

I am going to design a W-band frequency tripler using the package ADS, in order to get better efficiency, the source impedance should conjugate match the input impedance of varactor diode, and the load impedance shoule conjugate match the output impedance of varactor diode. But I dont't know how to conduct the conjugate match. When I optimized the

## THD+N (Asin wt) - sine wave without multiplier is infinity

Hi. I generated 1 sine wave (24bit output). In order to control the amplitude, the output multiply with a ratio(fixed point multiplier). for fix point multiplication, verilog declaration sin //zero pad ratio result_mult Asin <= result After the simulation, i realised that the THD+N is 74(-80db to

## Is Pspice suitable for a timing simulation

Hello, Yes, pspice is suitable for timing simulation as it has a transient simulation option where you get results versus time. It solves the time domain equations that belongs to your circuit components. For your special case, if you can convert what you want to a combination of circuit components and equations, you can do it. Pspice also e

## Problem with the simulation of MULT18X18 in modelsim

hi i have written a code to run the multiplier MULT18X18 placed in the libraries of virtex 2. When i simulate the multiplier in modelsim i dont the output. there is always an unknown value shown at the output. i have generated a 1 us clock in the test bench. when synthsized there is a warning that appears at that time "The block MULT18x18 is a

## Transient characteristic of multiplier

Hi, Currently i am using Proteus 7.4SP3 to simulate the AD633 multiplier. The two input is a trend of pulses and i want to get the output. The problem is that it occur 2 warnings which is then stopped my simulation. 1. DELMIN increased to 1.11022e-016 due to lack of time precision 2. TRAN: Timestep too small; timestep = 0: tr

## how to simulate the coefficient of a multiplier

hi guys i want to design a multiplier with the function of VOUT=K*(Vcomp-2)*Vin,in which Vcomp and Vin are two terminals of the multiplier. could anyone help me with the simulation of K when Vcomp equals to 3 and Vin equals to 1? thx

## problem with gate-level simulation

thanks for your reply,but i have initialized the registers,and its just a multiplier,it does not have multiple drivers can you try initializing all registers before you start the simulation run. Basically make sure all flip-flops have some valid value (0 or 1 NOT x) at the beginning of simulation. The x can also appear

## gilbert multiplier using cmos inverter in mixedmode simulation

hello friends i have to design gilbert multiplier ckt using mos and cmos structure. plz tell me hw will we design cascading of this ckt in spice code mixedmode simulation.and dc simulation i am doing work on silvaco plz tell me solution of this problem.

## Booth multiplier problem, signal and blocks removed...

Hi, i am trying to implement a Booth multiplier in VHDL using ISE Webpack. I use a Nexys 2 500 board. This is my first project using VHDL (and FPGA in general) so there are some issues that i still do not understand. First, i completed the project and simulated it. It worked and all went fine. Then i tried to generate the programming file to mou

## 8X8 multiplier testbench problem (ISIM)

Hi , can you tell me why im getting UUUUUUUU for first value of product...and it seems like all the values of product are shifted right..... is it something to do with the clock? ive attached to testbench coding and simulation. THanks! :D

## frequency multiplier using Xilinx System Generator

Basically an all-digital PLL (ADPLL) can be a solution to your problem. You didn't mention the intended output waveform of the PLL. In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. I

## Gilbert multiplier ac analysis

The multiplier implements y = x*y and you set x or y to zero, what do you expect? If AC analysis should make sense at all, you have to set the other input to a constant DC level.

## Query Regarding CMOS Four-Quadrant Multiplier

Hii all, I'm Designing a CMOS Four Quadrant Miltiplier using bias feedback techniques, the schematic for which is attached. I'm using Tanner for simulation. Also, i'm following 0.5 microns technology. The specifications for the transistors are as follow: * SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 19, 2011 at 13:4

## 4-bit x 4-bit array multiplier design using DSCH and Layout Simulation usingMicrowind

Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please help m

## clock multiplier in verilog with model sim

hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t

## Layout Simulation for multipliers in microwind 3.1.

I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I am not able to view the correct (...)

## How to do power simulation of CMOS digital multiplier using SPICE

Hai I am presently designing tree multiplier using spice.i want to analyze the power of the circuit can anyone help me to provide some test setup or how to analyze the power of the circuit using spice.

## Problems with hardware-co-simulation in simulink (spartan 3 xc3s-pq208) in XFLOW

Hello everybody. I am experiencing problem in hardware co-simulation in spartan 3e board. I am designing a system that requires two consecutive multipliers. for single multiplier the system works fine. however, when both multipliers are there, during generation of JTAG block, towards the end of XFLOW it shows an error, (...)

## QPSK modulator and demodulator Simulation

Hi all; Please I need Good simulation program to test hardware implementation for QPSK modulator and demodulator ,,,,,,,, I used Circuitmaker and it gives errors ??!!! ,,,,,,,,,, and multisim does not have MC1496 as all Suggestions around the world worked as multiplier ???? Thank you for any help Rawan Ayyoub

## vhdl multiplier 4 bit by 4 bit design with shift registers

hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; us

## 'Rubber diode' / Vbe multiplier

Thinking would help, there's a hierarchy of both parameters. You'll decide first about driver current and then about Vbe circuit dimensioning. I am a novice here mate. I really need a worked example to get my bearings so to speak. I have since found this web site containing a specific example: www.jopdesign.

What is your used a technique for designed rectifier ? u mean the rectifier type..? it is villard voltage multiplier. i copy the circuit directly from a paper but didnot get at least the approximate value for the output

## Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

That would prevent a latch from forming, but it does put a mux on the multiplier output which may be unnecessary. I dont understand quite why you need to "start" and "stop" the multiplier. Your design appears to just multiply two numbers. You could quite easily see these values on a simulation. You know when data is valid as the (...)

## Voltage Multiplier/doubler? Help explain circuit operation

Hi I was trying to figure out this circuit but could not figure out its operation. I had done a simple simulation, it seemed to work as per intention, i.e. a DC voltage doubler/multiplier?.. Can somebody help me understand how it works and its circuit tradeoffs. BTW - this is not the typical flying capacitor/switching diodes circuit. its only

## Help me design a 32 bit ALU in VHDL

hi all, I was thinking of designing a 32 bit alu with vhdl.. I have coded with functionalites add,sub,and,or,etc....(no multiplication and divsion).. My doubt is i just wrote case (selectinput) when 001-> c<- a and b; likewise.. is it this much easy to design an alu.. or I am doing something wrong .. pleas advise.. also How would

## Does Power Estimation Propagate Switching Activities?

hello, I am trying to do power estimation on a fairly complex design using Synopsys Power Compiler. So far I only set switching activities by hand. If I, e.g., set the switching activities for the inputs of a multiplier, will the power compiler estimate correct switching avtivities for all internal nets of the multiplier? If yes, how complex can

## How to use LUT, give a simple examples ?

I have read some information about LUT in FPGA, but I wonder that How to use LUT in Verilog program for Altera chip. Anybody can load a simple program use LUT by verilog for me and compare the perfomance with the program without using LUT ? I am confusing about LUT definition and can not make it clearly. In addition, I try to design a fast

## Anybody can correct this error ?

This is code to implement FIR by Verilog for FPGA. I have simulated it by Quartus 4.0 and find that the result is not corrected in the first cycle but corrected in the second cycle. I can not explain what reason ? I attach my simulation file and mark the error for two cycles . Anybody can help me ? //************************************

## Xilinx Spartan 3 Vs Lattice EC(P) device and tools

I assume the Xilinx tools will be marginally better, but that doesn't mean the Lattice tools are bad. They use Leonardo (migrating to PrecisionRTL) and Synplicity for synthesis, and Modelsim for simulation. At the back and the floorplanner and P&R is probably similar as Xilinx's. With regards to the hardware, I assume it is debatable wether EC/ECP

## Project ideas for M.E. about VLSI signal processing

1.GO FOR SOME STANDARD CELL BASED CARRY SAVE multiplier ,carry save adder 2.CODING AND DECODING OF A DIGITAL SIGNAL FOR TRANSMISSION VIA MOBILE PHONE 3.analysis of available arithmetic built in self test(ABSIT) schemes and development of a decoder generator for a digital signal processor 4.development of building blocks for a current