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Hi all, I want to design a 1GHz×5 SRD frequency multiplier use Agilent ADS. For a fresh guy, I don't know which simulation should I use (Harmonic Balance or Transient?) and which diode is better for my design? (ma44769 or HSMP3822? Somebody suggest 3822 for it's cheaper) What's more, the diode model is needed. Someone gave an address in this f
I am designing a 2 quadrant multiplier and 4 quadrant multiplier (simulation purpose)based on translinear operation..could someone help me out with what is the difference between a 2 and 4 quadrant multiplier and how to apply it on translinear circuits?
i need floating point multiplier VHDL code. if possible for 8,16 and 32 bit.
hello friends i have to design gilbert multiplier ckt using mos and cmos structure. plz tell me hw will we design cascading of this ckt in spice code mixedmode simulation.and dc simulation i am doing work on silvaco plz tell me solution of this problem.
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please help m
Hai I am presently designing tree multiplier using spice.i want to analyze the power of the circuit can anyone help me to provide some test setup or how to analyze the power of the circuit using spice.
Hello all, I am new to RF design and I am in need of some help. VSWR helped me do an amplifier design in Genesys but what I what to do now is make a multiplier. The overview is: Osc running at 25mhz > buffered > Filter/match to 50mhz harmonic > Buffer x2. I managed to do the amplifier opt/simulation with the help of VSWR, but I am unclea
You can simulate a frequency multiplier (e.g. frequency doubler) nonlinear behaviour using harmonic balance simulation. Most microwave simulation and analysis programs, such as Agilent Advanced Design System (ADS), Appwave's Microwave Office (MWO) and Eagleware's Genesys has this feature. I have designed a multiplier (...)
Well, a mixer and multiplier are of same type of architecture. The function realized by a multiplier and the mixer are the same. So, you must be using Spectre for simulation which is fine. Usually people use single quadrant gilbert cell type.
Dear all I want to use(m) multiplier of bjt to optimise our design flow. but netlist file of schematic don't include m(only have area item) for MOSFET is ok, who can tell me how to set it. Thanks, rehty
Hi, Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz? Thanks
hi all, i have a oscillator followed by frequency multiplier, i wanted to know the phase noise chaterstics at output of frequency multiplier. i use cadence for simulation of my circuit, problem is chosing the oscillator i am getting diffrent Phase noise charaterstic when i choose 1)oscillator as oscillator 2)frequency (...)
The simulation is no relation with process,because you have already known the substrate PNP can be done in the CMOS process.marth the is ok!
do anyone have sample of the ADS simulated frequency multiplier file? I would like to study some method on how to draw a frequency doubler schematic on the ADS.
Can anyone show me how to setup the simulation in AWR for a BJT frequency multiplier? I am using an Active biasing network also. Thank you, ks
hi i m designing 4 quadrent analog multiplier. there r four ip terminal in my strecture. i m giving V1+v1, V1-v1, V2+v2, V2-v2, signal at the input terninals, where V is D.C. bias and v is analog signal. i m gettin correct out put.but i dont know how can i do a.c. analisis of the circuit. i mean apply same ac signal at all the terminal with some
I am going to design a W-band frequency tripler using the package ADS, in order to get better efficiency, the source impedance should conjugate match the input impedance of varactor diode, and the load impedance shoule conjugate match the output impedance of varactor diode. But I dont't know how to conduct the conjugate match. When I optimized the
Hi. I generated 1 sine wave (24bit output). In order to control the amplitude, the output multiply with a ratio(fixed point multiplier). for fix point multiplication, verilog declaration sin //zero pad ratio result_mult Asin <= result After the simulation, i realised that the THD+N is 74(-80db to
Hello, Yes, pspice is suitable for timing simulation as it has a transient simulation option where you get results versus time. It solves the time domain equations that belongs to your circuit components. For your special case, if you can convert what you want to a combination of circuit components and equations, you can do it. Pspice also e
What multiplier topology did you use? Could you upload an image of your circuit? Could you also upload your simulation results?
Hi, Currently i am using Proteus 7.4SP3 to simulate the AD633 multiplier. The two input is a trend of pulses and i want to get the output. The problem is that it occur 2 warnings which is then stopped my simulation. 1. DELMIN increased to 1.11022e-016 due to lack of time precision 2. TRAN: Timestep too small; timestep = 0: tr
hi guys i want to design a multiplier with the function of VOUT=K*(Vcomp-2)*Vin,in which Vcomp and Vin are two terminals of the multiplier. could anyone help me with the simulation of K when Vcomp equals to 3 and Vin equals to 1? thx
thanks for your reply,but i have initialized the registers,and its just a multiplier,it does not have multiple drivers Is it timing simulation? any violations?
I want to make a frequency multiplier (60 Hz input frequency, output frequency of 120 Hz) using an FPGA (Spartan 3E). Can anyone help me with an example of whether or not you can do this. I already check that can be done with a DPLL but it is very difficult to implement.
Hello, I am trying to plot the ac response of a gilbert cell multiplier. I have set the differential pair inputs as V1 + v1 and V1 - v1. For the quad transistors, I have given V2 + v2 and V2 - v2 as inputs. To perform ac analysis, I have set the quad pairs ac magnitude as 0 and the diff pairs ac magnitude as 1, now after performing the simulati
Hii all, I'm Designing a CMOS Four Quadrant Miltiplier using bias feedback techniques, the schematic for which is attached. I'm using Tanner for simulation. Also, i'm following 0.5 microns technology. The specifications for the transistors are as follow: * SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 19, 2011 at 13:4
hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t
I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I am not able to view the correct (...)
Hello everybody. I am experiencing problem in hardware co-simulation in spartan 3e board. I am designing a system that requires two consecutive multipliers. for single multiplier the system works fine. however, when both multipliers are there, during generation of JTAG block, towards the end of XFLOW it shows an error, (...)
Hi all; Please I need Good simulation program to test hardware implementation for QPSK modulator and demodulator ,,,,,,,, I used Circuitmaker and it gives errors ??!!! ,,,,,,,,,, and multisim does not have MC1496 as all Suggestions around the world worked as multiplier ???? Thank you for any help Rawan Ayyoub
hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; us
What is your used a technique for designed rectifier ? u mean the rectifier type..? it is villard voltage multiplier. i copy the circuit directly from a paper but didnot get at least the approximate value for the output
That would prevent a latch from forming, but it does put a mux on the multiplier output which may be unnecessary. I dont understand quite why you need to "start" and "stop" the multiplier. Your design appears to just multiply two numbers. You could quite easily see these values on a simulation. You know when data is valid as the (...)
Hi I was trying to figure out this circuit but could not figure out its operation. I had done a simple simulation, it seemed to work as per intention, i.e. a DC voltage doubler/multiplier?.. Can somebody help me understand how it works and its circuit tradeoffs. BTW - this is not the typical flying capacitor/switching diodes circuit. its only
I am replicating an IEEE paper using Low-Power split-path data-driven dynamic logic. Since they are not standard logic blocks I was not able to synthesize it from RTL so I did fully custom schematic and layout by hand. The design is a 16x16 bit multiplier, and the layout passes DRC/LVS without any warnings or errors. I have ran about 35 random
Without more information, you can hardly model the circuit on a transistor level. A behavioral simulation using a piecewise linear function to reproduce the gain curve and a multiplier block should be feasible. But what's the objective of your simulation? Obviously you can get out only the information you put in before.
Hi friends, Here is two codes for FSK simulation in white noise but theoretical and simulated curve is not coming same. PLEASE correct following two codes of FSK simulation if possible so that both Simulated and Theoretical curve coincide and reply me how I correct these codes. CODE 1:- % FSK Modulation clc; clear all; close all; %GENER
Hi, When I perform the logic synthesis in rtl compiler it deletes some "unused" bits, thats ok, I perform the post logical synthesis simulation and the results are still ok. I tell the compiler not to perform the optimization and maintain the bits and the simulation is still OK. My problem is when I perform the simulation after (...)
Suppose, a 4-bit x 4-bit array multiplier has been designed using the AND gates and Adders. My question is- Whether that multiplier is analog device or digital device? Since the transistors are used to design that multiplier, it must be an analog device. But the inputs and outputs of that multiplier are digital (in bits). (...)
The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time. The code can probably run in simulation if z_temp is cleared before the loop. Adding the multiplicator n times is also the worst way to make a multipli
Hi, I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me. Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. (...)
Hi all, I am conducting simple noise simulation like 109932 using parametric simulation I sweeps the gate (VG) and input (VS) voltage and load capacitance(C). According to theory, the thermal noise depends on load capacitance. Therefore, the noise power is not related with gate and input voltages. Because l
I will upload PC DSP in filemanager(New) in savvas folder. DSP is software tools for digital signal processing and simulation applications more information: :):):):)):):):):)):):):)
How can I simulation circuit with Xilinx Foundation 4.1? (there isn't any package) I remember that in Fondation 2.1 it exists... How can I do ? ***************************************** Please don't reply unless you have useful information to add on this post. Thanks
Does anyone know... Is there any software that can be use to simulate the PLC program without using PLC(hardware).? All information regarding this topic will be highly appreciate. Thx you IN advance :smile: :razz: _________________ TheOne ***************************************** Please don't reply unless you have useful informat
i'm looking for a digital logic simulator for a small project of mine: should be a program easily interfacable from c (because the c code will generate the electronic circuits). in fact i'd prefer to have the source code and i probably will end up writing my own if i find nothing suited for my task. does anybody know about such a simulator (no spic
Hi all, Is there a RF simulation program except Aplac in which I can use the BSIM3 model? md
Hi PPP is a Web-based environment for Low-Power Design. Its Graphic User Interface is a set of dynamically generated HTML pages that can be accessed through any Web-browser. Three sets of tools are available: Synthesis for low-power, Power Optimization and Power simulation. File Transfer utilities are also available to upload input files and dow
Hi These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech. This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Is there any one can tell me whether Saber is suitable for system simulation? Epecially for optical communication system. How about its accuracy? Thx