Search Engine www.edaboard.com

Multiplier Simulation

Add Question

39 Threads found on edaboard.com: Multiplier Simulation
Hi I created an array multiplier in schematic mode with S-edit,then I extracted spice netlist,but I don't know what is this technology process,because transistors is defined like following line: M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1 I want to simulate this netlist with 0.18 micron technolo
Hi friends.. I have used TANNER for simulation. Can we generate the layout of a circuit directly from its schematic using TANNER like MICROWIND ? If a circuit consists of about 1000 MOSFETs, which tool should I prefer for layout designing and optimization: TANNER or OrCAD(Lite Version) or LTspice or LTpowerCAD ? I want to design a 4x4 mult
Hello, I am designing the controller for booth multiplier. (more info on will be found : BOOTH multiplier ). You can see the ASM CHART ON THE LINK. However, i've added a few more states like hold and end to it. But leaving the design aside, can anyone please see what is wrong with the co
The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time. The code can probably run in simulation if z_temp is cleared before the loop. Adding the multiplicator n times is also the worst way to make a multipli
Hi I was trying to figure out this circuit but could not figure out its operation. I had done a simple simulation, it seemed to work as per intention, i.e. a DC voltage doubler/multiplier?.. Can somebody help me understand how it works and its circuit tradeoffs. BTW - this is not the typical flying capacitor/switching diodes circuit. its only
Thanks Mohamed - OK, so the design consists of an oscillator, transformer and a Cockroft-Walton voltage multiplier chain. With this type of approach you'll be able to deliver an attention-getting (transiently painful) *SNAP* to anyone who touches the output terminal(s - don't forget to provide a ground contact near the HV output), but it won't ent
i m designing a multiplier with 2 d bypassing.This requires module to be called on conditional basis of input.Module "muxsum" and "fa" are being called depending on the input the input is given after simulation,so the condition on b is not acceptable."b" is input.Please help and guide. generate for(ii=0;ii
hi im trying to make a mmultilier of 4 bit by 4 bit here under is my code however i have some problems as its not working. it diviide the program in two clock cycles by the state however the program is not changing any type of help is reallyy appreciated thanks library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; us
Hi all; Please I need Good simulation program to test hardware implementation for QPSK modulator and demodulator ,,,,,,,, I used Circuitmaker and it gives errors ??!!! ,,,,,,,,,, and multisim does not have MC1496 as all Suggestions around the world worked as multiplier ???? Thank you for any help Rawan Ayyoub
Hello everybody. I am experiencing problem in hardware co-simulation in spartan 3e board. I am designing a system that requires two consecutive multipliers. for single multiplier the system works fine. however, when both multipliers are there, during generation of JTAG block, towards the end of XFLOW it shows an error, (...)
Hai I am presently designing tree multiplier using spice.i want to analyze the power of the circuit can anyone help me to provide some test setup or how to analyze the power of the circuit using spice.
i want to run a monte-carlo simulation for transistor mismatch in Hspice, i find this cod for monte-carlo simulation in hspice manual, .TRAN 1n 10n sweep MONTE=val .PARAM xx=GAUSS(nominal_val, rel_variation, sigma <,+ multiplier>) but i don't know the amount of rel_variation and sigma for TSMC 0.18 dos eny
I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I am not able to view the correct (...)
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please help m
Hii all, I'm Designing a CMOS Four Quadrant Miltiplier using bias feedback techniques, the schematic for which is attached. I'm using Tanner for simulation. Also, i'm following 0.5 microns technology. The specifications for the transistors are as follow: * SPICE netlist written by S-Edit Win32 7.00 * Written on Nov 19, 2011 at 13:4
How to break the loop to simulate loop gain using spectre or hspice in this ciruit?
Hi , can you tell me why im getting UUUUUUUU for first value of product...and it seems like all the values of product are shifted right..... is it something to do with the clock? ive attached to testbench coding and simulation. THanks! :D
hi,deal all i meet a problem when i simulate a multiplier with spectre,as we know,the formula of a multiplier is VOUT=k*v1*v2(v1 and v2 are the two terminals of the multiplier),i use vsin as the stimulation source to simulate the coefficient k. the simulation result indicates that the VOUT is higher when i assign (...)
Hi, i am trying to implement a Booth multiplier in VHDL using ISE Webpack. I use a Nexys 2 500 board. This is my first project using VHDL (and FPGA in general) so there are some issues that i still do not understand. First, i completed the project and simulated it. It worked and all went fine. Then i tried to generate the programming file to mou
hello friends i have to design gilbert multiplier ckt using mos and cmos structure. plz tell me hw will we design cascading of this ckt in spice code mixedmode simulation.and dc simulation i am doing work on silvaco plz tell me solution of this problem.
hi guys i want to design a multiplier with the function of VOUT=K*(Vcomp-2)*Vin,in which Vcomp and Vin are two terminals of the multiplier. could anyone help me with the simulation of K when Vcomp equals to 3 and Vin equals to 1? thx
Hi, Currently i am using Proteus 7.4SP3 to simulate the AD633 multiplier. The two input is a trend of pulses and i want to get the output. The problem is that it occur 2 warnings which is then stopped my simulation. 1. DELMIN increased to 1.11022e-016 due to lack of time precision 2. TRAN: Timestep too small; timestep = 0: tr
What multiplier topology did you use? Could you upload an image of your circuit? Could you also upload your simulation results?
Hello, I have a VHDL multiplier design that I am trying to synthesize with Design Compiler. The output is correct and verified through simulation, but it is being broken up into different modules, with some of the modules making calls to the other modules. I would like to generate the verilog gate-level netlist with all of the code in a sing
hi i have written a code to run the multiplier MULT18X18 placed in the libraries of virtex 2. When i simulate the multiplier in modelsim i dont the output. there is always an unknown value shown at the output. i have generated a 1 us clock in the test bench. when synthsized there is a warning that appears at that time "The block MULT18x18 is a
Hi all, I want to design a 1GHz×5 SRD frequency multiplier use Agilent ADS. For a fresh guy, I don't know which simulation should I use (Harmonic Balance or Transient?) and which diode is better for my design? (ma44769 or HSMP3822? Somebody suggest 3822 for it's cheaper) What's more, the diode model is needed. Someone gave an address in this f
I am designing a 2 quadrant multiplier and 4 quadrant multiplier (simulation purpose)based on translinear operation..could someone help me out with what is the difference between a 2 and 4 quadrant multiplier and how to apply it on translinear circuits?
Hi. I generated 1 sine wave (24bit output). In order to control the amplitude, the output multiply with a ratio(fixed point multiplier). for fix point multiplication, verilog declaration sin //zero pad ratio result_mult Asin <= result After the simulation, i realised that the THD+N is 74(-80db to
Hi All, I have read in many books that the Vt of MOSFET depends on channel length, Vsb, temp etc. I would like to know whether there is any dependency on Width/multiplier parameter of the MOSFET. Recently in HSPICE simulation, I found that the Vt of an NMOSFET is different for the following cases 1. W=8u, L=0.36u & M=1 2. W=2
For simulation, if you use multipliers in the schematic then the full drain and source area will be given in the netlist. If you use fingers then it should calculate the reduced source/drain area for the simulation. However, fingering the MOS will give you less parasitic resistance.
hi i m designing 4 quadrent analog multiplier. there r four ip terminal in my strecture. i m giving V1+v1, V1-v1, V2+v2, V2-v2, signal at the input terninals, where V is D.C. bias and v is analog signal. i m gettin correct out put.but i dont know how can i do a.c. analisis of the circuit. i mean apply same ac signal at all the terminal with some
Hi, Does anyone know how to implement a 2x clock multiplier in digital logic. I.e frequency of 1kHz to 2kHz? Thanks
Dear all I want to use(m) multiplier of bjt to optimise our design flow. but netlist file of schematic don't include m(only have area item) for MOSFET is ok, who can tell me how to set it. Thanks, rehty
hi i m doing project on pipelined multiplier accumulator... i m writing this code for simulation but there is some problem with wiat for statement Architecture behavioral of Entity mac is up to date. Compiling vhdl file in Library work. ERROR:HDLParsers:1015 - Line 37. Wait fo
Well, a mixer and multiplier are of same type of architecture. The function realized by a multiplier and the mixer are the same. So, you must be using Spectre for simulation which is fine. Usually people use single quadrant gilbert cell type.
if the coeffeicients are fixed you neednt to save the coeffeicients in rom you can implement fixed coeffeicient multiplier in verilog
My design is four quadrant multiplier (current mode) .I am in the stage of simulation using pspice and MOSIS test run parameters(AMIS 0.5um). But I want to know from fab experience of other people about matching of mirrors with respect to process.
You can simulate a frequency multiplier (e.g. frequency doubler) nonlinear behaviour using harmonic balance simulation. Most microwave simulation and analysis programs, such as Agilent Advanced Design System (ADS), Appwave's Microwave Office (MWO) and Eagleware's Genesys has this feature. I have designed a multiplier (...)
I am trying to simulate a Phase Locked Loop in spice. I have created all the nodes and placed all the transistor, resister, etc. into the simulator. I am using the same setup as what is found on the spec sheet of the LM565 (pg 7 - top). I also don't have the multiplier in the cct. So pin 4 and 5 are shorted together, just to see if it works. Any