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114 Threads found on Multiplier Verilog
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135472 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b);
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me. 135474 module mult4_4( input a, input b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wirew; wires; wirec; and(w,a,b); and(w,a,b); and(w,a,b
hi ! i want to design a multiplier 8*8 for 2's complements in verilog. the multiplier must get x and y as input which are 2's complements numbers and return another 2's complement as output . i must do it with designing half adder and full adder . help me :-D
Hi, I am using Primetime to perform Voltage scaling, then i need to get timing and power change. When I use set_voltage, i can see changes in power, timing remains the same. I have a combinational multiplier design. No clocks in verilog code. I am trying to use set_rail_voltage, but i dont know clear way. I am trying to use the following code set
Dear all I need to instantiate an Altera float-point matrix multiplier megafunction in my design, and plan to implement it with a one-hot state machine. The problem is that the filed generated by the quartus megafunction wizard have errors, such as in the .v (I use verilog) file there is Error (272006): MGL_INTERNAL_ERROR: Port altfp_matrix_mult|
i have this code and wanna to update it to multiply 4 by 3 bits any help :) thanx in advance // // // // // This file is part of the Amber project // // //
I came across a verilog example of improving power consumption in a multiplier. The original code is reg Enable; reg A, B, DataOut, MultOut, AddOut; wire A, B; always@(posedge clock) if (Enable == 1) DataOut <= MultOut; else DataOut <= AddOut; assign MultOut = A * B; assign AddOut = A + B; The assumption
As vGootimes said the FPGA equivalent to the huge, un-maintainable mess of structural verilog, would be this: module multiplier ( input a, input b, output p ); assign p = a * b; endmodule But if you want high performance you'll probably want to add a clock and include some pipeline registe
please share the code for fft computation. We have written the code for 8 bit vedic multiplier(urdhva tiryakbyham).
Unfortunate the floating point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL. For the same reason, wr
Hey all, I was wondering if you could help me with my homework. I need to implement a 4-bit multiplier at the gate-level in verilog using AND gates and adders I've drawn the layout, but I'm having trouble translating it to verilog. When I instantiate an AND-gate, how do I extract the least significant bit from the AND's output? (...)
Hi, I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me. Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea
can anyone help me build a 5x5 bit signed multiplier.. im a beginner and im trying to program it in altera Quartus II
I am trying to implement a floating point multiplier on spartan3E using verilog. And I want to display the result in LCD(spartan3E 16x2 LCD). How can we convert floating point to integer format in verilog? How can we display the floating point number in LCD? And also I wand to give input to the multiplier through a keyboa
i need code and block diagram for implementation of 16bit multiplication using carry save adder urgently. Can someone please help me out.
Do these operations in the OP state. shift one of the operands and add the other one to the product (don't shift the product).
I am designing (256x256)-bit multiplier using DSP blocks available on Xilinx FPGAs. I split operands into several chunks of 64-bits, using Karatsuba technique 256-bit multiplier can be constructed using 3, 128-bit multipliers each of which are further realized by 3, 64-bit multipliers. i have constructed 64-bit (...)
Hi, what trouble u have to written this array multipliers, having a verilog code or concept, send your written-ed verilog code. Regards, Rajavel
how to calculate the total delay when no. of clocks are used in verilog code and help me out to write the code for 8 bit wallace tree multiplier in verilog
Are you asking about a parameterizable module, where the bit length of some inputs is defined by a parameter, or do you mean that the length is variable at runtime? A generate construct can only work for the first case. generate if (SIZEPAR == 8) // instantiate 8x8 multiplier else // instantiate 4x4 mutiplier endgenerate
The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time. The code can probably run in simulation if z_temp is cleared before the loop. Adding the multiplicator n times is also the worst way to make a multipli
Hello All, I would like to make a signed multiplied on verilog, using an Spartan-6. Spartan-6 has the DSP48A1 multiplier, that is able to make a pre-sum, and a post-sum. Meaning I can write the following code: wire A, B, C, D; wire MUL = ((A + B) * C) + D; And the ISE will synthesize a DSP48A1 multiplier.
I am trying to build a ripple carry adder using a hierarchical verilog structure description. What I have is not working right... out puts are all messed up. My logic is messed up somewhere but not sure where. I grabbed the test bench from a 8 bit multiplier to use for the RCA and so I know I am overlooking something basic... any help would be g
please send me the verilog code for booth multiplier
Hi , Is it possible to use clock gating in combinational circuits like full adder , multiplier etc.. Pls give me the design or verilog code?
I want a verilog code for computation sharing multiplier
Hi Arpkum, If any one of your operand is a constant one then there is an easy way like this: Say if one of your multiplier operand is 11, then 11 can be represents in the power of 2 as 11 = 8 + 2 + 1 = 2^3 + 2^1 + 2^0 And if A is the other operand Then A*11 = A*8 + A*2 + A = A*(2^3) + A*(2^1) + A*(2^0) = A with padding 3 zero's on LSB +
Can any body help me in doing verilog code for generic multiplier ?
90236 I am trying to implement a sequential shift and add 4bit multiplier as shown in the image. I am having a separate module for the 4 bit ripple carry adder. I have tested the adder module and it works fine. now i need to trigger it from the multiplier module. so that it triggers on the 'add' signal. please help
That would prevent a latch from forming, but it does put a mux on the multiplier output which may be unnecessary. I dont understand quite why you need to "start" and "stop" the multiplier. Your design appears to just multiply two numbers. You could quite easily see these values on a simulation. You know when data is valid as the "mult_start" signa
hi i m designing a bypassing multiplier. nd in this by checking the multipler bit, we can bypass a particular row or clumn so as to reduce switching activity. but in verilog, conditional use of generate statement is not being supported for bypassing. the reason is while elaborations, we cant conditionally call any other module. so what shud i do
Hello. I am working with QuartusII. My project is Serial Mutrix multiplier and I use verilog, but when i compile my project the following error appears.Can you help me? Internal Error: Sub-system: GDFX, File: /quartus/synth/gdfx/gdfx_slice.cpp, Line: 736 (*sgate_nodes) != NULL && (*sgate_oterm_coll) != NULL Quartus II Vers
Hi, i m working on booth multiplier , everything is working, but last four assignment statements are not giving proper results. module newproj (a,b,rslt,rslt1,rslt2,rslt4,rslt3,xyz,xyz1,xyz2,xy z3); input a; input b; output rslt; output rslt1; output rslt2; output rsl
You have a 6-bit input LUT. Lower 3 bits are multiplier; high 3 bits are multiplicand. Data at address 0 is 0 (0 x 0). Data at address 10(001010) is 2 (001 x 010). Data at address 27 (011011) is 9 (011 x 011) etc.
i need to design a multiplier unit.. design idea: only binary inputs representation signed representation..can provide a sign bit input.. ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program
Hi, my code currently looks like this. Is there any way my code can accept non integer numbers (A=3.05). I read that my output has to be a reg type so how can we represent multiplication, division or addition using non integers? For ex. 3.05 + 1.07 or 1.06*5.01. If the output must be of type reg. I read online that there are very complicate
hi can u send verilog or vhdl coding of 4x4 bit braun multiplier and 4x4 baugh wooley multiplier
i really need to know if is possible to multiply a clock frequency in verilog or maybe someone can explain me how to delay a clock signal with a quarter of a period
Why is not it used in RTL for multiplication? Generally speaking, it is used. Thus I don't exactly understand the question. There may be reasons to instantiate explicite multiplier blocks instead of infering it from a "*" operator. It depends.
To my understanding: 1): If you want to synthesis that multiplier, you just write mul = a * b; will be ok. Then synthesis tool will synthesis this code to logic gates. 2): If you want to design a multiplier (design a multiplier architecture) with simple logic functions, such as add, OR, AND, you may need rearch the multiplier ar
I am doing my final year M.E project....For that i have drawn a 4x4 wallace tree multiplier and simulated using microwind 3.1. I have got a correct output in Schematic simulation in DSCH2.But, When i create a verilog file for that and Compile in Microwind 3.1 and create a layout, in the layout simulation, I am not able to view the correct inputs a
Spartan 3 has inbuilt 18x18 multiplier. You can directly instantiate that using MULT18X18 U_MULT18X18 ( .A () , // insert input signal #1 .B () , // insert input signal #2 .P () // insert output signal ); For details see this application notes from xilinx.
hello , i was trying to implement a clock multiplier by introducing a delay to one of the inputs to the xor gate here is my code module clkmul( clk,A,B,C); input clk; output A,B,C; reg A; always begin A <= #2 ~clk ; end assign B = #1 clk ; //v9 assign C = A ^ B; // c is ouput clock endmodule will this logic work t
Yes, there are more errors module mult8(p,x,y); output p; input x,y; reg p; reg a; integer i; always @(x , y) begin a=x; p=0; // needs to zeroed for(i=0;i<8;i=i+1) begin if(y) p=p+a; // must be a blocking assignment a=a<<1; end end endmodule P.S.: A brief co
try to use structural verilog... make code for multiplier first then connect all like this,,, : module multiplier_fn(inp1,inp2,product); input inp1,inp2; output product; assign product = inp1 * inp2; endmodule module activation_fn_2 (inp1,inp2,inp3,cin_low,cout1,out); input inp1; input inp2;
Hi, i designed a 4 x 4 array multiplier in DSCH2.6 and verified the functionality and its working properly. A verilog code is also generated. A layout is also generated using Microwind2.6. While doing layout simulation i am getting a message stating that "access violation at address 004910B7 in module 'Microwind2.exe'." Can any one please help m
i'm sorry, but i'm looking for 'structural' design type of 8*8bit multiplier So why did you ask for a verilog code? ... such as 8*8bit array multiplier... And why didn't you try G00GLE? Also look for G00GLE images! [QU
Hi, I am new to verilog. I need to write verilog code for modified booth multiplier. How to write the code for padding 1 zero to LSB of a multiplier, let's say 4bits input? Thanks. Rgds, KK
does anyone have modified booth multiplier code in verilog or vhdl?
Google is your friend. you could find an example of 4x4 braun multiplier on this document: 2.4.1 Braun multiplier :-