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Hi All, I am working on this project where I need to simulate the following circuits: > Figure 4.4 shows an xor gate. I need to know how it works and the different parameters I would need for its functioning (which are Iss, Vb I1 and R1) > Figure 4.5 shows a current-steering differential latch. I need to know what Vsource (biasing voltage sh
Hello all, was hoping someone could help me out with this. I'm trying to figure out how to design a D flip flop using nothing but 2:1 mux(s). Nothing else allowed. I can see how a latch can be designed using a 2:1 mux where the output responds instantly to the input based on the select line. however, to do this for a flop, one would (...)
Hello everyone, i would be glad if you could help me with my question. I have this boolean equation: F= BC'D' + ACD' , and i want to realise it with 4:1 Multiplexers. I have managed to realise it with one 8:1 multiplexer by using the signals D,C and B as selectors and 1,0 and A as inputs but i cannot figure out how to do it with 4:1's, since a 4:1
HI All, How can i make LATCH from mux. and also tell me That How can i make Flip-Flop from mux
I have made a good 4:1 mux it can take to 2 bits of opcode input. The opcodes are 00,01,10 and 11. I call it the No Failure Multiplexor or NF mux for short. If you want it and cannot copy and paste it email me at forest_201@hot mail.com. NOTE : THIS IS NOT A JOKE. IT IS A REAL
Hi all, Below is the verilog code for posedge and negedge flipflops using mux. I have also attached the pictorial representation of the circuit. Verilog code : module mux_ff( clk, in, out_pos, out_neg ); input clk; input in; output out_pos; output out_neg; wire clk; wire in; reg (...)
Can anyone draw a 4:1 priority mux that in synthesized using an if elesif statement? Please provide the RTKL of the 4:1 mux also, if possible.
Hi all. I have a below schematic: there are two clocks named clk1 and clk2. Then they are selected by a mux, then the output clock is divided by a two divided register. Then the output of the register is used as the main clock for the following logic.
Can someone give me a suggest on how to built RS-232 multiplexer? from 1 com port from computer(host) to became 64 com port(slave) or 32 com port(slave) basicly controller by RTS or DTR and CTS or DSR Host(computer) for decided which com slave active. The speed from 115.2K to 57.6K or 38.4Kbps. system block 1.PC Com---max232--MCS-51
Can someone give me a suggest on how to built RS-232 multiplexer? from 1 com port from computer(host) to became 64 com port(slave) or 32 com port(slave) basicly controller by RTS or DTR and CTS or DSR Host(computer) for decided which com slave active. The speed from 115.2K to 57.6K or 38.4Kbps. system block 1.PC Com---max232--MCS-51
Can someone give me a suggest on how to built RS-232 multiplexer? from 1 com port from computer(host) to became 64 com port(slave) or 32 com port(slave) basicly controller by RTS or DTR and CTS or DSR Host(computer) for decided which com slave active. The speed from 115.2K to 57.6K or 38.4Kbps. system block 1.PC Com---max232--MCS-51
U can implement the ex-or gate using 1. Nand gate 2. Nor gates 3. a(bbar)+ b(abar) => 2 and, 2 inverter, 1 or 4. mux (cmos or TG or...)
i will suggest use the pll at the o/p of mux...
I also have an idea like cipi said use a mux to switch b/w channels and then add a dc voltage depending on the channel selected for example when ch1 is selected by mux add 5v dc so that its on top of the screen and when ch2 is selected add 2.5V so its on middle of top half and so on......
I had the same question. See Question 45 in this book: . That discusses switching power supplies, but I think "cross-conduction" is more general. You have a situation where there are two transistors, only one of which should be on at any given time. for example, you might be selecting one of two power inputs (IN1 and IN2) to b
Hi, can we use only the mux mux i_mux (.inp0(OUT), .inp1(D), .out(OUT), .s(CLK)); ?? regards Yes, as a matter of fact you can. Check this out:
Well, dont expect us to do your work for you. If your VHDL is not good, get on a VHDL tutorial. It sounds like he wants you to mux the two 4x4 rams
Your mux needs AND gates with two to n+1 inputs per gate and n+1 gates. Then there are 3 output mux gates to select >,=,< for A & B with n bits each. pour s'amuser, study
hi, i am new CPLD and FPGA, i want to how to start with CPLD and what are the software tools required, if write a code for FGPA will it work for CPLD Can i implement the Basic gate, mux , Adders, Subtractor and Shift register using CPLD or not, i think i may asked very stupid question because i am very new to this, (...)