1000 Threads found on edaboard.com: Mux Questions
Draw an inverter. Draw the layout. No, I use a P-well process (or whatever is opposite of what you draw) Redraw it.
Draw a 4-1 mux using transmission gates (or whatever they think you don't know based on how you answered #1)
What tools do you know? Do you know Verilog (or VHDL)? How many pins was the biggest project you have made? Wha
EDA Jobs :: 06-21-2003 04:32 :: electronrancher :: Replies: 12 :: Views: 6580
i am having a 2X1 that select line is X (unknown state) what will be the output.
input may be 0 or 1.
if the select is z (high impedance what will be the ouput
If select line is X then the output will also be X . Although this depends on the way u have coded if u have used if -else type not considering then ur
Electronic Elementary Questions :: 04-28-2005 10:58 :: semiconductorman :: Replies: 1 :: Views: 1148
does any one konw what is the logic expression of a mux?
ASIC Design Methodologies and Tools (Digital) :: 08-18-2006 04:08 :: foster_cn :: Replies: 10 :: Views: 3306
can u help me solving this digital question
To built an 4 bit 2's complement number using 2:1 mux?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-21-2006 07:07 :: vikram161 :: Replies: 10 :: Views: 1539
I am using two 555 timers to generate two different frequencies. They work great. However, I want to use the 74LS157 2 to 1 mux to control which frequency goes through. When i connect the two out puts of the 555 timers to the inputs of the mux i get strange waveforms out. My select function is changing at rate of around 100 Hz. I hooked the
Analog Circuit Design :: 03-22-2007 09:49 :: nwo4life :: Replies: 2 :: Views: 1091
porosity comes form 'porous'. Its basically air gaps in dilectric layers, which reduces the di-electric constant of the layer.
4 or less inputs in a gate: has to do with its input loading. If the input loading is higher, the propagation delay will be high. May be 4 is the sweet spot, and if more inputs are required, then you'd use 2 gates in par
ASIC Design Methodologies and Tools (Digital) :: 08-06-2007 08:27 :: avimit :: Replies: 4 :: Views: 1381
Can any one post the viva questions and answers for digital electronics lab.
The experiments are
1.half adder and full using NAND
2.binary to gray code converter
3.gray to binary code converter
4.BCD to Excees3 code converter
5.binary adder/subtractor and BCD adder using IC 7483
Electronic Elementary Questions :: 10-17-2010 11:09 :: atchutharam :: Replies: 6 :: Views: 10606
1. your comparator can either drive a chain of tapered inverter- also known as tapered buffer. That generally drives bigger loads with improvement in delay. If you wish to drive even larger load- try reading about Hidh Drive Buffer- i drove 1nF cap using that. But in your case- I guess tapered buffer should help you..
2. for jitter analysis- expo
Analog IC Design and Layout :: 05-08-2011 17:58 :: dhaval4987 :: Replies: 1 :: Views: 561
Hello all (First post on forum)
I understand that I have yet to contribute anything to this community and therefore you will be unlikely to help me, but I'm hoping someone will find it in their heart to offer assistance.
Basically I am revising for a University resit exam that's coming up for a Computer Systems module. For the most part, I can
Electronic Elementary Questions :: 08-10-2011 06:43 :: Swedish Rambo :: Replies: 4 :: Views: 521
1.Difference between MULTIPLEXER and ENCODER
2.What is DATA SELECTOR?(multiplexer)
3.Give advantages of mux,demux,encoder,decoder,magnitude comparator.
4.What are the minimization techniques available.
5.What is TTL and state its characteristics.
6.What are sequential circuits.Give example.
7.Difference between LATCH and FLIPFLOP.
Electronic Elementary Questions :: 11-01-2011 08:57 :: v.strawberry :: Replies: 1 :: Views: 1628
There will definitely be a problem, if you are using a continuously switching signal as a select.
You need to have a clock gating check performed at these points, and if you are getting a violation then you need to fix them before proceeding.
The clock gating check can be ignored only in the case when the select signal of the mux is stat
ASIC Design Methodologies and Tools (Digital) :: 07-01-2012 03:39 :: shobhit :: Replies: 14 :: Views: 1069
In the next months i have to migrate a FPGA VirtexII VHDL design (near to million gates) to ASIC.
In the original design i use a classic FPGA flow using as main tools Synplify+Amplfy+Modelsim, but i think boundary conditions,timing constraints and layout (even synthesis) in ASIC will be very different and other flow and considerations will be us
ASIC Design Methodologies and Tools (Digital) :: 01-30-2002 05:09 :: hwswboy :: Replies: 21 :: Views: 7381
I am a newbee in FPGAs. I have a few doubts. Hope that someone can clear them.
1-Are all FPGAs have volatile memory i.e. they lose program on power down.
2-How can I make my FPGA board so that it can operate as stand alone without the interference of downloading PC everytime I wish to use it. Can anyone site a practical example.
ASIC Design Methodologies and Tools (Digital) :: 03-05-2002 01:39 :: Agent006 :: Replies: 6 :: Views: 2223
I have got 2 questions about DSP:
1°) have someone already bootload a DSP (TI c5402) via the HPI port?
2°) Does someone use the KERNEL/BIOS for real time application??
Professional Hardware and Electronics Design :: 03-08-2002 11:23 :: tibs :: Replies: 0 :: Views: 768
As we know, data multiplexing is often applied and two main implementation methods are prevalent in FPGA of Xilinx, say Spartan. They are BUFT and the combination of mux and LUT.
However, in practice, some expericense informs us that BUFT is not recommended due to its simulation mismatch and poorer performance. Also just for this, Synplify aut
Other Design :: 07-26-2002 04:32 :: Joyee :: Replies: 7 :: Views: 1757
I'm making one A/D moard with mc and I need more pins. Sounds familiar? I'm in dilema if I should use mux CD4067, but there is quite big resistance Ron. Does anyone have any experience with use of this mux circuits in real aplications. Any better solution?
Professional Hardware and Electronics Design :: 10-02-2002 19:34 :: tjalps :: Replies: 5 :: Views: 1913
I have a couple of questions regarding this subject.
1. Is there a direct way to export an allegro *.brd file to a pads ascii file?
If so, that would make things very simple for my current endeavor.
2. I am using a translator that calls for an extract of allegro for
exceptable input format. (*.txt or *.val) How is thi
PCB Routing Schematic Layout software and Simulation :: 12-31-2002 13:29 :: edaedaeda :: Replies: 2 :: Views: 4603
I have a few questions about LVDS
(1) The clock pair frequency is different from the data pair frequency. What
is the skew requirements between clock pair and data pairs?
(2) How should I measure the delay: Is it from the crossing point of the
driver differential pair to the crossing point of the receiver differential
PCB Routing Schematic Layout software and Simulation :: 01-17-2003 00:06 :: colin_cheng :: Replies: 3 :: Views: 1748
I was until now using DSP with no cache support and so was novice in uC knid of programming. Now I am supposed to port the same into DSP with cache. The DSP in question is Blackfin with L1 and L2 memory. The question is can I move program from L2 to L1 using DMA in background while I am using L1 for program execution. I do not want use L1
PC Programming and Interfacing :: 01-20-2003 04:36 :: brmadhukar :: Replies: 3 :: Views: 1097
Timing and testing in tri-state bus implementation is a problem.
The designers don't take more time to trim timing problem by using mux-based bus.
In SOC design, all most designs choose mux-based bus, because IP integration is easier.
Another benefit of the mux-based bus is to improve bus bandwidth efficiency significantly, eg. AMBA 2.0.
Microcontrollers :: 01-23-2003 02:14 :: jiang :: Replies: 28 :: Views: 6217
ASIC Design Methodologies and Tools (Digital) :: 02-03-2003 03:22 :: cin :: Replies: 3 :: Views: 6175
I have a few doubts relating to PCB design:
1. What is the significance of 'Copper Pour attached to GND NET' in PCB design?
2. What are the applications in which it is recommended?
3. Where is it not recommended?
4. Is it advisable to select the entire PCB and 'Pour Copper attached to GND NET' OR just fill certain critical areas?
PCB Routing Schematic Layout software and Simulation :: 02-05-2003 23:34 :: bimbla :: Replies: 4 :: Views: 2862
please upload some good interview questions for ASIC\FPGA job hunters.
I know there is another post on the same topic. But if anyone has more questions.
ASIC Design Methodologies and Tools (Digital) :: 03-29-2003 09:11 :: eda_wiz :: Replies: 4 :: Views: 6087
I have a coplanar T-Resonator. It's an open quarter wavelength resonator. I'm using the resonator for substrate characterization. I did 2-port measurement by taking the T arms as port 1 and port 2.
My questions are:
1. How can I extract the quality factor due to the conductor losses and the radiation losses.
2. Do I need to take the T
RF, Microwave, Antennas and Optics :: 04-07-2003 08:32 :: junction_crosstalk :: Replies: 0 :: Views: 1034
i like the Psoc and the online help.though i am a beginner on it.
i have study the PSoc for a week, and have some questions followed.
(1)on the DEVICE EDITOR interface,how to define the registers's name,such as DBA00,DBA01,DCA00,ACA00,ASA10,ASB20.. and why?
(2)on the DEVICE EDITOR interface,what means about the user module parameter such as 24v1
Microcontrollers :: 05-13-2003 00:46 :: Bely :: Replies: 2 :: Views: 998
I am programming PIC microcontrollers in Assembler. Sometimes I get stuck and don't know how to solve a problem. I think many people know what I am talking about. :) I was looking for a forum where I can ask questions on which I can't find the answers in datasheets. I found this forum. Is it possible to find any answers here? If it is, whic
PC Programming and Interfacing :: 06-10-2003 09:23 :: scandrew :: Replies: 1 :: Views: 959
In my design, I need to access the CSRs. For which I have come up with a solution of having a 40:1 mux. But seeing to the size of the mux it is not favuorable to have such a big mux.
Can anybody tell me how can I access the CSRs. Is there any way to split this big mux which will not affect the timings of the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-14-2003 02:16 :: paash :: Replies: 2 :: Views: 783
I'm starting to collect data to design IC tester and also I would like to integrate IC identifivation circuit. I have a number of questions
1- for IC identification circuit how can I apply the expected test vector to the IC whil I did not the Input and Output pins(i.e the IC can be damaged while try to now its number by appling input to output p
Professional Hardware and Electronics Design :: 10-13-2003 08:25 :: Al Farouk :: Replies: 2 :: Views: 1155
I want to insert Caller ID information on the telephone line so that a standard CLI device can display the number sent to it. I have the following questions.
1. What is the modulation type of CLI data.
2. What is the frequency and amplitude of the CLI carrier and Data
3. What is the packet contents of the CLI transmission.
I have tons of in
Hobby Circuits and Small Projects Problems :: 10-13-2003 08:33 :: techie :: Replies: 1 :: Views: 1171
can somebody tell some interview questions for PCB designer
or some other engineering job
EDA Jobs :: 10-28-2003 10:25 :: mitaka :: Replies: 1 :: Views: 6554
iam trying to switch my clock while system running
I have used a mux as a concurrent statment so that when power up If FPGA see 1 on an I/o pin it selects clock source 1 and if it see 0 it will select source 2 ...
it's a very simple code and working correctly ..
entity switclock is
Port (c1,c2,mxcon : in std_logic ;
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-17-2003 09:06 :: Vonn :: Replies: 4 :: Views: 1995
Hi to all,
I'm trying P-CAD2002 SP1.I have some questions:
- When I re-route a trace the 'loop' (the old trace) didn't delete.
Is there a flag or setup to do this command ?
- Can P-CAD import nVisage schematic and back annotate to it?
PCB Routing Schematic Layout software and Simulation :: 02-11-2004 04:36 :: mkbs :: Replies: 1 :: Views: 1080
I have two questions related to slots:
1) There is a retangular slot in a metal plate, it needs to be fed by a
2) There are two cross rectangular slots in a metal plate, two pair of
cross points on the edges of the slots need to be shorted, but two short
lines across do not connect with each other.
Could you let me kno
Electromagnetic Design and Simulation :: 02-20-2004 11:26 :: ethen :: Replies: 0 :: Views: 922
what do u mean by "mux with comma" ??
ASIC Design Methodologies and Tools (Digital) :: 02-29-2004 20:40 :: yeewang :: Replies: 3 :: Views: 1197
I need help for preparing for an interview. Interview will be based on 8051 microcontroller and its interfacing.
If anybody have "questions and Answers" type documents on this microcontroller please share.
Microcontrollers :: 03-19-2004 06:45 :: ITP :: Replies: 2 :: Views: 7357
I'm considering of designing a near EPP-compliant interface from a PC to a SLIC Si3210 evaluation board. The latter has a digital PCM input/output, both transmitted in serial manner. At this point I'm interested in transmitting data to the SLIC. For this I have found an ancient IC, the 74LS166, which is an 8-bit parallel-in serial-out (PISO) IC
Hobby Circuits and Small Projects Problems :: 04-05-2004 09:50 :: Fourier :: Replies: 2 :: Views: 1334
I just finished my first PCB with Easy-PC.But i have some questions :
1.I have single side PCB and I just can not have a right printout of Top Copper.How to print in Easy-PC?
I printed a some print-outs from printing&plotting.But i have 6 different pages and i think i selected all.I can not see drill holes of pads.How to print holes?
PCB Routing Schematic Layout software and Simulation :: 04-08-2004 17:48 :: Analyzer :: Replies: 2 :: Views: 1167
I have read the paper "concepts and methods in optimization of integrated lc vcos", and i am going to design a complementary crossed coupled lc vco.Now i have some questions on this:
1.what kind of simulation and optimization tool can i ues in this design?
now i have only the advanced design system(ADS).
2. how about the o
Analog IC Design and Layout :: 04-12-2004 21:52 :: lxb97409 :: Replies: 0 :: Views: 1349
I learn about microcontrollers from mikroelektronika's tutorial , I think it's cool , at least it made me able to start, anyways, I have some general questions ,
1) what is the main purpose of RBPU (bit 7 in option register) , I think it turns the internal pull up resistors in PORTB off and on, but what is that used for?
2) can someone please
Microcontrollers :: 04-26-2004 06:23 :: Always_Confused_Sudent :: Replies: 1 :: Views: 528
I am a newbie to use spectre. I have several questions to start with
1. I have do a dc analysis, and an output directory dc.raw/ is created. Howe to see the waveform? I have tried the AWD (analog waveform display) but I can't load the file in dc.raw
2. I have used spp to translate the spice netlist and the input .sp to
.scs, but th
Analog Circuit Design :: 04-30-2004 05:13 :: Vitamin-C :: Replies: 3 :: Views: 1357
hello evry body,
my name is kranthi ,i am going to complete my MSc in soc design,presently i am working on MSc porject "memory controller verification using specman".
could you plz inform me what type of questions generally they will ask on verification at interviews ..
if u had any prvious question could you plz send me will be very h
EDA Jobs :: 05-01-2004 09:41 :: kranthi :: Replies: 1 :: Views: 2521
GP: Ground Pad
SP: Signal Pad
@: spiral inductor
The other questions are:
1. Do I need to connect two ground pads under the signal pad on each side?
2. Do I need to draw "open" "short" "through" and "load" for calibration?
Electromagnetic Design and Simulation :: 05-06-2004 02:58 :: yorkyong :: Replies: 0 :: Views: 618
I am a bit new with timing problems and I would like to ask you three
questions. So, here we go:
In my design I have to control /CS and /RD signals. The specifications says
that the /RD signal has a setup time to the asserting of /CS of 0ns (/CS
should be asserted at least 0ns before /RD is asserted) and Thold
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-19-2004 13:22 :: mImoto :: Replies: 3 :: Views: 804
hi all, here are several questions about phase noise at LC VCO
(1). In my opinion,there are four systems: Linear Time Invarant, Linear Time Varant, Nonlinear Time Invarant and Nonlinear Time Varant. If I want to analyze the phase noise at LC VCO, which system is resonable?
I ever study some phase noise models of VCOs such as Leeson's, Abidi's a
RF, Microwave, Antennas and Optics :: 05-19-2004 22:52 :: trashbox :: Replies: 2 :: Views: 882
Could you help me on the following questions:
1. Which information are included in the verilog model?
2. In which design flow we must use the verilog model?
3. How to deal with the analog signal in verilog model? Can anybody show me a example about ADC or DAC model?
Thanks very much.
ASIC Design Methodologies and Tools (Digital) :: 05-30-2004 12:40 :: ajianer :: Replies: 1 :: Views: 1007
Has anyone ever used ADS Momentum to simulate a LNA?
Is that necessary?
I have several questions to ask:
1, how to describe the Low Noise transistor in Mom?
I have only a S2P file to make s-parameter simulation in schematic window, so what to use in Mom?
2,How to deal with the ground ports in Mom?
3,How to deal with the lumped componen
RF, Microwave, Antennas and Optics :: 06-07-2004 10:09 :: htforever :: Replies: 5 :: Views: 1280
I am a newbie in this field. I have cpuple of questions that I would like to ask.
1. With regard to data throughput of the DSP system, what govern the capacity of the system.
2. Given a typical embedded DSP application, how to estimate the data
throughput requirements of the application as well as the number of MIPS
that the embedded
Digital Signal Processing :: 06-11-2004 03:51 :: patrick :: Replies: 2 :: Views: 792
I am in US and have an undergraduate education in RF. I learnt for LNA, Mixer, Oscillator, Filter, Amplifier, Stubs, Couplers with also Design Labs and Actual impementation of them and testing them using only Network Analyzers not the real world.
What Interview questions I should expect? Mostly I am looking for any trick questions I have never l
EDA Jobs :: 07-22-2004 07:00 :: djalli :: Replies: 2 :: Views: 2153
Hi..I am using the software to simulate the transformer. In the documentation of this software, the transformer model is Fig01(attached),but it also said "this is not a circuit model for the transformer but simply a translation of the 2-port z-parameters into a particular circuit rep
RF, Microwave, Antennas and Optics :: 07-22-2004 20:35 :: trashbox :: Replies: 0 :: Views: 1044
I need synthesis a project with some gate or mux clock,
clk1 = clk1_en & clk_tx;
//clk_en1 comes from other clock domain: clk_pci
clk2 = state? clk_pci : clk_rx;
how set constraint ?
i try use set_case_analysis
or create_generated_clock, but not set right.
ASIC Design Methodologies and Tools (Digital) :: 08-17-2004 08:58 :: xigu :: Replies: 0 :: Views: 1457