8 Threads found on edaboard.com: Mux Questions
i need to implement multiplexer in matlab simulink ?
note : mux block in simulink is useful to combine signals into one vector.and i don,t this
i need to "select" only one input from all inputs and pass it (natural mux)
if i want to implement custom b
Digital Signal Processing :: 02-16-2014 03:11 :: mohamed mahmoud :: Replies: 1 :: Views: 547
1.Difference between MULTIPLEXER and ENCODER
2.What is DATA SELECTOR?(multiplexer)
3.Give advantages of mux,demux,encoder,decoder,magnitude comparator.
4.What are the minimization techniques available.
5.What is TTL and state its characteristics.
6.What are sequential circuits.Give example.
7.Difference between LATCH and FLIPFLOP.
Elementary Electronic Questions :: 11-01-2011 08:57 :: v.strawberry :: Replies: 1 :: Views: 2392
I want to know the how a mux is synthesized...how to arrive at the depth of logic for, say, a 4-1 mux with sel. in general, given N inputs and M selects and 1 o/p, how do we arrive at logic levels.
thx in advance...
ASIC Design Methodologies and Tools (Digital) :: 08-12-2009 10:07 :: putra_sena :: Replies: 2 :: Views: 991
I will try to describe the solution for you because i did not have aready file to be downloaded.
The first multiplexer has inputs as (first four lines for x x3,x2,x1,x0) (second four lines for y y3,y2,y1,y0 ) respectively the selector connected to input a. the output of this mux is A A3,A2,A1,A0 which will be directed to the positive number of t
ASIC Design Methodologies and Tools (Digital) :: 04-21-2008 07:57 :: Alkakkali :: Replies: 4 :: Views: 2940
I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal problem from
ASIC Design Methodologies and Tools (Digital) :: 04-11-2007 15:31 :: ethan :: Replies: 6 :: Views: 2173
can u help me solving this digital question
To built an 4 bit 2's complement number using 2:1 mux?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-21-2006 07:07 :: vikram161 :: Replies: 10 :: Views: 2289
does any one konw what is the logic expression of a mux?
ASIC Design Methodologies and Tools (Digital) :: 08-18-2006 04:08 :: foster_cn :: Replies: 10 :: Views: 3879
1)how can i guarentee that my FSM output is glitch free..........
Register the FSM outputs
3)what is the size of LUT if i want to implement two nindependent logic functions of 5 variables..........
4 input LUT with a Fx mux for 5 variable logic
but we cannot use the same slice for another 5 variable
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-01-2006 00:37 :: bansalr :: Replies: 1 :: Views: 1513