36 Threads found on edaboard.com: Mux Questions
Draw an inverter. Draw the layout. No, I use a P-well process (or whatever is opposite of what you draw) Redraw it.
Draw a 4-1 mux using transmission gates (or whatever they think you don't know based on how you answered #1)
What tools do you know? Do you know Verilog (or VHDL)? How many pins was the biggest project you have made? Wha
EDA Jobs :: 21.06.2003 04:32 :: electronrancher :: Replies: 12 :: Views: 6528
SOP = Sum Of product.
You can implement any logic circuit by draw it's truth table then from the truth table you can find equation for the o/p using AND & OR gates only.
CPLD uses these tech. It uses programmable AND & OR Gates array.
Note: this in simple, but actually it the Logic Cell contain Flip-Flops and mux for handle all logic
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.11.2004 08:10 :: SphinX :: Replies: 5 :: Views: 991
i am having a 2X1 that select line is X (unknown state) what will be the output.
input may be 0 or 1.
if the select is z (high impedance what will be the ouput
Electronic Elementary Questions :: 26.04.2005 02:02 :: icon :: Replies: 1 :: Views: 1126
1. It depends on your ATE machine, how many scan chain can ATE support. And the more scan chain, the less test time. So it can save more cost in testing.
2. Generally, you should use dff in your design, do not use RS-flop and JK-flop. As far as I know, current DFT tools (DFT compiler and DFTAdvisor) does not support this kinds of flops. And the
ASIC Design Methodologies and Tools (Digital) :: 18.11.2005 20:40 :: zhustudio :: Replies: 23 :: Views: 2777
1)how can i guarentee that my FSM output is glitch free..........
Register the FSM outputs
3)what is the size of LUT if i want to implement two nindependent logic functions of 5 variables..........
4 input LUT with a Fx mux for 5 variable logic
but we cannot use the same slice for another 5 variable
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.08.2006 00:37 :: bansalr :: Replies: 1 :: Views: 1213
does any one konw what is the logic expression of a mux?
ASIC Design Methodologies and Tools (Digital) :: 18.08.2006 04:08 :: foster_cn :: Replies: 10 :: Views: 3257
can u help me solving this digital question
To built an 4 bit 2's complement number using 2:1 mux?
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.11.2006 07:07 :: vikram161 :: Replies: 10 :: Views: 1480
I am using two 555 timers to generate two different frequencies. They work great. However, I want to use the 74LS157 2 to 1 mux to control which frequency goes through. When i connect the two out puts of the 555 timers to the inputs of the mux i get strange waveforms out. My select function is changing at rate of around 100 Hz. I hooked the
Analog Circuit Design :: 22.03.2007 09:49 :: nwo4life :: Replies: 2 :: Views: 1073
I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal problem from
ASIC Design Methodologies and Tools (Digital) :: 11.04.2007 15:31 :: ethan :: Replies: 6 :: Views: 1774
porosity comes form 'porous'. Its basically air gaps in dilectric layers, which reduces the di-electric constant of the layer.
4 or less inputs in a gate: has to do with its input loading. If the input loading is higher, the propagation delay will be high. May be 4 is the sweet spot, and if more inputs are required, then you'd use 2 gates in par
ASIC Design Methodologies and Tools (Digital) :: 06.08.2007 08:27 :: avimit :: Replies: 4 :: Views: 1349
there is no such a think as biderectional buses inside FPGA, even if you declare bi-directional signal inside your module compiler will have to create two separate busses.
Also there are no tri-state buffers inside FPGA better practice is to use multiplexor, again if you are puting tri-stable buffer complier will put mux.
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.08.2007 12:38 :: Iouri :: Replies: 10 :: Views: 759
If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
Design a circuit to divide input frequency by 2?
Design a divide by two counter using D-Latch.
Design a divide-by-3 sequential circuit with 50% duty cycle.
What are the different types of adder implementation?
Draw a Transmission Gate-based D-Latch?
ASIC Design Methodologies and Tools (Digital) :: 05.02.2008 08:49 :: master_picengineer :: Replies: 4 :: Views: 18693
1) Design a circuit which will either substract x from y or y from x, depending on the value of a .If a=1, the output should be x-y, and if a=0, the output should be y-x.Use a 4 bit substractor and two 4bit 2to 1 mux?
2) Realize a full adder using a 3 to 8 line decoder and a)two or gates b)two norgates
ASIC Design Methodologies and Tools (Digital) :: 03.04.2008 00:51 :: vlsitechnology :: Replies: 4 :: Views: 1650
you can use "delay cell" whose W/H is less than one.
what "W/H" mean? INVERTER, NAND, BUFFER are the fast cells. but Inverter pair has large initial delay, because of mux. NAND pair has large step delay...
i need a new structure...
Added after 34 seconds:
ASIC Design Methodologies and Tools (Digital) :: 14.11.2008 10:58 :: yibai :: Replies: 5 :: Views: 674
Can any one post the viva questions and answers for digital electronics lab.
The experiments are
1.half adder and full using NAND
2.binary to gray code converter
3.gray to binary code converter
4.BCD to Excees3 code converter
5.binary adder/subtractor and BCD adder using IC 7483
Electronic Elementary Questions :: 17.10.2010 11:09 :: atchutharam :: Replies: 6 :: Views: 10400
1. your comparator can either drive a chain of tapered inverter- also known as tapered buffer. That generally drives bigger loads with improvement in delay. If you wish to drive even larger load- try reading about Hidh Drive Buffer- i drove 1nF cap using that. But in your case- I guess tapered buffer should help you..
2. for jitter analysis- expo
Analog IC Design and Layout :: 08.05.2011 17:58 :: dhaval4987 :: Replies: 1 :: Views: 549
Hello all (First post on forum)
I understand that I have yet to contribute anything to this community and therefore you will be unlikely to help me, but I'm hoping someone will find it in their heart to offer assistance.
Basically I am revising for a University resit exam that's coming up for a Computer Systems module. For the most part, I can
Electronic Elementary Questions :: 10.08.2011 06:43 :: Swedish Rambo :: Replies: 4 :: Views: 504
1.Difference between MULTIPLEXER and ENCODER
2.What is DATA SELECTOR?(multiplexer)
3.Give advantages of mux,demux,encoder,decoder,magnitude comparator.
4.What are the minimization techniques available.
5.What is TTL and state its characteristics.
6.What are sequential circuits.Give example.
7.Difference between LATCH and FLIPFLOP.
Electronic Elementary Questions :: 01.11.2011 08:57 :: v.strawberry :: Replies: 1 :: Views: 1576
There will definitely be a problem, if you are using a continuously switching signal as a select.
You need to have a clock gating check performed at these points, and if you are getting a violation then you need to fix them before proceeding.
The clock gating check can be ignored only in the case when the select signal of the mux is stat
ASIC Design Methodologies and Tools (Digital) :: 01.07.2012 03:39 :: shobhit :: Replies: 14 :: Views: 1005
As we know, data multiplexing is often applied and two main implementation methods are prevalent in FPGA of Xilinx, say Spartan. They are BUFT and the combination of mux and LUT.
However, in practice, some expericense informs us that BUFT is not recommended due to its simulation mismatch and poorer performance. Also just for this, Synplify aut
Other Design :: 26.07.2002 04:32 :: Joyee :: Replies: 7 :: Views: 1734
iam trying to switch my clock while system running
I have used a mux as a concurrent statment so that when power up If FPGA see 1 on an I/o pin it selects clock source 1 and if it see 0 it will select source 2 ...
it's a very simple code and working correctly ..
entity switclock is
Port (c1,c2,mxcon : in std_logic ;
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.12.2003 09:06 :: Vonn :: Replies: 4 :: Views: 1961
some interview questions -
1. What is difference between signal and variable ?
2. How to write FSM in Moore/Mealy style ?
3. About sensitivity list for combinational amd sequential circuit
4.Design a COMBINATIONAL circuit that can divide the clock frequency by 2. write vhdl code...
6.Implement 3x8 decoder using 1x2 decoders..
ASIC Design Methodologies and Tools (Digital) :: 11.08.2005 06:21 :: barkha :: Replies: 3 :: Views: 3688
i have a couple of basic questions
1. How are swithes implemented in digital circuits. by switch i mean just a normal on/off connection (not a mux).. I know of one way which is by the use of transmission gates.. is there any other way
2. How does switching take place.. meanin. what is the power consumed for switching. . is it just the one
Electronic Elementary Questions :: 12.04.2005 06:43 :: abhigopal :: Replies: 8 :: Views: 1071
Need your opinion on synthesis. I need to do a Clock Tree Synthesis. Since my output signal is a pulse train and it is not a registered output. This signal goes to a combo logic (mux) before it?s goes out. Plus, this pulse train must sync with my main clock (posedge of sck).
Now, the questions are:
1. Do I need to do clock tree as we
ASIC Design Methodologies and Tools (Digital) :: 24.05.2005 21:06 :: no_mad :: Replies: 3 :: Views: 1267
i am in a cdr project and i have two questions:-
1- in dual loop cdr is the gm cell used with the phase detector is just a simple OTA , i cannot find any notes or what so ever about gm cell ,all i can find is about CP only, so if anyone have any knowledge about gm cells it will be great ,also if any pappers or books or... about gm cells
Analog IC Design and Layout :: 28.02.2006 11:24 :: safwatonline :: Replies: 3 :: Views: 840
I want to save a string/...
I'm not sure if I understand the requirement correctly ...
if you mean:
"i want to store 4/8/16/? bytes in a memory as a
parallel word and then read them out byte by byte"
- create a mux at the output of the memory;
- push byte by byte of your test word to a fifo usin
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.08.2008 04:51 :: j_andr :: Replies: 6 :: Views: 666
multiple gate offers choices for the synthesis tool. a mux can be implemented by and gates and inverters, but when a mux is present in the library, it will be efficient in terms of area, power, speed, as compared to a mux which is synthesized using and gate and inverters. Hence so many cells in the library.
ASIC Design Methodologies and Tools (Digital) :: 10.09.2008 04:50 :: avimit :: Replies: 4 :: Views: 811
I want to know the how a mux is synthesized...how to arrive at the depth of logic for, say, a 4-1 mux with sel. in general, given N inputs and M selects and 1 o/p, how do we arrive at logic levels.
thx in advance...
ASIC Design Methodologies and Tools (Digital) :: 12.08.2009 10:07 :: putra_sena :: Replies: 2 :: Views: 701
I have a statistical question about the application of clock enable signal. I want to know How many percent of applications connect the clock enable to a fixed active voltage level (and what are some of these applications?) and How many percent of applications connect the clock enable to a varying signal (and what are some of these
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2010 07:05 :: a.akbari61 :: Replies: 2 :: Views: 1973
I just looked at your code.
Please note that there is no difference between the following two blocks, with respect to functionality. Both are combinational logic which synthesized to two mux.
out1 <= sel1? I1: I0;
out2 <= sel2?out1:I3;
ASIC Design Methodologies and Tools (Digital) :: 26.07.2010 17:19 :: alaparthi :: Replies: 4 :: Views: 758
I would like to know your inputs on DFT PLanning needed for a new design partiularly
1. What flops to make scannable and which flops to avoid scannable
2. How to decide the number of chains?
3. Do we keep separate scan i/os or mux them with functional i/os? What would be the criteria for that?
4. How do we make sure that eac
ASIC Design Methodologies and Tools (Digital) :: 11.11.2010 17:47 :: raviram80 :: Replies: 17 :: Views: 1263
For your case use a digital mux (Multiplexer, aka Data selector) like, e.g. MC14051B (8 channels) or MC14519B (4*2 inputs / 4 outputs). Or 1 inverter and 2 NAND (or AND) gates.
Analog Circuit Design :: 11.04.2011 11:31 :: erikl :: Replies: 10 :: Views: 1741
I am in need of some good books that will teach you the tricks of the digital logic like implementing gates from mux etc and also some indepth digital electronics tricks
the book should teach me how to answer the questions in the following pages
Electronics hardware interview questions
Electronic Elementary Questions :: 13.04.2011 22:31 :: madhan_2005 :: Replies: 8 :: Views: 3689
the actual square root is 8 bits.
The other entity appears to be some sort of mux, I guess a load of muxes creates a square root.
Either way, its pretty poor VHDL code.
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.04.2011 07:11 :: TrickyDicky :: Replies: 5 :: Views: 587
My earlier post was reply to third post of the thiread where you have said "How can x-propgate when ports are given Low or High?"
Coming back to your original question :
Lets take a small example(mux module) :
There is a 2-bit select signal where valid combinations are : 00,01,10
and "11" is forbidden
Assume this submodule exists in
ASIC Design Methodologies and Tools (Digital) :: 28.05.2011 12:15 :: dcreddy1980 :: Replies: 17 :: Views: 1576
Test point insertion is related to make the unobservable or uncontrollable logic to make observable and controllable by adding a mux where the control signal is Test enable.
Test point insertion is not to add a flip flop please correct me if i am wrong.
DRC is design rule check i agree with you. Here i am talking about ATPG DRC.
My doubt is dur
ASIC Design Methodologies and Tools (Digital) :: 05.04.2013 05:25 :: lookthemoon2007 :: Replies: 3 :: Views: 321