1000 Threads found on edaboard.com: Noise And Zener
Phase noise and AM noise measurement in the frequency domain
RF, Microwave, Antennas and Optics :: 04-14-2003 09:15 :: HO_220 :: Replies: 0 :: Views: 1435
I have device with external charge pump and PLL circuits. The reference frequency is 20MHz. Waht cares have to be take to reduce phase noise and measure it.
RF, Microwave, Antennas and Optics :: 07-30-2003 00:25 :: brmadhukar :: Replies: 0 :: Views: 748
I am wondering why. Some publications just show the noise values from a hand calculation, not from the simulation. Why?? Are there any reasons? Because ".noise" cannot provide us a correct result like as ".fft" in SPICE? Or because hand calculation is enough to estimate it?
Regarding of noise, does (...)
Analog Circuit Design :: 01-06-2005 04:22 :: reltol1 :: Replies: 2 :: Views: 1513
Why not try spectre of Cadence, the new version of spectre even display jitter directly in Pnoise simulation
Analog Circuit Design :: 03-13-2005 23:39 :: linxf2003 :: Replies: 5 :: Views: 1917
I don't know how to simulate kickback noise and error rate of Flash AD converter.
Could any body help me?
Analog Circuit Design :: 05-02-2005 08:53 :: Lantis :: Replies: 1 :: Views: 870
who can give me some papers or books for low noise and high PSRR BandGAP?
Analog Circuit Design :: 08-02-2005 05:42 :: jake :: Replies: 6 :: Views: 1780
I have several questions about noise in communication system, anyboday
can help me?
In communication system, thermal noise is amplitude noise?phase noise?
or both? How do I look it as?
What kind of physical noise like thermal noise, shot noise is modeled by (...)
Digital Signal Processing :: 08-20-2005 04:02 :: GDF :: Replies: 6 :: Views: 2073
how to check phase noise and jitter in cadence of the whole pll system. i have checked phase noise of vco seperatly. should i do same pss and pnoise simulation for pll also or is there any other mean to measure it.
Analog Circuit Design :: 11-24-2005 02:35 :: us1710 :: Replies: 0 :: Views: 1021
i need help!
how to simulate a gaussian noise and selective frequency fading channel in CDMA system?
please give me some reference book in this field
Digital communication :: 03-28-2006 04:50 :: hai chau :: Replies: 2 :: Views: 2037
I assume that you want to built a ohmeter with an audio indication of the resistance. Connecting long probes to the inverting input of the opamp can cause the effect that you mention. The best way to measure a resistance is with a current source in order to avoid noise and instability. You can improove your circuit by inserting a rather large resis
Analog Circuit Design :: 03-30-2006 02:54 :: ptmsl :: Replies: 2 :: Views: 1340
can anyone help me finding the models of calculation of 'man made noise' and 'sky noise'.
RF, Microwave, Antennas and Optics :: 04-03-2006 00:40 :: eelinker :: Replies: 0 :: Views: 544
how to reduce the noise and increase the power and current for an audio mixer? how can we enhance a basic audio mixer?
Analog Circuit Design :: 07-27-2006 23:18 :: zesty_q :: Replies: 0 :: Views: 553
if you want to using this LDO for RF VCO/PLL, I suggest that u must care the 1~100kHz output noise which will affect the close-in noise about pll/vco. It's really really true, but I don't think the MAXIM's 60uV is enough.
Analog IC Design and Layout :: 12-09-2006 04:47 :: hanjiemy :: Replies: 4 :: Views: 1060
The phase noise proportional to the oscillation frequency , and so , inverse proportional to capacitance, also, for tail current source, you concern with the currnet noise and so , increasing its gm will increase its thermal noise,, also, for the cross-coupled pairs , you concerned with input (...)
Analog IC Design and Layout :: 11-01-2006 02:29 :: husseinadel :: Replies: 8 :: Views: 1687
Can any1 tell me the relation between KT/C noise and resolution of ADC for a SAR ADC ?
Analog Circuit Design :: 07-11-2007 07:46 :: raghu_eee :: Replies: 0 :: Views: 739
Can any1 tell me the relation between KT/C noise and resolution of ADC for a SAR ADC ?
Analog Circuit Design :: 07-11-2007 08:24 :: raghu_eee :: Replies: 0 :: Views: 584
in this relation for thermal noise (or resistor noise or jahnson,...):
I want the reason of that 4 as coeffecient.where does that 4 come from? or why?
consider a V source as the source of noise and a series resistor.(may help)
RF, Microwave, Antennas and Optics :: 10-08-2007 03:44 :: sadid :: Replies: 1 :: Views: 497
How noise is different from distortion
Digital Signal Processing :: 05-03-2008 02:50 :: mohsin677 :: Replies: 7 :: Views: 7890
""Consider a cellular system operating at 900. Suppose that for acceptable voice quality a signal-to-noisepower ratio of 15 dB is required at the mobile. Assume the base station transmits at 1 W and its antenna hasa 3 dB gain. There is no antenna gain at the mobile and the receiver noise in the bandwidth of (...)
Digital communication :: 03-14-2010 01:07 :: moonnightingale :: Replies: 0 :: Views: 870
how to measure the phase noise and jitter of Voltage Controled Oscillator(VCO) using Hspice tool.
Analog Circuit Design :: 05-29-2010 10:47 :: Pardeep duhan :: Replies: 0 :: Views: 714
I am a undergrad student and doing a project about Power Supply using
Op-amp and zener Diode.beside, I need to prepare a ~25 mins presentation on this topics.
Could anyone gives me some advices about the topic?
any typical examples on this topics?
or any applications based on this type of power supply?
Analog Circuit Design :: 10-06-2010 23:41 :: keung56 :: Replies: 0 :: Views: 1037
The noise terms are confusing me in cadence,such as input noise and equvalient input noise,,output noise and equvalient output noise,who can tell the difference between them?
What is the meaning of squared output(input )noise?
I also have a (...)
Analog IC Design and Layout :: 01-03-2011 21:05 :: afujian :: Replies: 2 :: Views: 796
now i am looking for this paper, pls upload it for me if u have. many thanks
"Delta-sigma A/Ds with reduced sensitivity to opamp noise and gain"
Analog Circuit Design :: 03-16-2011 00:52 :: wonbef :: Replies: 1 :: Views: 471
hi everyone,im going to do device noise analysis for the sigma delta adc in cadence tool and hence optimizing the design in noise and also in power.please help me with your ideas and suggest any useful books or papers on noise optimization for each of the blocks in sigma delta adc or any (...)
Analog IC Design and Layout :: 06-19-2011 15:45 :: deepthi yamaka :: Replies: 0 :: Views: 460
I have a look on people's matlab on BPSK BER over rayleigh channel.
I don't understand why noise and channel are the same as shown below. so rayleigh channel is the same as noise then?
Can anyone explain it to me please.
Digital communication :: 06-27-2011 12:04 :: mazdaspring :: Replies: 2 :: Views: 1753
Does anyone know how to get the RMS output noise and input dynamic range
of a transimpedance amplifier using cadence or synopsys?
Please help me. I don't have any idea on how to get it..
Analog Circuit Design :: 03-21-2012 11:24 :: aprilyne :: Replies: 0 :: Views: 374
noise reduction is equal to the square root of no. of samples taken.
for more details and mathematical analysis read the
Professional Hardware and Electronics Design :: 03-07-2013 05:01 :: apolama :: Replies: 1 :: Views: 312
in QPSK system:
what are the matlab equations for noise and fading channel?
what is the theoritical equation for calculating BER?
this is because I see several different formula, for example:
N0 = 1/10^(SNR(i)/10);
n = sqrt(N0/2)*(randn(1,length(sig))+1i*randn(1,length(sig)));
h = (...)
Digital communication :: 04-22-2013 16:14 :: barznjy :: Replies: 2 :: Views: 567
1.Can anybody comment on the difference between the forward characteristics of an ordinary diode and zener diode?
2. What is the meaning of breakdown? Does it mean the diode has been destroyed?
Electronic Elementary Questions :: 07-29-2013 10:24 :: gurpreetbrar :: Replies: 4 :: Views: 940
I have VERY LIMITED experience in SAR ADC design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
Analog IC Design and Layout :: 07-10-2014 22:31 :: diodelite :: Replies: 0 :: Views: 147
hi to all,
i am doing a project on 8051 which includes the controlling of the 12v DC motor using a relay......
so i need to a help in reducing the noise and back emf which is generated by the DC motor......
Microcontrollers :: 02-15-2013 08:45 :: jjeevan007 :: Replies: 7 :: Views: 829
Nois Figure is the Signal to noise ratio auf the Output of a two port divided by the Signal to noise Ratio on the input. I.e. the noise figure tells you how much noise the four port added.
The (equivalent) noise temperature is related to the latter. Your two-port-box (an amplifier for example) adds a (...)
RF, Microwave, Antennas and Optics :: 05-14-2003 12:05 :: harkonnen :: Replies: 4 :: Views: 2022
I TRY TO LEARN ADS2003,THERE IS PROBLEM IN PLOTTING GAIN and noise CIRCLES AFTER I MODIFY IN THE meas eqn,there is no plotting ,i.e. s circles invalid,here thethe design file and the error message,pls giude me
Electromagnetic Design and Simulation :: 04-17-2004 00:18 :: abdoeng :: Replies: 3 :: Views: 1014
ATF36077 is conditionlly stable how i plot nise and gain circles
Refer to the figure, from component palette list, under S-parameter simulation, there is gain circle and noise circle option, detail of usage, plese check out the help file... it is hard to explain everything here...
RF, Microwave, Antennas and Optics :: 04-18-2004 11:07 :: activewei :: Replies: 1 :: Views: 1409
As we know PA has noise circle and gain circle,
but in your practical experience, is it impractical to consider it and just use the try and error method?
RF, Microwave, Antennas and Optics :: 09-28-2004 10:46 :: rhjang :: Replies: 2 :: Views: 950
I'm going to use an AVR microcontroller (ATMEGA16) in a board that must work in a noisy environment with high EMI noise (beside the 3-phase motors), but I'm not sure that AVR can work in such places. Now, can I use it with no problem?
Microcontrollers :: 11-22-2004 00:25 :: madjid :: Replies: 4 :: Views: 3000
I know there are shot noise, thermal noise and 1/f noise in the CMOS transistor. CMOS has the saturation and linear region. Is the noise model same in these two regions? Or the noise model is available in the saturation region only?
RF, Microwave, Antennas and Optics :: 02-28-2005 08:20 :: wccheng :: Replies: 8 :: Views: 1926
Do anyone know what's the meaning of "fn" and "id", which is related to the noise of MOSFET (model used: bsim3v3)?
I have thinking that probably "fn" is the flicker noise and "id" is the thermal noise components. But I don't think there is so much flicker noise in the design (it is an (...)
Analog IC Design and Layout :: 03-07-2005 01:25 :: terryssw :: Replies: 2 :: Views: 1926
Low noise and Low distortion are two different concepts. Distortion is mostly controlled by how your output drivers are driving. Low noise requires more bulkier input differential pair. But there is one common thing, between the two conditions. We need to have ample current in each branch in the circuit. That reduces the (...)
Analog Circuit Design :: 04-14-2005 04:49 :: Vamsi Mocherla :: Replies: 3 :: Views: 624
My question is which of the Current and Voltage is more immune to noise specialy at dc mode for BJT?
Analog Circuit Design :: 04-28-2005 17:00 :: tufan :: Replies: 0 :: Views: 560
I have a small question that might be a silly one;
What's the difference between the voltage regulators and zener diodes.???
I mean the difference in the function. They both used to sustain the voltage at a certain level.
Thanks for answering my silly questions.
Electronic Elementary Questions :: 05-06-2005 23:29 :: seadolphine2000 :: Replies: 8 :: Views: 6555
Hspice RF compute iip3, NF, phase noise and ....
but i want user manual of it .
Do you have any solution to compute iip3 and noise figure in hspice 2003.
can you help me?
Analog Circuit Design :: 07-28-2005 03:01 :: hr_rezaee :: Replies: 5 :: Views: 1459
Hi, could anyone please provide some materials on dc offset of transistor pair in weak inversion and the thermal noise, 1/f noise of transistors in weak inversion as well? I could only find information on current mismatch of current mirrors in weak inversion from IEEExplorer. Thank you.
Analog Circuit Design :: 09-02-2005 04:08 :: pseudockb :: Replies: 0 :: Views: 848
I think this is correct? For higher frequencies, the flicker noise is negligible and the noise of the transistor is dominated by thermal noise. So for most circuits, the pmos noise IS lower
Analog Circuit Design :: 09-23-2005 18:12 :: orbb :: Replies: 7 :: Views: 1547
Insert a voltage source into the loop. The voltage source is used to break the loop in stb analysis.
Output noise can be converted into an equivalence of input noise. and input noise can be converted into an equivalence of output noise too.
I need help with the Stability analysis and (...)
Analog IC Design and Layout :: 06-07-2011 22:57 :: leo_o2 :: Replies: 9 :: Views: 2376
How to simulate the noise performance using Hspice ? When I run transient analysis in Hspice , can I view the noise from the waveform ?
Analog Circuit Design :: 10-15-2005 08:42 :: xwcwc1234 :: Replies: 10 :: Views: 2284
Analog design is full of different trade-offs. In my view, you can not say which process is better until you design the circuit in both technologies and see which one is less noisy. What I can say from basic formulas of noise in CMOS technologies is that, usually by scaling the noise of the process will increase. For example, thermal (...)
Analog IC Design and Layout :: 12-02-2005 12:05 :: OpAmp :: Replies: 2 :: Views: 755
Smaller aspect ratio with minimal gate length, L, ensures lower flicker noise.
Analog IC Design and Layout :: 01-02-2006 21:09 :: hrkhari :: Replies: 12 :: Views: 1784
I mean if Pll output signals are fed into a power amplifier , and we test it at the output of the PA, will phase noise of PLL and gain be a tradeoff?
RF, Microwave, Antennas and Optics :: 02-22-2006 22:42 :: bigworm :: Replies: 2 :: Views: 560
For a conventional PLL, integer-N and 2nd loop filter.
If I reduce the charge pump current and modify the loop filter to maintain
the same loop bandwidth. All other components are the same. The phase noise
will be improved or degraded? Why?
Let's discuss this in two aspects, in band and (...)
Analog IC Design and Layout :: 03-08-2006 04:01 :: hebu :: Replies: 0 :: Views: 1492