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Phase noise and AM noise measurement in the frequency domain
Hi I have device with external charge pump and PLL circuits. The reference frequency is 20MHz. Waht cares have to be take to reduce phase noise and measure it. Madhukar
I am wondering why. Some publications just show the noise values from a hand calculation, not from the simulation. Why?? Are there any reasons? Because ".noise" cannot provide us a correct result like as ".fft" in SPICE? Or because hand calculation is enough to estimate it? Regarding of noise, does (...)
Why not try spectre of Cadence, the new version of spectre even display jitter directly in Pnoise simulation
I don't know how to simulate kickback noise and error rate of Flash AD converter. Could any body help me? Thanks
who can give me some papers or books for low noise and high PSRR BandGAP?
I have several questions about noise in communication system, anyboday can help me? 1) In communication system, thermal noise is amplitude noise?phase noise? or both? How do I look it as? 2) What kind of physical noise like thermal noise, shot noise is modeled by (...)
how to check phase noise and jitter in cadence of the whole pll system. i have checked phase noise of vco seperatly. should i do same pss and pnoise simulation for pll also or is there any other mean to measure it.
addition of guassion noise and fading simulation is generic to and type od signal . you need to generate random noise either by command or in simulink . also by adding delayed ( by particular amount of samples) version of the signal in original signal you can also see the multipath fading (...)
I assume that you want to built a ohmeter with an audio indication of the resistance. Connecting long probes to the inverting input of the opamp can cause the effect that you mention. The best way to measure a resistance is with a current source in order to avoid noise and instability. You can improove your circuit by inserting a rather large resis
can anyone help me finding the models of calculation of 'man made noise' and 'sky noise'.
how to reduce the noise and increase the power and current for an audio mixer? how can we enhance a basic audio mixer?
if you want to using this LDO for RF VCO/PLL, I suggest that u must care the 1~100kHz output noise which will affect the close-in noise about pll/vco. It's really really true, but I don't think the MAXIM's 60uV is enough.
AA The phase noise proportional to the oscillation frequency , and so , inverse proportional to capacitance, also, for tail current source, you concern with the currnet noise and so , increasing its gm will increase its thermal noise,, also, for the cross-coupled pairs , you concerned with input (...)
Can any1 tell me the relation between KT/C noise and resolution of ADC for a SAR ADC ?
Can any1 tell me the relation between KT/C noise and resolution of ADC for a SAR ADC ?
in this relation for thermal noise (or resistor noise or jahnson,...): N=4RkTRB I want the reason of that 4 as coeffecient.where does that 4 come from? or why? consider a V source as the source of noise and a series resistor.(may help)
Hi noise is external signal which affects your signal, it's not correlated to your signal While distortions is deformation of your signal. distortion may be due to power supply limitations , non linearity ,band limited filters Salam Hossam Alzomor www(.)i-g(.)org
""Consider a cellular system operating at 900. Suppose that for acceptable voice quality a signal-to-noisepower ratio of 15 dB is required at the mobile. Assume the base station transmits at 1 W and its antenna hasa 3 dB gain. There is no antenna gain at the mobile and the receiver noise in the bandwidth of (...)
how to measure the phase noise and jitter of Voltage Controled Oscillator(VCO) using Hspice tool. with regards pardeep kumar
I am a undergrad student and doing a project about Power Supply using Op-amp and zener Diode.beside, I need to prepare a ~25 mins presentation on this topics. Could anyone gives me some advices about the topic? any typical examples on this topics? or any applications based on this type of power supply?
Hi all, The noise terms are confusing me in cadence,such as input noise and equvalient input noise,,output noise and equvalient output noise,who can tell the difference between them? What is the meaning of squared output(input )noise? I also have a (...)
hi,all: now i am looking for this paper, pls upload it for me if u have. many thanks "Delta-sigma A/Ds with reduced sensitivity to opamp noise and gain"
hi everyone,im going to do device noise analysis for the sigma delta adc in cadence tool and hence optimizing the design in noise and also in power.please help me with your ideas and suggest any useful books or papers on noise optimization for each of the blocks in sigma delta adc or any (...)
I have a look on people's matlab on BPSK BER over rayleigh channel. I don't understand why noise and channel are the same as shown below. so rayleigh channel is the same as noise then? Can anyone explain it to me please. noise=1/sqrt(2)*(randn(1,N)+1i*randn(1,N)); (...)
hello! Does anyone know how to get the RMS output noise and input dynamic range of a transimpedance amplifier using cadence or synopsys? Please help me. I don't have any idea on how to get it..
noise reduction is equal to the square root of no. of samples taken. for more details and mathematical analysis read the
Hi, in QPSK system: what are the matlab equations for noise and fading channel? also; what is the theoritical equation for calculating BER? this is because I see several different formula, for example: 1- N0 = 1/10^(SNR(i)/10); n = sqrt(N0/2)*(randn(1,length(sig))+1i*randn(1,length(sig))); h = (...)
1.Can anybody comment on the difference between the forward characteristics of an ordinary diode and zener diode? 2. What is the meaning of breakdown? Does it mean the diode has been destroyed?
I have VERY LIMITED experience in SAR ADC design. Would you tell me how to tackle the noise and to estimate the resolution of the comparator? Thanks
hi to all, i am doing a project on 8051 which includes the controlling of the 12v DC motor using a relay...... so i need to a help in reducing the noise and back emf which is generated by the DC motor...... regards jjeevan
Nois Figure is the Signal to noise ratio auf the Output of a two port divided by the Signal to noise Ratio on the input. I.e. the noise figure tells you how much noise the four port added. The (equivalent) noise temperature is related to the latter. Your two-port-box (an amplifier for example) adds a (...)
I TRY TO LEARN ADS2003,THERE IS PROBLEM IN PLOTTING GAIN and noise CIRCLES AFTER I MODIFY IN THE meas eqn,there is no plotting ,i.e. s circles invalid,here thethe design file and the error message,pls giude me
ATF36077 is conditionlly stable how i plot nise and gain circles regards Refer to the figure, from component palette list, under S-parameter simulation, there is gain circle and noise circle option, detail of usage, plese check out the help file... it is hard to explain everything here...
As we know PA has noise circle and gain circle, but in your practical experience, is it impractical to consider it and just use the try and error method? Best regards.
Hi, I'm going to use an AVR microcontroller (ATMEGA16) in a board that must work in a noisy environment with high EMI noise (beside the 3-phase motors), but I'm not sure that AVR can work in such places. Now, can I use it with no problem?
Dear all, I know there are shot noise, thermal noise and 1/f noise in the CMOS transistor. CMOS has the saturation and linear region. Is the noise model same in these two regions? Or the noise model is available in the saturation region only? Best Regards, wccheng
Do anyone know what's the meaning of "fn" and "id", which is related to the noise of MOSFET (model used: bsim3v3)? I have thinking that probably "fn" is the flicker noise and "id" is the thermal noise components. But I don't think there is so much flicker noise in the design (it is an (...)
Dear wonbef, Low noise and Low distortion are two different concepts. Distortion is mostly controlled by how your output drivers are driving. Low noise requires more bulkier input differential pair. But there is one common thing, between the two conditions. We need to have ample current in each branch in the circuit. That reduces the (...)
DEAR friends My question is which of the Current and Voltage is more immune to noise specialy at dc mode for BJT?
Hi,.. I have a small question that might be a silly one; What's the difference between the voltage regulators and zener diodes.??? I mean the difference in the function. They both used to sustain the voltage at a certain level. What else.??? Thanks for answering my silly questions.
Hspice RF compute iip3, NF, phase noise and .... but i want user manual of it . Do you have any solution to compute iip3 and noise figure in hspice 2003. can you help me?
Hi, could anyone please provide some materials on dc offset of transistor pair in weak inversion and the thermal noise, 1/f noise of transistors in weak inversion as well? I could only find information on current mismatch of current mirrors in weak inversion from IEEExplorer. Thank you.
I think this is correct? For higher frequencies, the flicker noise is negligible and the noise of the transistor is dominated by thermal noise. So for most circuits, the pmos noise IS lower
Insert a voltage source into the loop. The voltage source is used to break the loop in stb analysis. Output noise can be converted into an equivalence of input noise. and input noise can be converted into an equivalence of output noise too. I need help with the Stability analysis and (...)
How to simulate the noise performance using Hspice ? When I run transient analysis in Hspice , can I view the noise from the waveform ?
hi, I have a question on the relatioonship between the noise characteristcs and the cmos process scaling. I intend to design a TIA(155M) and 0.6um and 0.35um mixed cmos process are availble. I just want to know, from the view of noise improvement, which process is better? Scaled process means better or (...)
Smaller aspect ratio with minimal gate length, L, ensures lower flicker noise. Rgds
I mean if Pll output signals are fed into a power amplifier , and we test it at the output of the PA, will phase noise of PLL and gain be a tradeoff? thank you
For a conventional PLL, integer-N and 2nd loop filter. If I reduce the charge pump current and modify the loop filter to maintain the same loop bandwidth. All other components are the same. The phase noise will be improved or degraded? Why? Let's discuss this in two aspects, in band and (...)

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