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Noise Simulation Adc

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23 Threads found on edaboard.com: Noise Simulation Adc
In the standard noise simulation, ideal resistor noise (calculated from its resistance value) is included (there may be an option to select/deselect it). Same is true for all the devices, if their models include the corresponding parameters.
Hi all, I am trying to simulate an adc on verilog-A, using MOSFET models generated from TCAD tools. In order to quantify adc performance in terms of SNR etc. I need to include noise in my simulations too. Can someone help to identify where I can include noise sources in the simulation (...)
If you just wanna know thermal/flicker noise for most linear circuits, you could simply use "noise" simulation. I'm afraid that DFT is just for the simulation of quantization noise for sampling circuits.
hi all, i have design a sigma delta adc. the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine. if the veriloga sw be changed to cmos-sw, the dc noise peak arise, & independent of fft point number. the 1/R_sw/C_s ~= 6*(2*pi*f_sample). my english is very poor, thanks for your help!! Add
It is actually possible, in simulation with no mismatch, to achieve such a result especially if your THA and comparator are much faster or more accurate than required by optimal design. You should try a monte-carlo run and see what happens. Your measured results will, of course be worse than that! Of course, if you add noise you will get worse
Hi, Can any one help in doing in noise simulation of SC integrator - part of a incremental sigma-delta adc? Any good reference or simulation type details will help a lot. Thanks Sanku
in pipelined adc,such as 1.5-bit-per-stage,if there is no front end S/H,then the main source of thermal noise is the KTC noise;in simulink behavioral simulation,in order to take KTC noise into consideration,we can add a noise submodel into the ideal model of every stage,just as the below (...)
Hello, I want simulate my first first order delta sigma adc, attached schematic. I can simulate it and I see behind the LP again my input signal. My problem is I cant see the noise shift to higher frequency. I simulate transient and adjust transient noise (noisefmin noisefmax and (...)
also noise (but i don't think you put it into your simulation), ron of switches, clock feedthrough or charge injection, lousy cm-feedback of the opamp. Also saturation of the opamp, limited gbw, sr, finite gain, ...
I am running into a problem when I was trying to simulate my DSadc in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about
I am running into a problem when I was trying to simulate my DSadc in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about
Hi, Ask your question briefly and clearly. When you want to consider nonideal effects, try entering the factors one by one, not all of them simultaneously. This helps you to find the problem better. How do you consider the KT/C noise in the system?
It's hard to include random noise in SPICE simulation. But you can try verilog-a/ams for evaluating their impact on adc performance.
HI all i am simulation a pipeline adc. I give a sine input, and do .tran simulation in hspice. Then catch the 10-bit digital code to do fft in matlab. Then i want to know, the fft results can give the SNR results? And is the noise compont included in the tran simulation results? What (...)
hi neoflash, Yes you are right. They find the ENOB from Signal to noise and Distortion ratio SINAD of the T/H circuit to determine its linearity.
Hi Everyone, I have just designed a 8-bit folding interpolation adc. When I simulate my adc, I cannot get to 8-bit of resolution. The SNR that I got from the power spectrum is only -30dB. The noise level is at -40dB. Is there any technique I can use to lower the noise level in the adc. Can anyone who has (...)
just pass a single tone and measure its power. The amplitude in other bins give noise
jswei303, You are talking about measurement or simulation results ? Because if it is measurements, what you see can be caused the noise - even if you put a perfect DC voltage at the input of an adc, you'll see different codes coming out, from sample to sample.
Hi, all I have designed a 3 order sigma delta SDM. after the chip come back. the second order harmolic distortion is -70db, and the noise floor is about -100db, How can I to reduce the second order harmolic distortion. Best regards Crossbow
for noise analysis such as SNR, you should use RF simulator. for distortion analysis, just general trans simulation and do FFT is enough.
We design chip in which input signal is chopped at 4Khz. After amplification this signal is manipulated in adc with sampling frequncy 1MHz. I have simulation results ( on PSpice) for the noise at 4KHz and 1MHz. My question is: Is there any rule to calculate (on the base of the noise at both frequncyies), the real (...)
I ever use hspice behavior write a "idea D/A convert" for simulation DNL/INL .. but too idea and I ever try use add "gitter noise" in clock ..but not work
How do people estimate the effect of sampling switches noise on a cirсuit level? I was doing long transient simulations, than FFT and finally got PSD from which I could get the SNR and estimate SFDR. However it seems that transistor noise source are not included in transient analyses and Matlab behavioral (...)