246 Threads found on edaboard.com: Nor Not
The loop is a bit misdrawn, and the scheme would require
you to know the generator's internal voltage amplitude
or the 10K resistor's current (which is not shown to be
measured, nor the added series resistance of doing that).
If your signal generator is the normal 50 ohms then what
you measure at the 10Kohm resistor owes more to the (...)
Analog Circuit Design :: 03-30-2017 08:13 :: dick_freebird :: Replies: 3 :: Views: 272
I need some help in identifying a component i found in the board.
Its a 6-pin IC.
It seems to be heart of my Industrial Timer.
I am not able to collect any data about this whatsoever, nor can i find any datasheet...
If any one can help me in finding this or something similar...could do huge favors.
Plz revert here...
I have also
Analog Circuit Design :: 03-14-2017 06:08 :: electronika.design :: Replies: 3 :: Views: 324
Your picture doesn't give us any information. nor does your text. But I might guess that you've got off-grid objects.
Software Problems, Hints and Reviews :: 02-08-2017 17:18 :: barry :: Replies: 1 :: Views: 371
Give me an idea to solve thisI am really puzzled trying to understand how someone expect to have some help without posting any code nor schematic diagram.
Microcontrollers :: 11-24-2016 16:07 :: andre_teprom :: Replies: 7 :: Views: 406
Hi I got cadence IC616 and MMSIM13 from and installed it successfully and also applyed the patch successfully but it does not have license.dat file neither in IC616/share/license nor in MMSIM13/share/license
I request you pls share the license file or email me
Linux Software :: 11-19-2016 04:55 :: Aradhna :: Replies: 0 :: Views: 4
Without further information, it's a pretty useless post.
So far, you have written legal C code which can work in any C enviroment. But we neither know what writeMAX6955() does nor how the msg parameter is actually supplied in your program.
I feel that the below Forum rules quote describes the information content of your post quite well
Microcontrollers :: 10-30-2016 09:29 :: FvM :: Replies: 9 :: Views: 345
Some gates invert their output.
A dual input "OR" gate like a CD4071: with either or both inputs high, the output will be high.
A dual input "nor" gate like a CD4001: with either or both inputs high, the output will be low.
The difference is the nor inverts the output. There are also AND and NAND gates.
You do not need a resistor to ground, (...)
Elementary Electronic Questions :: 10-01-2016 15:40 :: Audioguru :: Replies: 20 :: Views: 1000
There isn't any model for such circuits for neither ADS nor any.Its' characteristics are defined and you take it, use it.
RF, Microwave, Antennas and Optics :: 08-23-2016 14:59 :: BigBoss :: Replies: 3 :: Views: 437
1. Difference between qualitative and quantitive analysis? If we want to perform these for any electronics circuit
qualitative: data are not calculated nor simulated nor measured; they are estimated - at best; quantitative analysis: data are calculated, simulated or measured.
Elementary Electronic Questions :: 07-30-2016 14:48 :: erikl :: Replies: 1 :: Views: 404
The thread sounds confused. You are apparently reporting a violation of harmonic or spurious emission requirements ("radiation measurement"). It's neither related to receiver sensitivity nor transmitter output power, at least not directly.
You did however not tell at which frequency the limit values have been exceeded. Neither information (...)
RF, Microwave, Antennas and Optics :: 07-30-2016 11:44 :: FvM :: Replies: 23 :: Views: 990
I would like to build the clock tree with NAND/nor gates. As we know these gates are universal gates, so we can build BUF/INV logic with these gates.
If anyone of you have idea about this concept, please let me know.
I don't bother about the performance, just I want to build the clock tree.
I am trying to build with EDA tools present in m
ASIC Design Methodologies and Tools (Digital) :: 05-20-2016 10:44 :: rajasekhar.347 :: Replies: 5 :: Views: 452
i have been trying to run cst solver through matlab, but it just wont work nor it shows any error. the following code is being used:
Electromagnetic Design and Simulation :: 03-28-2016 08:22 :: yattharth :: Replies: 1 :: Views: 509
I don't think that one of the FFT belong to the top diagram signal.
I can neither see signal amplitudes, nor frequencies, nor overtones.
Digital Signal Processing :: 03-13-2016 00:38 :: KlausST :: Replies: 7 :: Views: 3263
OK. Pulse frequency modulation, pulse width modulation, amplitude modulation, frequency modulation...
-No expected reflections nor interference-
What about the receivers for them ? Any links where to learn ?
RF, Microwave, Antennas and Optics :: 02-20-2016 15:07 :: Externet :: Replies: 4 :: Views: 444
There is not a model for the PIC18F97J60 for Proteus nor is there ever likely to be as it would be very expensive to produce.
I hope that in the future that Labcenter will produce models for some of the newer processors, but I am not holding my breath.
The best available PIC18F processor in Proteus is the PIC18LF47J53 this maybe good (...)
PC Programming and Interfacing :: 02-03-2016 01:16 :: pjmelect :: Replies: 1 :: Views: 882
A HCMOS crystal oscillator is designed to drive digital circuits with high input impedance. It's rather intended to drive low R/high C loads, nor to achieve specific "analog" waveforms.
Analog Circuit Design :: 01-31-2016 11:32 :: FvM :: Replies: 11 :: Views: 613
I was working on my project with logic, sequential and combinational ICs.
And, wanted to test the 74LS10 3-input NAND gate and it wasn't working!!
All other ICs are working, nor, 2-input NAND, counter, 555 timer.
I've other 74LS10, if they all not working then I'd combine 2-input NAND and one AND gates to get 3-input NAND gate.
I just w
Elementary Electronic Questions :: 01-21-2016 12:03 :: eagle1109 :: Replies: 4 :: Views: 387
i could not able to write in addr 2049, only 0-2048 addr is aces sable in ccs driver
Good joke. How can a 2kx8 memory have addresses 2048 or 2049? Neither Standard EE24C16 nor FM24C16B has.
Microcontrollers :: 11-21-2015 09:36 :: FvM :: Replies: 9 :: Views: 881
The answer you find in the datasheet.
We don't know microcontroller type, nor it's periferals, nor it's supply voltage, not the load current at the IO....
So it is impossible for us to give a good answer.
Microcontrollers :: 11-17-2015 06:43 :: KlausST :: Replies: 3 :: Views: 312
It's not readily available, nor is it cheap. But if you have a large research budget, ask Dr. Pekka Ikonen, Head of Strategic Marketing at TDK-EPC
RF, Microwave, Antennas and Optics :: 08-18-2015 02:53 :: SunnySkyguy :: Replies: 3 :: Views: 625
we can neither check your hardware nor check your code, as long as you don´t post it.
So I´ve googled and found a lot of "how to use GY80" guidelines. Did you read them?
Please provide more information.
Microcontrollers :: 08-14-2015 14:44 :: KlausST :: Replies: 14 :: Views: 1191
you do not tell us how long the interconnecting transmission line is, nor how much amplitude ripple you can live with over a bandwidth.
If they are really close, just hook one to the other. If they are far apart, you could add a series resistor at the mixer, and run 75 ohm line.
if it is narrowband, you could just run 50 ohm line from the
RF, Microwave, Antennas and Optics :: 07-22-2015 10:48 :: biff44 :: Replies: 3 :: Views: 608
not knowing your technology nor your DRC rules, I 'd assume:
You have N_WELLs WITH DIFFERENT POTENTIAL in your layout. Seems - in your technology - that N-Wells have to be marked (e.g.) by a DNW_LV_MARK marking layer. But there must be different DNW_LV_MARK marking layer polygons for N_WELLs WITH DIFFERENT POTENTIAL. And these have
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-07-2015 12:42 :: erikl :: Replies: 2 :: Views: 574
you don't say it is video or stills
nor if it color or B/W
BUT if you need to do 1) and especially 3) as well you definitely can not use a wee micro-controller, you need a full-blown PC.
Embedded Linux and Real-Time Operating Systems (RTOS) :: 07-06-2015 05:48 :: kam1787 :: Replies: 2 :: Views: 809
1. I'm simulating 8 bit mips processor from CMOS VLSI DESIGN: 4th Edition. This is results that I obtained for Astro and VCS using Synopsys. I've no problem with Astro but for VCS simulation, at the first instruction, the result is ok but when it proceeds to second instruction, there is something which I not quite understand. Why the me
ASIC Design Methodologies and Tools (Digital) :: 06-22-2015 04:47 :: deepsetan :: Replies: 0 :: Views: 351
I do not hold solder in my teeth nor with my toes.
instead I fasten down the item I am soldering and hold the solder in one hand and the soldering iron in the other hand, or I fasten down the solder and hold the item to be soldered in one hand and the soldering iron in the other hand.
Some handicapped people have only one hand and they have no prob
Elementary Electronic Questions :: 05-30-2015 15:44 :: Audioguru :: Replies: 7 :: Views: 581
Your photo-diode is not a current nor a voltage source because it is reverse biased. Then light on it causes it to leak and become a resistance. Then it conducts some of its bias to the opamp input.
A photo diode without bias is a tiny solar cell that does generate a voltage and a current.
Analog Circuit Design :: 05-28-2015 00:02 :: Audioguru :: Replies: 4 :: Views: 666
You're right: this cascode circuit is not very temperature (nor supply voltage) stable. But at least Q1's Vc will stay 1*Vbe below Q2's Vb.
The Figure 2.24 text just says the current stability referred to load changes is improved (compared to a simple constant current source).
This is true, because the cascode transistor Q2 (in base mod
Analog Circuit Design :: 04-16-2015 16:52 :: erikl :: Replies: 1 :: Views: 552
Standard core voltage for a 180nm process is 1.8V. Usable voltage may range from 0.9 to 2.5V, depending on the foundry's specification. It does not depend on any model type nor EDA tool label.
Analog Circuit Design :: 01-14-2015 19:01 :: erikl :: Replies: 3 :: Views: 763
I'm trying to do this in schematic, may be this is not possible in the schematic?
Right. In schematics no vias (nor layers) are used. Just wires to connect schematic symbols.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-08-2015 19:16 :: erikl :: Replies: 4 :: Views: 655
Lets put it this way: Xilinx does not provide tools that can convert a .bit file back to a netlist, nor does any other vendor.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-06-2014 13:55 :: mrflibble :: Replies: 1 :: Views: 829
The everyday way to measure power is to connect various resistance loads. Measure the volts and amps delivered. notice that maximum power is not always achieved at maximum volts, nor is maximum power always achieved at maximum amperes.
Since you have two fixed voltages, you should test the total power when (a) both are powering loads, and (...)
Power Electronics :: 11-21-2014 02:43 :: BradtheRad :: Replies: 2 :: Views: 1022
I am developing a system that needs to work with nor FLASH PC28F128P33T85 Numonyx .
My codes are in assembly and following is some sample of the codes.
When i write and then read , it has not been written to the location.
Anybody can help me? any experiences is need on 28F128 Series nor Flashes.
Datasheet is the way i have a
Digital Signal Processing :: 10-30-2014 07:18 :: dashtibox :: Replies: 0 :: Views: 547
If both inputs of a 2-inputs NAND gate are high then its output is low. If both inputs of a 2-inputs nor gate are low then its output is high. The "N" means it inverts.
They are logic gates so they do not default to anything.
If a logic gate is TTL then it draws a high power supply current all the time and its inputs float to a logic high if they
Elementary Electronic Questions :: 10-11-2014 21:32 :: Audioguru :: Replies: 16 :: Views: 788
No, you are not correct.
All that bit of code says is that "if a is greater than or equal to b, assign a to d." The value of b is not changed by the comparison, and nor would it be in the microcontroller world. There is also nothing in that code to indicate that a<=b would always evaluate to TRUE. You have given no (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-29-2014 13:04 :: rberek :: Replies: 9 :: Views: 1410
The difference between both calculations (11 versus 53 primary turns) comes from different designed Bmax values. Unfortunately neither the 450 mT nor the 100 mT number have been substantiated. A core loss and transformer temperature rise calculation should be performed. If you do it, you'll see that 100 mT ("1000 G") is not effectively utilizing th
Power Electronics :: 08-04-2014 21:21 :: FvM :: Replies: 14 :: Views: 1822
zeners are not efficient nor stable compared to bandgap reference diodes used in all LDO's (LM317 type and many others)
Zeners must draw more than the worst case load to ensure when loaded there is still enough current to get past the knee in the zener. Then when no load, that current * voltage can lead to thermal problems for high power.
Elementary Electronic Questions :: 08-01-2014 20:17 :: SunnySkyguy :: Replies: 4 :: Views: 775
The tiny speaker produces no bass sounds below 150Hz.
I could not find a manufacturer's name nor datasheet for the little stereo amplifier IC.
The two channels of the amplifier are already bridged so their outputs cannot be combined for higher output power in mono.
With a 5.5V supply, it produces 1.5W into 4 ohms per channel with low (...)
Elementary Electronic Questions :: 07-15-2014 02:38 :: Audioguru :: Replies: 19 :: Views: 1519
You need to know the actual LDR resistance with the room light, not with sunlight nor moonlight.
When the room is not lighted then is there any other light that would reduce the resistance of the LDR? Measure the LDR.
Then you will be able to design a simple circuit.
Analog Circuit Design :: 07-09-2014 15:04 :: Audioguru :: Replies: 5 :: Views: 618
i implemented vhdl program for one of the digital design, here latch (using nor gates) is one of the components, while i simulate the output of latch is
undefined--u--, if i plase some delay(after x ns) in inputs of latch the out put is came, but the hardware didn't consider this type(after x ns) of commands.
if i check that latch component
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2014 05:59 :: surerdra :: Replies: 1 :: Views: 597
I would like to know about VS motor. This type of variable speed motor is not a combination of VFD with induction motor nor it is a DC motor with speed controller. Perhaps it is an induction motor but different approach in speed control. I only heard the description of it. Also I tried with few books and could not find any (...)
Power Electronics :: 07-04-2014 19:09 :: ahsan_i_h :: Replies: 2 :: Views: 547
I write a custom library for synopsys design vision which only consists of XOR, nor, and IV (inverter or not). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of nor gates. I write the library as flows:
area : 1000; (...)
ASIC Design Methodologies and Tools (Digital) :: 06-14-2014 21:30 :: Ebrahim Songhori :: Replies: 0 :: Views: 479
I would expect process value and setpoints represented by simple signed or unsigned integers, neither arrays nor character strings. In case that the setpoint is given as a decimal string, it would be converted to an integer number, e.g by atoi() before comparing it with the process value.
this definition gives an error with GNU C
Microcontrollers :: 05-06-2014 07:01 :: FvM :: Replies: 6 :: Views: 515
For the same drive strength, the NAND-not combination needs less silicon space than the nor solution.
Vice versa, by using your nor solution on the same silicon area as the NAND-not combination, the nor output has less drive strength.
However, if you don't mind about drive strength (or silicon area (...)
Analog Circuit Design :: 04-27-2014 22:00 :: erikl :: Replies: 4 :: Views: 605
Dear norbila Md nor. You can use these pdf files. I wish this helps!
Elementary Electronic Questions :: 05-13-2014 08:05 :: husamsdu :: Replies: 4 :: Views: 695
do you need to vary the voltage and have a current limit?
- - - Updated - - -
you can design a BUCK converter in order to get this voltage , because it will be more efficient than a linear converter.
though that is often true it is not the only consideration, nor maybe not th
Power Electronics :: 03-30-2014 06:35 :: kam1787 :: Replies: 3 :: Views: 703
here for almost all current mcu today
but you did not specify your mcu, nor the language you use ?
PC Programming and Interfacing :: 03-17-2014 14:06 :: Kripton2035 :: Replies: 6 :: Views: 1118
Energy by default flows from source to sink. Only at RF we consider reflected power and measure it. It is not the case at DC nor mains AC. Maybe rikotech8 is asking about measuring energy flow in power grid where exists more than one energy source? Who knows?
Analog Circuit Design :: 03-01-2014 09:29 :: Borber :: Replies: 8 :: Views: 755
I don't see neither eq. 4.49 nor 4.48
Mathematics and Physics :: 02-20-2014 20:37 :: albbg :: Replies: 3 :: Views: 872
How could you make layout XL "focus" only on the layout and not some extra space around the layout ?
The thing is that when i generate my cell, it creates a larger cell than it should be because of an "extra" space added i don't know why !
There is no floating pin nor any other object, still it confuses me.
Thanks for your help[A
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-17-2014 15:45 :: K4R1 :: Replies: 1 :: Views: 582