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49 Threads found on Not Using Mux
Hi all! I have design with clock multiplexers and clock gating cells. I'm using Cadence RC compiler for synthesis. After synthesis, i need to simulate resulting netlist with SDF file using ncsim. When i run the simulation, i see that clock mux and gating cell delays are not '0'. How to get an SDF file with excluded clock (...)
For (0,1) I get that 1st TG is open and the 2nd TG is closed. Didn't you note that the 2nd pair is driven by S'0, but not S0 ?
I'd have to check the synthesis results, but I think the char : char + 1; might result in an implementation where the select to the multiplexer is a register (char) followed by an add by 1 before being used to select the mux output. not an optimal circuit for performance, this is a direct result of using a variable as it is evaluated immedia
If you need priority use "if-else" else use "Case". "if-else" is not same as "Case", not sure why the synthesis result is the same. ads-ee explained in post #4 why "if-else" is exactly the same under the given conditions. If you read the explanation, which part is wrong in your view? For which value of sel do you expect different Y
Hi All, I am new to the frontend. My expertise lies mostly in the back end . I am trying my hand at verilog coding and simulations using ncvim. Some how I a not able to dump a proper vcd file to view in simvision. Can someone please help me to figure out the issue. This is the content of a simple mux ( file my_mux.v) (...)
Indeed, interesting experiment. But I don't think the results would be consistent or reliable. not a good engineering practice, if this design becomes a "real" product.
Hi, If you are using EM keypad, you need the coding circuitry for that I think. But if you are going to implement it in FPGA you can use simple push button keys and connect them to a mux and AND gate Circuit. A 4:1 mux can be used for 4 digit code. AND gate is for detecting if any key is pressed or not. Select line of the (...)
You only switch the 1x2 mux to select the appropriate device so it only takes one operation each time a selection is made, the I2C traffic isn't affected. I susect the real answer to the question is you select a different address using the hardwired address pins on the IC though, almost all, if not all, I2C devices have selectable address (...)
Dear Friends i am interfacing GSM Module Sim 900 and GPS Module Holux M89 with Atmega32A using 74157 Multiplexer and select pin of mux is connected with pin 16 of Atmega32A. The Problem is that mux is not passing gps and gsm data to microcontroller. i have checked the continuity of traces all are ok. a proper voltage 4.9 is (...)
Hello All, I have a design..I am trying to insert dft in the netlist.. I am using Synopsys DC Compiler with DFT Compiler from synopsys. I am using the full scan mux-d style.I want to know that what are the main reasons for not stitching the some flops which are already converted to scan flops after compile -scan. I (...)
I'm not sure this can be done. I looked at it a little bit, but couldn't figure it out. I'd be interested to see it done. You can do it with 2 mux's or mux and gate.
This is a simple asynchronous mux, so why not replace the process in nuxtwo with the single line: cout <= m when o = 0 else n; ?
we can use any number of and,not gates
It's not possible, because FPGA have pure digital IOs, that can't be used as analog switches.
It's a simple 5-channel mux, I don't see a particular problem related to the loop scheme. You can also enroll the loop, use a generate statement or rewrite it like this: FPGA_TO_HOST_TX_O <= UUT_TO_FPGA_RX_I OR not CONNECT_I; FPGA_TO_UUT_TX_O <= HOST_TO_FPGA_RX_I OR not CONNECT_I;
Hi sujan, check the recieving part of your it the same you are using or not. I had faced the same problem but i dit it atlast. Better you add your circuit and program till then nobody will come to know where you are facing the Problem.
Both node outputs K & D (as well as nodes H & S) seem to be unused, i.e. not connected to any input? Should only be a warning.
Can any Boolean functions be realized by 2--1 multiplexers & why can or why can not???Can anybody help me...?:-( ..... Thanks!!!:smile:
I think you need to give us more info. If you are trying to measure a resistor, why are you using a sine wave and all that other stuff? Just put a constant current source into your resistor, and measure the voltage, right? Why not DC?
Hi, Pls any one tell how to calculate the power consumed by the opamp if i am using +15v and -15v supply also.... i m not able find how to calculate the power consumed by analog mux adg508f with supply vdd = +15V and vss = -15V Thanks & regards Rocker
@std_match, I am not sure what the interviewer meant. I know how to implement a 6:1 mux, but in my course of study i have never come across a x:2 mux. The confusion is, it could be a decoder, but as we know the general convention is x:y, where x is no if input lines and y is no of output lines. The no of select lines depend on x(encoder) and (...)
You get started, when you get stuck, come back for help with your problems. We're not here to do your homework assignments.
Is it possible to create a XOR gate using two 2-to-1 mux's if you do not have access to A bar or B bar and can not use an inverter or not gate. I think it is impossible, but my professor is convinced otherwise. If A and B are both 1 it seems that it would be impossible to make the output 0 (...)
you can create a 2 digit BCD counter by using two 4 bit counters and some logic gates.The main idea is that when the count in the first(LSB) counter reaches the value "1001"( 9 in decimal) it is reset to zero and the second(MSB) counter is incremented by '1'. I am not sure about why you need a 4:1 mux for this. --vipin vhdlguru.blogspo
Hi all I am using synopsys design vision for scan insertion into my design (mux based) However I am not able to find out which library to be given as a target library so that scan chain insertion models can be fed to the tools. I have faraday 180nm library as well as OSU std cell library but I am not finding any db file (...)
this will work.... I0(A'B') = logic 1 I1(A'B) = (not C) I2(AB') = (C xnor D) I3(AB) = (C xor D)
You need to by pass this generated clock using mux. mux can be inserted in design itself or now-a-days tool can also insert mux automatically by finding such places. But definetely, second option is not receommended to be used as it may create equivalance issues. mux whose input 1 (...)
FvM is very right. i have designed some thing like this before. i have one comment on your design. the way you are trying to store 32 bits in an array of 32 will need a 1-to-32 mux. which i think will be not a good design. instead if you make a sift register of 32 and store in MSB and shift in each cycle. after 32 cycles you can read the data
Can anyone send me a material on not ,AND ,XOR,XNOR,NAND,INVERTER using mux ??? Plz its urgent send me a material i will give u 20 points
Hi basha_vlsi, How did u arrive at the inputs .. I mean design of (C and D) ( not(C) and D).. Please elaborate.. it will be helpful.. thanks, sp3
I think he's asking why "Requirement" is 0.000ns. It seems like something went wrong in the constraint arithmetic, but I'm not sure what caused it. It would help to see the HDL code.
Whether this will work? Data to D pin of the FF. Data -> buf -> Input A of XOR Data -> buf -> not -> not -> not -> not -> Input B of XOR Output of XOR -> Input A of AND Clk -> Input B of AND Output of AND -> CLK pin of FF regards, Arun
I assume you are referring to a Xilinx FPGA. I'm not clear exactly what you are building, but if you really need to switch between two clocks without glitches, try the BUFGmux (if your FPGA provides it) instead of an ordinary mux such as muxF7. If possible, try to design synchronous logic that doesn't require gating or (...)
manasiw2 u cant do that, if u tie the clock to the select pin using a single mux then if become latch no DFF cause the output will change as long as the input is changing if the clk is still high. It become level trigger not edge trigger. I think kanagavel_docs have provide a good solution for this question.
In FPGA? Please be aware that you will not find any architecture capable of doing this function.
HI, How to derive xor gate using 2:1 mux and 1 not gate? -P
hi , anyone help me to implement mux using XOR gate? note: its not xor using mux thanks in advance
its not possible to build 2to1 mux by using xor gates only. This is because of xor gates fundamental property I call it as pass gate what I mean is consider two input xor gate if one input is '0' output follows other input if one input is '1' still o/p follows other input but inverted. this is unlike AND gate which is blocking gate if (...)
Why not let Astro do the whole thing. It will usually do a better job than is possible by human. 1- Specify a clock source (frequency, jitter and so on....). 2- Specify all other clocks as generated clocks sourced from the source clock. 3- Tell Astro to insert a BCT on all these clocks, including the master clock trunk.
Hi all, I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal (...)
Hi research............ well the Logic you have gone for is not right....BECAUSE one pin is always grounded which means no chance of selecting 100,101,110,111.......states.....RIGHT if you write the characteristic table you will realize.........the fault the method to go is for the grnd pin connect another mux(2 x 1)... i (...)
VHDL is strongly typed language. Means it will not do type conversion automatically. You will have to take care of type conversion using functions like to_integer. here is how you can write ur mux. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity mux8to1 is port (X: in (...)
You can split total LED's current using multiplexing control for the LED's. Divide 128 leds into 8 group and display only one group at once. Of course multiplexing leds requires a little bit more current than static driven but total current will be less. Use high brightnes LED devices (it requires lower current to emit good light). Precisely adjus
two inputs A and B, One select line. Let the select line be A(or B) the first input would be B(or A) the second input would be not(B)(or not(A))
using assign is better, it will not cause sim/synt mismatch.
Is the output delay corresponding to input is permittable in the design? I guess its not , unless your design is sequential.. You can achieve the same results by using a combinational 16:1 mux with 16 bit inputs and 4 bit select. But ur code needs to be changed. Please post ur NETLIST for omre comments.. rgds
you should read this Microchip application note: LCD Fundamentals using PIC16C92X Microcontrollers note: Microchip calls it mux ratio, not duty cycle Mik My fault: Microchip of course
As we know, data multiplexing is often applied and two main implementation methods are prevalent in FPGA of Xilinx, say Spartan. They are BUFT and the combination of mux and LUT. However, in practice, some expericense informs us that BUFT is not recommended due to its simulation mismatch and poorer performance. Also just for this, Synplify aut
This does not happen to me. How did you do it?

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