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1000 Threads found on edaboard.com: Opamp Biasing
Hi, I have designed a folded cascode two stage opamp on 130nm process. The opamp works fine. Figure below shows the gain and phase response of opamp. It has 45 degree phase margin. Now the next step is to design circuit which generated the bias voltages for opamp. For initial case i used a resistive voltage divider to (...)
hi all! to bias the tail current of the opamp, bias with which one as below is better 1. Ptat current 2. Constant current
An opamp's input must be biased at half of its total power supply voltage for the highest symmetrical output swing. biasing an opamp has nothing to do with its voltage gain. Its voltage gain is the ratio of its negative feedback resistor to the other resistor (the input resistor if the opamp circuit is inverting or the (...)
Hi; I have a question in biasing an opamp. I only have +3volts supply on my circuit. The opamp i am using requires +3volts and -3volts. So, do i need to generate -3volts supply for biasing? If i use 0volts instead of -3volts then my simulation is incorrect. What is the bestway to fix this problem. Is there a fix (...)
Hi all and good day! I have question regarding correct biasing of opamp input pins. I am studying desing of fully differential opamp and have misunderstanding of correct biasing procedure. As I understand from books opamp is self powered and biased element so it not need biasing at normal (...)
HI GUYS I AM DESIGNING FOLDED CASCODE opamp FOR SWITCHED CAPACITOR APPLICATIONS I AM FACING FOLLOWING PROBLEMS 1) biasing THE PMOS M18 AND M10 WHAT SHOULD BE THE CIRCUTARY FOR biasing IT OR WAT I HAV DON IS CORRECT THE CASE FOR NMOS M23 ,M24 TOO ( CHECK ATTACHMENT FOR PIC OF DESIGN ) 2) NO PMOS OF CASCODE BRAN
Hi, Can you guys please help me with designing the bias circuit for the fully diff folded cascode opamp (attached) i.e., to generate the bias voltages Vb1, Vb2, Vb3. 108205 I tried to search in many books, but none seem to explain properly the biasing schemes that can be used. Any reference to relat
To measure a high current(up to 30A, typically 15-20A.) i used a resistor based current measurement. I connected the sensing resistor to the low side and amplified(x10) the voltage on the resistor via an opamp (LM358N). Then i applied some tests and saw that, output voltage of the opamp is not directly proportional to the current. What may be the p
I think the first can get the higher gain since the cascode output, the second is not easy to increase the gain since the gain mainly acquire from the output stage. But the first output swing is small, but i think it meet our application in bandgap error opamp. The second reason is the bandgap Vbe is low, so it need a Pmos input.
I think the structure in opamp will be useful.
Suppose in your second stage you have NMOS common-source amp and PMOS current source load. Then your second stage biasing current is mainly controlled by the PMOS current source, and actually Vgs of the NMOS is determined by this current. However if the opamp is used as a feedback amplifier, the common-mode feedback will automatically adjust the Vg
u can refer to a book Analog Integrated Circuit Design by Daved Johns & Ken Martin. In chapter 5 & 6 have depth explaination on biasing circuit for opamp. one of the circuit i have posted at
An ideal symmetric opamp surpress the common mode noise components from the bias. If the opamp is used in circuits which have to reject some big signals the common mode noises get modulated by the big signal and distort the wanted small signal. So in addition to AC small signal noise optimisation run a period noise analysis with a blocking signal.
Hi there, My question is that whether the input common-mode voltage has to be equal (or intend to set to be equal) to the output common-mode voltage of opamp for the general opamp design? Thank you very much. ethan you'd better use the same value for the input and output, if you want to make multi-stage system with
It's difficult to control the drain voltage in open loop configuration. Without negative feedback, the gain of the opamp will be so high that the transistors can be easily driven out of saturation region, making the drain voltage difficult to be controlled. You can use a common mode feedback circuit to stabilise the drain voltage. You can try con
Importantly, is the Y-axis right? I mean you have a Y axis which calls of degrees. I do not think so. I do not think that there is an opamp which will cause a 5 degree phase shift. Secondly, have you put the options as .OPTIONS UNWRAP for the phase plot? If you have done so, then the cause is due to two RHP zeroes and not multiple poles. The pr
The first method is to use cascode transistors instead of simple common source amplifier. Then, you can use Gain-boosting method which is described in almost all CMOS analog circuit design books. opamp
Hi Guys, Currently im designing an opamp for my design familiriaty. If you noticed from my schematic there are 2 PMOS biasing. For bias1, i believe what i have done is correct that is I biasing them according to W/L ratio. But as for bias2, i believe that biasing shouldn't be like that as the VGS is not same at the two (...)
everything in saturation? no, it is not right. Maneatis load should not be all in satiration region. U may not understand maneatis load's theory. u need a buffer first to increas the vco swing and then followed a comparator. buffer can have the same structure as ur vco cell. hi actually i used the maneatis delay cell ins
Normally, the bias circuits must make all the transistors of opamp to work in the saturation region
biasing circuit is used widely in analog circuit design to bias circuit in proper operating point. let sat if you design opamp, all the transistors must be biased in saturation mode because in this mode we can get large gain. example of bias circuit is voltage reference circuit, current mirror/sink/source. it depend on your applications. hope my ex
im a newby...i trying to do a sample and hold ADC using rail to rail opamp.i have finsih up the construction base on one of the sample i found in internet.but there were no calcullation in W/L ratio. if i want to learn how to calculate there any good reference that anyone can share. what i doing now with the W/L ratio is just by put a
This circuit consists of simple differential opamp and Its Bias Circuit. What is the role of N4 in Bias Circuit? thanks
Hi, I have several questions concerning the attached opamp structure. 1. What is function of M14, is it source follower ? how does it work ? 2. What is the function of Mp and Mn, common gate ? how does it work ? 3. Does the M16 and M17 form the class AB structure ? 4. What is advantage of this opamp ? 5. Is it a LDO circuit ?
Thanks for your comment. Do you think that it is neccesary to bias all opamp with Bangap current? What do you think of PTAT biasing? It seems to be compensating for input gm variation across temperature. biasing 1, 2 and 3 are more commonly use for biasing. Which one do you think is better? Why? Thanks.
How does the bandwidth of opamp depend on biasing current ?
Hi, How can to reduce offset in input terminal of opamp ? Layout? or circuit? Thanks
I am looking for a circuit that can generate the bias voltage for the opamp that I have far that circuits I have looked at are either supply or temperature there any circuit out there that does not use diode and can generate the bias voltage for opamp?
Hi, I am trying to design a fully differential cascode opamp with common mode feedback. I have read Razavi, Holberg and Johns and I have a schematic but I can not find anywhere how to decide the values of the biasvoltages. Can anyone tell me where to find information about the values of the biasvoltages. Anna
if you are trying to maintain the voltage constant then ideally you are operating in DC... i dont think you would have worry about these things... btw what opamp are you using and what circuit and application r u tryin which requires an opamp for biasing???
on page 155, figure 5.3.18 in Huijsing's opamp theory and design, He said, for this general-amplification feedforward biased class-AB output stage, 1. "Q3, Q5, Q4, Q6 form a positive coupling loop with a current gain of slightly lower than1, which keeps this loop stable." I think this is a current loop, but I don't how
Hi all, I have a question about SC CMFB. Is it possible that after the CMFB settles to its desired voltages, one can use the opamp without using the CMFB. Like the case in an algorithmic ADC, where opamp is used in few clock continuously without the CMFB being used.
I successfully completed the classic 2 stage opamp design with Miller compensation, and am looking at advanced Op Amp designs. I started with Folded Cascode opamp design and am in a confusion not knowing where to start. I went through Johns Martin, and Jacob Baker's books. Both seem totally different in the way Folded Cascode
Hi I am designing an application specific CMOS op-amp which has very stringent requirements. I am starting with a basic 2-stage topology Some of the requirements would be : 1. Unity gain Bandwidth > 500MHz (Also in feedback my opamp needs to have a 3dB Bandwidth of > 25MHz) 2. High gain >75dB 3. Another very important requirement of my de
I want to run dc analysis of an opamp, should the cmfb circuit be included? Thanks
In typical two-stage opamp, second stage is usually a common source gain stage with current mirror load, like in miller opamp. How to actually bias this stage? Since it is essentially an inverter, the dc operating point of output node is very unstable and either nmos or pmos could easily goes into linear region and kill the gain... any suggestio
hi, all when designing the op in bandgap reference, how large the load capacitance should we consider? (generally) i have designed a two-stage opamp with following specs that meant to be used as an error amplifier in a buck converter: DC Gain: 78db Phase Margin: 85 degrees G.B.: 10MHz PSRR: 100db loading: 5pF compensation capacitor: 3
Why do we insert a large cap on the input and a large inductor in the feedback when performing an AC analysis on an opamp? Like this...
how do i generate Vbn Vbp Vcascn Vcascp Vbcm??? if opamp is fully differential....
The very old 741 (43 years old) opamp usually has a positive supply and a negative supply. Then when its input is at 0V it has plenty of bias voltage. The input can swing positive or negative a little.
R4 provides a DC path.The small bias current of the opamp will charge the cap otherwise.
As shown in the figure below, it has a capacitor feedback loop so that the dc voltage from input and output will be blocked at same time, so how can I supply dc bias to the input node of opamp? Thanks! 81024
Anytime I read something like the header "opamp behaves strangely" I first look at the power supply - and very often single supply is used without knowing the consequences (proper biasing).
Hi, i've designed a CMOS folded cascode opamp to have a SLEW rate of 150 V/us (Iss of the differential pair is 30 uA and CL = 200 fF) in unity gain configuration. I found that ICL is about 1 mA.I saw current in the differential pair is unbalanced in one branch only for a very quick time so the capacitor can't charge like i would. So i would know
All shown DC-biasing circuits can be used. The purpose of DC bias is to operate the P/N or Schottky junction at the best point where then open/closed" ratio offers the best rectification of RF input signal. Some circuits leave the DC-bias voltage at the DC or video output. THe best solution is to use a pair of detector diodes connected to (+) and
Hi, I designed a folded cascode opamp with gain boosting and it works properly, now I want to design biasing voltages of the opamp. I could design a biasing circuitry for the main opamp, but I had a hard time finding a way to generate the dc voltages that need to be applied to the gain booster input. I (...)
Hi, I want to ask all the analog ASIC designers here if they have some nice formular collection and cookbooklike papers how to design different flavors of opamps (from 2-stage till full-swing class ab outputs). I know the book from holberg and gregorian - what i'm looking for is more complete formular collection (for example also for class ab am
i know quite a few. for single stage, you can either do this using a custom IC or using discrete components. i am assuming you want to bias at a fixed voltage and with a constant current. what is the gate current, how much do you need. What FET are you using. If it is low then you can use a crude method. A lm555cm timer configured as a free
links to some useful documents here:
Anyone have infornation about RF transister biasing? Especially, class B,C.