Search Engine www.edaboard.com

Are you looking for?:
why ota , why ota , why ota , why ota

How to calculate THD and HD2 and HD3 of an OTA in cadence

Hello Can any one help me in calculating THD, HD2 and HD3 in cadence. I am designing an ota. I dont know what sampling frequency to use? In some forum I have read I have to calculate DFT aswell for THD can any one help? Thanx

[Moved]: Noise in RMS and PSRR calculation in Cadence

Please can anyone one help me in calculating the noise in VRMS. I have got the noise in cadence in uV/sqrtHz now I want to convert the uV/sqrtHz in Vrms. I have the noise result attached. Do I have to use calculator if yes the how? I want to calculate PSRR in cadence of an ota. Can any one help me step by step procedure to calculate PSRR (...)

[Moved]: How to calculate the overall transconductance of an OTA circuit in cadence

Can anyone help me in plotting the overall transconductance of an ota (Gm) circuit in cadence step by step. Do I have to do the ac analsis or DC analysis?

Assura DRC error cmhv7sf

Hi there, I'm making an ota layout in cadence, ams 0.18um (cmhv7sf). The only DRC error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932

you can simulate DC simulation after that you go to results --> Annotate DC solution . the DC current is noted in the schematic and you multiply by Vdd to obtain Power Consumption

Monte carlo Simulation for two stage ota

Hi I am designing a two stage ota using cadence . Need to run monte carlo simulation for offset voltage. can somebody give me any user guide. Thanks.

[Cadence - LVS] Problem on Bulks

Hello guys, I'm new on cadence and I'm designing the layout of an ota and on the LVS I have encountered the following message: "Unmatched Internal Nets" I think regarding the connection between: ->The bulk and the vdd! of the transistors (WHITE on the image) ->The connection between the bulk and the com_diff net (BLUE on the image) The imag

i wanna design and simulate bulk driven ota Which type of transistors should I choose (for bulk driven mosfets) ? ( pmos2v , pmos2vdsw , ...) cadence ic TSMC 180nm pdk

create .SCS file to cadence design

Please be clearer. I am not sure what do you want to do. If you want to create your own ota based on your design, just draw the schematic.

How do you measure the output impedance of an OTA in Cadence?

As a suggestion, should I place a voltage source at the output and inject a current back into the ota, can I calculate Rout by vsrc / iinput? Or something like that? Yes - that is the classical method. Use a small-signal ac source and provide the proper biasing (operating point). The signal input must be grounded

Linear range of an OTA in cadence spectre

Hi, Could anyone help me out to plot the linear range of a single ended ota, I mean the test bench to plot the input differential voltage V/s the output current. I am trying to plot the curves but I guess my test-bench is wrong. Pls help me out

design op-amp in weak inversion

Hi all, I'm designing an ota in weak inversion using cadence. I found the threshold voltage of each transistors working in weak inversion are different and they are also changing with applied gate-source voltages. Does anyone know how it happens? Thanks in advance!

Cadence: How to give multiple instances different variables?

Hello, I'm drawing a 2 stage fully differential miller ota with 2 CMFB networks. These CMFB networks are ideal and contain a vcvs with a gain "Acm". However, when I put 2 instances on my schematic and use the ADE (Analog Design Environment) to retrieve the variables I only get 1 variable Acm for the 2 blocks. I wish to control them independently

Plot gm/id vs (id/(w/l)) curve in spectre-cadence

Hi, I am trying to plot gm/id vs (id/(w/l)) curve of a transistor for design of ota, i referenced many suggestions in the community but none of them is giving a clear idea about how to plot the above mentioned curve. I am able to get the plots for gm/id vs id , but when i am trying to do the parameter sweep w/l and ch

Design of third-order OTA-C type filter using cadence

hello,i have using cadence to design the basic ota but i cnt get the correct ac response... How to determine the value for Vin+,Vin- and Vbias? 87232 87233

Design of third-order OTA-C type filter using cadence

Hi, This might help you. One is the internal circuitry of an ota. And the other is how you can build double ended ota from two single ended otas...

Gain of two stage OTA

I am a beginner in cadence,I am designing a two stage ota. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output shows amplification,but i get a triangle wave with ac ga

PAC analysis VerilogA

FATAL : "Attempting to write a file that is not open. Open a file first then you can write to it. May be simply your path/fileName isn't correct?

How to measure THD and gain in cadence 6.1.4

yes, add input signal to design in testbench view as Vcm and diff signal on top of it, ( simply connect vdiff to pos input of ota with mag of 1, and vcvs with gain of -1 to neg input,) and then run your ac simulation. Ofcourse instead of selecting Vout as in amp u should select Iout . from the resulting plots (ac simulation result ) u get what u n

Test bench of OTA parameter measurement in CADENCE

Hello every one, I have attached design of programmable ota. but i dont know how to measure parameters like gain, phase, CMRR, PSRR, slew rate etc. To measure all this parameters i have used one test bench which is also attached here. But problem is that i have measured gain in db, which is negative and phase is also negative. In test bench th

How to apply differential input in layout of OTA

You need to create a symbol for your ota schematic before creating layout. Then create layout for that ota cell and extract the layout. To run post layout sims, I would create a config for the testbench. In the config view, point your layout ext file instead of schematic and the run your sims.

gm measurement plot in OTA in CADENCE 6.1.4

Hi Rajeshree, setup up your testbench such that your ota is in unity gain Feedback. Run a DC sweep and measure the output error current. you can connect your output to a current mirror source/sink (it depends on your transconductance design). Change in o/p current wrt change in i/p V is your Gm of the whole circuit..

Wide Swing OTA-HELP i finding various parameters in cadence tool.

m finding difficulty in transient response?? Which difficulty? Appropriate testbenches are well described in the above PDF. But still i find problem in calculating gain margin??....can u tel me how to calculate it from plots??? Just plot the gain vs. frequency. Gain margin is the g

Spike in phase of output voltage

Hallo, I see a smooth spike in cadence when phase of a 2 stage miller compensated ota is simulated while i was trying to find out phase margin. Can any one tell me the reason why i see the small spike(its actually not so sharp).

netlist error in Cadence Virtuoso IC Design Tool

I am facing a netlist error while running a test bench circuit which has only a single ota subcircuit . It was working okay after i completed the test bench and ran some simulations on it. After that I wanted to simulate the post layout of that ota circuit, for which i simply inserted the extracted file name as performed in the last part of this

Analog IC ckt design on Cadence Tool

how to evaluate slew rate, PSRR,IIP3 and CMRR? Theoritical analysis for Double CMOS pair in detail. And also the transfer function for Modified Nauta ota using Double CMOS pair. Plz help me since i am working project on this tool

Cadence Virtuso: How to model current limiter

Why not directly use current mirror ota with 100uA output?

how to measure parameters of a operational transconductance amplifier(OTA) design

hello everyone i have designed the analog schematic of a operational transconductance amplifier(ota) circuit in cadence . now i want to measure the following parameters of the designed circuit:- 1) Dc gain 2) unity gain bandwidth 3) phase margin 4) power consumption 5) settling time 6) output swing

How to calculate SFDR for an OTA on Cadence Virtuoso

Can anyone tell me what is the procedure for finding the SFDR from cadence of an ota?

how to plot the curve of gm vs Vpk for OTA-C filter

Hi all, I am trying to design a Gm-c filter,the next step is to ensure the linear input range of the Gm cell no less than 200mV peak to peak,my question is how to plot the curve of gm vs Voltage peak to peak with cadence? anybody can help me?

Capacitive feedback OTA Design Issues in Loop gain

HI I have designed a capacitive feedback ota ( ota is folded cascode single stage ota with ideal CMFB). When I simulate the loop gain of ota (using iprobe and stb analysis in cadence) I get a 'High Pass' response at low frequencies. I am not sure why this is happening. Please help to solve this issue. (...)

op-amp noise simulation

Hi guys, I have designed a 2 stage op-amp, diff input and single output. I use cadence spectre simulation tool. All the specs are pretty good. Now I want to calculate the open loop input referred noise of ota. But I have a question in noise simulation and I dont know if the results I get are correct or not!!! I want to perform noise analysis.

How to measure and simulate the OTA offset voltage in Cadence?

hi all, I am designing a folded cascode ota, and I want to know how to measure and simulate the ota offset voltage in cadence. Moreover, I want to do Monte Carlo Simulation for the offset voltage. Anyone can help? Thanks in Advance

OTA sizing by gmoverid approach

Sorry if I am confusing you. What I did was just connect the gate to the drain of the MOSFET, ground the source and connect a DC current source from ground to the drain/gate of the MOSFET. Now the transistor is always in saturation and you can sweep the DC current value from say 100n to 100u or a number that you know covers your range for the ota c

Matching technoque for filter to get S11 -ve

Hi,i am trying to design a continuous time filter by using an ota. I am working in cadence and using a port at the input .But,i am getting the S11 as 0dB in most of the part.But i need S11 -ve.Can any one tell me please how can i get S11 there any matching techinique specific for the filter. thank's

Problem with layout genration in virtuoso

hellooooo..... I need a small help... I am using cadence virtuoso for schematic entry and layout design for a SigmaDelata ADC... I created the individual modules in like ota, comparator etc in a seperate library. I also cereated the layouts for these modules.. Then i made the the circuit of the ADC using these modules.. For its layout i used t

How to measure input noise of an OTA in cadance?

How to measure input referred noise of an ota in cadence. Thanks in advance.

HD3 and THD measurement in cmos ota using cadence

hello !! how can i measure HD3 ,THD, IIP3, IIM3 using cadence analog environment for cmos ota design please reply soon......its urgent thanks in advance :)

The procedure of the simulation of the Harmonic Distortion

Dear All, thank you for reading this topic. I just design an ota and I will conect it to a capacitor to build a lowpass filter. Then I will put a 100mV sine signal at the input and want to see the harmonic distortion at the output. Does anyone show me the procedure that how can I get the result? A sample is put in the attchment and t

what r the value of these parameters in gpdk180n

What is the value of vthn, vthp, λn, λp, ?nCox, ?pCox in gpdk 180n library for simulation in cadence spectre.I am using 1.8 voltage supply. Plz reply if anyone knows. Its needed to start my ota design. thanq in advance. Added after 1 hours 40 minutes: please reply someone. [color=#999

Fully differential OTA testbench

I design a fully differential ota but have some problems with the simulation config.Can somebody provide suggestions and materials about the ota testbench.Thank you!

how to use cmdmprobe in stb analysis (cadence)

hi, there. i want to analysis the stability of this full differential ota(shown below), can anyone here tell me how to add the cmdmprobe in analogLib into this circuit to do the stb analysis? Thanks.

Good tool for verilog-a simulation.

I find modelwriter of cadence is very useful for verilog-a simulation. I can produce lots of blocks of analog circuit automatically, such as adc, dac, ota, peak detector, VCO, PLL, and so on. And the parameters of all blocks can be set as we like. And then use spectre to simulate. It is quite useful. Recommend it to you. And the detail of it

hi can someone tell me how to do a pole-zero analysis of an signle foleded-cascode ota in cadence ? thanks in advance .

how to simulate the OTA with SC-CMFB in cadence

I have search the similar topic in EDAboard but I just get the way to simulate it in Hspice. But in my lab we use cadence as simulation tools so I want to know the way which can be used in cadence. 3x!

urgent help needed in simulatin of SCA

hi, i have designed OP ota for SCA and now i don't how to simulate my SCA, could some one suggest me efficient way to do that, or maybe any artical or paper. after i finish my thesis i will try to make one report for those people interested in this area to learn the good steps for making ota, my one 1.2v with highe performance. other thing i wn

How to measure the Gm of an OTA in Cadence?

Configure the negative loop back with large R~1GOhm and C~1F (as low pass filter) for offset voltage compensation. Insert ac voltage source Vin with DC bias in series with positive input of ota. Do AC analysis. Gm=Iout/Vin, where Iout u can measure at the output of ota. Good luck

Help me plot the gm of OTA versus the differential input using Spectre

hello, i want to plot the gm of ota ,versus the diffrential input , i am using spectre , can any one help me? i attached a picture of what i want to draw taken from a papper. thnx