377 Threads found on edaboard.com: Ota Gain
How to determine transistor size of folded cascode ota(gain=80db,fu=30Mhz)?
Analog Circuit Design :: 25.02.2004 20:47 :: rose_song :: Replies: 5 :: Views: 3321
iam designing a fully differential folded cascode ota
gain: 66 db
Vdd: 3.3 V
power dissipation 3.7 mW
BW: 980 Mhz
I have used switched capacitor CMFB(Common Mode Feed Back)
Problem: Iam getting gain of 54 dB and power dissipation of 2.7mW but the problem is that the gain curve is not crossing 0dB it reaches a (...)
Analog Circuit Design :: 22.01.2008 05:21 :: shobhit :: Replies: 6 :: Views: 2389
i am designing a 3rd order Sigma-Delta ADC for Audio applications. The specs would be something like 18bits, THD<0.1%, OSR = 256.
What will be an estimate of the ota gain and BW, and why?
Analog Circuit Design :: 20.10.2008 17:32 :: tapanshahp :: Replies: 0 :: Views: 435
1) I want to get a relation between the Vref variation due to the temperature variation and the ota gain of the bandgap reference source shown in the figure.
Could I make a small signal analysis???
something like that:
2) I saw, in simulations, a voltage variation between the input terminals of the ota due (...)
Analog Circuit Design :: 23.04.2009 14:26 :: jc2 :: Replies: 0 :: Views: 805
I am designing an ota for my GmC filter, and I have question regarding the THD simulation.
In, papers, I find THD results for the ota while sweeping input signal amplitude. However, I am not sure if the output is left open for this simulation. for example, if the ota gain is 40dB, then for a 100mVpp input which very often (...)
Analog IC Design and Layout :: 13.07.2010 23:00 :: sharkies :: Replies: 1 :: Views: 620
My gain is an expression for a four stage ota gain, which i want to sweep with my input Common mode level. I guess there is little clue to what-to-do in your reply !
Analog IC Design and Layout :: 28.08.2010 13:34 :: EmbdASIC :: Replies: 4 :: Views: 592
Am I understanding this correctly. I have an ota and given that the f3db is 60 and I want to increase its gain but the as the gain increases the value of the f3db decreases and the ouput resistance also increases and vice versa so there's no way to have a high increase in gain of ota while maintaining the (...)
Analog Circuit Design :: 24.10.2012 07:07 :: nosrej :: Replies: 3 :: Views: 311
I am designing a 2-stage miller ota like the one in the attachment.
I need 72dB DC-gain, currently I'm stuck on 57.8dB.
I've calculated an expression for the gain:
Av(DC) = gm1(Ro1//Ro3)(Ro5//Ro6)
What do you think of this expression?
My instinct would say:
Av(DC) = gm1(Ro1//Ro3)gm5(Ro5//Ro6)
However the last doesn't
Analog Circuit Design :: 08.04.2013 13:48 :: The_Dutchman :: Replies: 1 :: Views: 269
i need design one SC circuit,the frequency of clock is 1MHZ,VDD=2.5V,the visual GND=1.25v.now i need to firm the ota spec.i want the open-loop gain of ota is 40db at 1mhz,and the PM is 45 degree at 0db. its right?
the common inout voltage how to firm? and its should be ?
Analog Circuit Design :: 15.11.2004 21:40 :: jodenma :: Replies: 1 :: Views: 668
I am designing a fully differential ota. with out CMFB i designed the telescopic ota
with dc bias conditions. Then i designed a SC CMFB circuit.
I want to measure the openloop gain in dB's but i am getting -ve result.
can anybody please help how to design this? Is it able to measure the open loop gain with out using (...)
Analog Circuit Design :: 14.01.2005 12:37 :: pra :: Replies: 12 :: Views: 2617
many ota architectures are suitable for your design. You have not mentioned several things about your ota:
- power supply voltage & target technology (Vt of transistor)
- required output swing
- power dissipation requirement
Analog Circuit Design :: 03.02.2005 18:46 :: borodenkov :: Replies: 8 :: Views: 3013
I've come up with a strange issue.
When simulating a ota with feedback, I simulated the loop gain by cutting the loop at ota input.
In almost all corners, the phase margin will be close to 70degree. However, in fast corner and hot temperature, the loop DC gain is positive. However, transient simulation shows that there (...)
Analog Circuit Design :: 21.03.2005 08:36 :: mike_bihan :: Replies: 7 :: Views: 844
I have recently seen in one publication a low-power SD ADC design with a single stage telescopic cascode ota with gain enchancement. The spec for the ota is:
Technology: 0.18u CMOS
Power supply: ≤1V
DC gain: 80 dB
Bandwidth with 2pF load: 8.5 MHz
However I highly doubt if it possible to realize telescopic (...)
Analog IC Design and Layout :: 21.04.2005 10:24 :: mr_chip :: Replies: 2 :: Views: 1302
I have some doubts regarding the connections for the ota connections used as buffers.
There are two inputs and two outputs of differential ota. so can we directly
connect inputs to outputs (say in+ to out- and in- to out+) to act as a
buffer, or resisters are needed. If resisters are needed, what shud be it that we need to have
Analog Circuit Design :: 02.06.2005 04:22 :: meghna :: Replies: 7 :: Views: 1165
I just don't see any reason to simulate the DC gain of fully differential ota with SC CMFB using spectreRF: you may have some improper settings there which screwed up the ota DC gain. You can do some tricks to get the DC gain of the SC CMFB without using spectreRF.
Analog Circuit Design :: 10.06.2005 02:56 :: willyboy19 :: Replies: 6 :: Views: 1311
I have to design buffer for bandgap voltage=1.2V at 0.35LV technology.
The requrements are low noise, gain>65dB, PM>70deg, GBW>6MHz, SR>10V/uS, VDDmin=2.4V.
Can any one give me advice wich type ota is most approprite for this goal,
Now I try to use folded casscode ota as a first stage, after that invertr with Miller capacitor, and (...)
Analog IC Design and Layout :: 14.06.2005 12:41 :: tyanata :: Replies: 6 :: Views: 952
I'm going to design a two stage folded cascode ota.
first stage is folded cascode(pmos input pair) to provide gain
second stage is common source to increase the output range
compensation is cascode compensation
My question is in my circuit, how to decide the input pair IDS and folded branch IDS.
Is there a design iteration flow for me to
Analog Circuit Design :: 19.06.2005 23:55 :: qslazio :: Replies: 1 :: Views: 1719
For my fully differential fold-cascode ota with SC-CMFB, according to the Ken's paper "Simulating Switched-Capacitor Filters with SpectreRF", I use PSS and can achieve good common mode output voltage results when I let two input signals are disabled. I have used two "vsource" as my two differential inputs, and actually I set ty
Analog IC Design and Layout :: 05.07.2005 05:08 :: ethan :: Replies: 0 :: Views: 925
I had designed a Fully DIfferential Folded Cascode ota. Now I want to characterize this ota for CMRR,PSRR,SFDR,IMD,Slew Rate etc. The measurement setup for some of the above parameters need ota to be configured in Unity Feedback. Now the question is
1. Can I have equal valued RESISTORS in input and feedback side of (...)
Analog Circuit Design :: 04.08.2005 07:01 :: Pack :: Replies: 1 :: Views: 1380
I got a question for the step response configuration, which I have not thought about clearly.
My opamp is single stage fully differential fold-cascode ota to drive capactive load. The CMFB is switch capacitor circuit.
When I tried to test step response, I used unity gain feedback configuration (shown in figure (a)) and go
Analog IC Design and Layout :: 10.08.2005 00:29 :: ethan :: Replies: 3 :: Views: 1232
In my design, the TSMC CM025 process is used.
GBW need to be higher than 500MHz, so the gm of input NMOS is fixed to 2*phi*Cl*700MHz(Cl is the load capacitance, which is 3pF).
AC and PAC simulation shows the GBW is 220MHz(phase margin is 85), much less than 700MHz,then I checked the nondominant pole(located larger than 4.5GHz, i
Analog Circuit Design :: 21.08.2005 03:08 :: wdd :: Replies: 6 :: Views: 865
tsmc 0.35um Process ,, It is a little hard ,
We have implement 80M/12bit pipeline ADC ,
We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like ota . That ota can get more high gain . high BW
Analog IC Design and Layout :: 07.09.2005 02:17 :: mitgrace :: Replies: 4 :: Views: 967
If I want to design a 12bit, 65 or 80MHz pipeline ADC, how can I get the various modules' parameters, such as the sample resolution, ota gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my aim? T
Analog Circuit Design :: 06.09.2005 10:25 :: carlyou :: Replies: 2 :: Views: 952
I had desinged an ota or opamp for switched-capcitor circuits(Pipelined ADC),
but I don't know how to simulate the settling behavior.
As I know, a closed loop circuit composed of capacitors and ota is needed, then apply a step response to the input, we can get the DC error and settling
time(for example, 0.1%) according to the outp
Analog Circuit Design :: 12.09.2005 10:15 :: wdd :: Replies: 4 :: Views: 1164
i am desinging the 10msps pipelined adc.
for this i am desinging the S/H amplifier which is of type fully differential folded cascode with gain boosted opamp.
when i simulated my fully differential folded cascode witout gain boosting ..
i found my gain is 48db. UGB=230Mhz, settling time is 18ns.
but to increase the (...)
Analog IC Design and Layout :: 29.09.2005 07:25 :: manissri :: Replies: 4 :: Views: 966
I have been seeing people use transconductor, gm, and operational-transconductance amplifier (ota) interchangeably, but I am not convinced that they are the same. May I get an opionion on them in terms of:
(1) What are the types of input/outputs (voltage, current, etc)?
(2) What are the impedance of input/outputs (high, low, resistive, capaciti
Analog Circuit Design :: 30.09.2005 15:58 :: DoctorX :: Replies: 4 :: Views: 1158
1. SC CMFB should not affect ur DC gain of ota
2. SC CMFB neet time to settle down to the correct voltage which will
bias the main ota at the right bias point.
3. u had better check bias points of ota, and compare it with SC CMFB & without SC CMFB. if ur result show 20dB degrade, then the bias point must be changed, (...)
Analog Circuit Design :: 04.02.2007 20:54 :: Btrend :: Replies: 4 :: Views: 1290
i am desingning the 12 bit 10 msps pipelined adc. for this i am using for S/H amplifier - folded cascode fully differential with gain boost opamp. i am getting 106db gain, P.M.-61 degree, UGB-261mhz.
my input range is 2Vpp. so my lsb is 2/4096 = 488 uv. my supply is 0 - 5v
my question is when i put my opamp in unity ga
Analog IC Design and Layout :: 22.10.2005 02:09 :: wsy979 :: Replies: 7 :: Views: 880
I want to know if its possible to make a fully differential folded cascode to work without common mode feedback ckt, I mean, I just cannot get to DC bias the ota without the CMFB, it either goes to rail or gnd at the output without it, is it supposed to do so or is it s'thing wrong with my bias? as I am reading someones paper, and he desig
Analog IC Design and Layout :: 03.11.2005 08:52 :: ASICK :: Replies: 3 :: Views: 1107
Attached is the design notes of the CMFB which you are looking for. I would suggest you to look on journal papers as well on the topic of CMFB. From there you will get the ideas on the design aspect and the factors like stability, settling time and so on. ota stand for Operational Transconductance Amplifier which give you the I/V respons
Analog Circuit Design :: 12.11.2005 02:18 :: suria3 :: Replies: 5 :: Views: 1622
Need some feedback on the ota and Voltage amplifier. As we know that Voltage amplifer will have low output impedance and we can say it sense input and output as voltage to voltage whereby ota will have high output impdeance and will sense voltage to current which the gain is transconductance. Both amplifer can be applied input as (...)
Analog Circuit Design :: 16.11.2005 04:28 :: suria3 :: Replies: 3 :: Views: 2611
I am designing a switched-capacitor common feedback full differential operational transconductor amplifier, but I couldn't know how to simulate gain and phase margin of switched-capacitor ota using Cadence tools?
Please give me a advice, thks.
Analog IC Design and Layout :: 07.12.2005 04:21 :: rfic :: Replies: 14 :: Views: 2305
I was requested in my class to design a high-swing Telescopic-cascode fully-differential ota to work in a voltage buffer (shown below) in an ADC. The expected load is shown below.
There is additional loading of 1 pF at each of the ota output nodes (not shown).
The amplifier is required to accommodate a maximum swing of
Analog IC Design and Layout :: 10.12.2005 12:57 :: Mostafa El-Meehi :: Replies: 3 :: Views: 1527
I find that in most current mode controller, the ota is used for the error amplifier instead of the OpAmp. What's the benefit of using ota?
Analog Circuit Design :: 20.12.2005 01:03 :: jwfan :: Replies: 5 :: Views: 1446
What is the gain of a NMOS diff amp with diode connected PMOS loads (like an ota) and a PMOS diff amp with NMOS doide connected loads? I calculated the gain as gm(nmos)/gm(PMOS diode connected) for first case and
gm(PMOS)/gm(NMOS diode connected) for the second case.
Also I am attaching a comparator figure. How would you go about (...)
Analog Circuit Design :: 27.12.2005 05:25 :: suhas_shiv :: Replies: 5 :: Views: 1164
Are there some methods to enhance the gain of an CMOS opamp?
I designing an CMOS opamp. The architecture is a simple ota with an Nmos diff. pair.
Analog IC Design and Layout :: 04.01.2006 12:59 :: leonken :: Replies: 5 :: Views: 1423
1. The input diff. pair Q1 and Q2 must operate in saturate region?
If the Q1 and Q2 operate in subthreshold region, the Dc gain of the diff. pair stage will be reduced?
2. the Q5 and Q7 must operate in saturate region?
3. the Q3 and Q4 must must operate in saturate region?
4. How to bias the Q6? the Q6 operates in saturate region too?
Analog IC Design and Layout :: 13.01.2006 22:36 :: leonken :: Replies: 1 :: Views: 636
Does anybody use such bulk driven ota? How large is the DC gain?
And how to improve the DC gain of such ota?
Does the operating state of M2, M3, M4 and M5 must work in saturature region?
Analog IC Design and Layout :: 14.01.2006 12:02 :: leonken :: Replies: 5 :: Views: 1055
could you tell me what's happening.
I design an ota for LDO and met this problem. When i do .OP and polarize inputs with a given voltage, everything is alright. I've got 100V/V gain and so on.
How to set AC properly to achieve the same results?
I simulate LDO with an open loop. negative input is grounded through small resistor and
Analog Circuit Design :: 18.01.2006 04:30 :: jutek :: Replies: 1 :: Views: 617
can anyone know about how to analysis the systematic offset of basic two-stage ota. It seems quite easy to analysis the systematic offset of basic two-stage opamp, but I don't know how to do in ota?
Analog Circuit Design :: 06.02.2006 22:48 :: chen_Analog :: Replies: 2 :: Views: 1023
would like to ask if anyone has links/references to basic of ota, especially current-mirror ota used in the bioamplifier (like the one used by harrison in his paper for neural amplifier)
one of the thing i want to know is the gain bandwidth equation, which i was told as gm/CL. but when it is compared to two stage op amp, which gbw is (...)
Analog Circuit Design :: 16.02.2006 12:15 :: puyeng :: Replies: 1 :: Views: 588
This configuration is not amplifier because there is not signal path from input to output (no signal flow from drain to gate!!!). Your simulation results are probably incorect, and gain should be 0.
If you wanted to make folded cascode then m1, m2 should not be there...
If you wanted to make m1,m2 diode connected (simple ota amplifier) there is
Analog IC Design and Layout :: 13.03.2006 07:49 :: pixel :: Replies: 12 :: Views: 1949
I have a simple and basic question...
Say I am designing a twe-stage ota. The first stage is for gain and the second stage is for output swing - for example, the first stage is telescopic ota and the second one is a common-source amplifier.
The small-signal gain of the first stage is 1000 and the second (...)
Analog Circuit Design :: 18.03.2006 15:21 :: ee484 :: Replies: 6 :: Views: 1544
I just designed a two-stage ota.
When I compare with and without compensation resistance, their response were very simliar. Actually, without compensation resistance (even marginally better) response turned out to be better phase margin and gain.
(Actually, both responses are the almost identical, but at very high frequency (not frequ
Analog Circuit Design :: 01.04.2006 00:56 :: ee484 :: Replies: 6 :: Views: 991
for a self biased single stage ota, the maximum gain is about 50dB. As the tail current inc, gm inc but ro dec so the gain isn't increase
But u can reach a 60dB gain or higher using a folded cascode or a telescopic cascode otas
Analog IC Design and Layout :: 01.04.2006 04:04 :: eng_Semi :: Replies: 1 :: Views: 941
I browsed almost all the papers of the IEEE of the gain boosted ota, all mostly said about the same thing, just add a Op Amp to increase Rout, like the picture attached.... The problem is how to decide the bias and the Width/Length of the the added Op Amp. I used the Op Amp as same as the original one(the one needed gain boost), the
Analog IC Design and Layout :: 19.04.2006 05:05 :: wdd :: Replies: 4 :: Views: 707
i want to plot the gm of ota ,versus the diffrential input , i am using spectre , can any one help me?
i attached a picture of what i want to draw taken from a papper.
Analog IC Design and Layout :: 22.04.2006 11:37 :: safwatonline :: Replies: 7 :: Views: 1281
Hi, I have a stupid question about integrator noise..
Say an ota has an input-referred noise Vn at it's positive input, and be connected into integrator, the transfer function (1/SRC) has infinite gain at DC, ideally.
So what would input-referred noise Vn be at ota's output?
If I give input a rectangular wave, the (...)
Analog Circuit Design :: 28.04.2006 05:56 :: intuition :: Replies: 0 :: Views: 884
We want to design an ota with a gain of 8000. The first stage is a telescopic cascode and the 2nd stage is simply a CS. We tried to size our transistor but it seems like a mission impossible for us to get such a high gain. Can anybody help us? Thank you very much!
Analog IC Design and Layout :: 01.05.2006 00:51 :: airboss :: Replies: 12 :: Views: 1445
i want to design low gain simple ota?
i need gain about 10-20 V/V with vdd <1.3V,3.3V>
Analog IC Design and Layout :: 03.05.2006 07:17 :: jutek :: Replies: 0 :: Views: 525