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205 Threads found on Ota Gain
Hi All, In the attached frequency locked loop, why is there a need of compensation network formed by Rz,Cz, and Cc? As far as I see there is only one integrator in the closed loop, the ota. The oscillator from vctrl to output frequency is just a gain block since the output variable of interest is just frequency. Single integrator loops are inher
I have designed an ota but its DC gain is -3.4dB. What does this mean? Unit of ota gain is transconductance V/A, so -3.4 dB might translate to 675 mS, or is it 675 ?s, or something different? Generally, the gain and GBW required for a filter depends on the filter topology and designed quality factor.
Hi I have a specification as high gain (80db), fast settling few ns, good PM. I have gone through several topolgoies. One of them I am considering now is from Huijsing's book having a folded mesh with a minimum selector. 130720 If I use Regular PMOS NMOS devices I can't manage to keep all of the transistor in saturati
Hi, I've build an RC integrator (28nm CMOS): A nonideal current source is sunk into an ota with an integration cap in feedback. fu=400MHz, DC gain~73.38dB. The step response looks as expected (time constant ~238.7ns, DC gain ~73.38dB): 129607 For low frequencies (e.g. 6MHz, 10MHz, ...) the tran output is precicel
Hi, Can anyone suggest me DC offset cancellation circuit for high frequency application (50 MHz) circuits. I used the continuous time feedback model circuit include LPF+ota, but it degrades the opamp gain and linearity at common mode output votlage range. I am not sure the sampling clock based DCOC will work for high speed applications or n
Hi I m designing a two stage ota using gm/id method. I have a problem in picking the length of the transistor. I have chosen a large length for large gain and good matching. And my ft is around 10 times the UGB of the ota. Are there any relationship between ft of the transistor and UGB of the amplifier. I mean is there any thumb rule that ft (...)
I had some questions in LDO design when it comes to the error amplifier (EA) 1) Why is it advantageous to use otas when designing the error amplifier in LDOs? I know that we utilize ota when we are driving small capacitive loads and voltage amplifiers when driving high impedance loads. Since the output of the EA is connected to the gate of the
It's quite a good value; some papers
I have designed a biquad ota-C low pass filter, tunable from frequency from a few Hz to few KHz. However if I increase the tuning current, although the frequency increases but the dc gain decreases. Please help me to understand why this could be happening and what could be the possible solution for this. Thanks in advance.[/
140dB (!!) is a voltage gain of 100 million. Then an ota with an input offset voltage of 5mV will produce an output of 500,000V when its input is zero! What about low frequency noise being amplified 100 million times? Don't be silly.
It depends on how you look at it. If you consider the opamp to be voltage controlled voltage source, then the output impedance is very low. If you consider it to be voltage controlled current source (operational transconductance amplifier, ota), then the output impedance should be very high. Choose the correct model for your analysis. Both are one
OK!! how to estimate ota targets of design? especially for a 12b pipeline adc using 10 1.5bit/stage HOW MUCH gain HOW MUCH BANDWIDTH HOW MUCH LOAD CAPACITOR oh god would you please anyone share some experience? that's why does exist isn't it? if I'm wrong let me know.
Hi, I have a boubt in the second stage of fully differential output ota. I used PMOS loads, Is it double size needed in the second stage than 1stage of PMOS loads? Why PMOS loads needed double size than 1st stage? Thanks!
Hello. I am designing a tunable high pass filter : the signal goes through a cap then into a grounded resistor. To make it tunable, the res is actually a differential inputs/single-ended output ota, fed through the invert input, and with a feedback from the output to the invert input (like
Hello all, I understand that the larger the gain the less the effect of offset since the more its impact on the output is supressed. But does offset itself reduce gain? Say my input diff pair contributes significant Vt mismatch leading to offset. Would this reduce my Aol? Thanks, Diarmuid
Hi guys. I am designing a Symmetrical ota and I am facing a problem. The maximum gain that I am able to get is around 50dB with a current consumption of 700uA. The GBW is aprox. 130MHz. The circuit that I am talking about is this I wo
Hello! I extract this integrator from a paper which is used in AGC circuits to produce control voltage of VGA. I can not understand how it can perform as an integrator because it is a symmetrical CMOS ota which amplifies the differnce between Vpeak and Vref and if we consider the output capacitor as the capacitor of integrator an amplifier which w
Change your amplifier to ota (differential pair loaded by current mirrors) or design it as floded cascode.
This is a simple two stage ota ... with fully differential output at first stage and single ended at the second stage. gain will be approx gm^2 (ro || ro)^2 .. assuming the all the ro and gms are same. The MOS arm connected to VB2 is used for CMFB (Common Mode Feedback) as the first stage is fully differential. Working of the CMFB Loop (as
I have an ota with an op-amp I-V converter giving output at unity gain on a 20Hz +/- 5V sine wave input. It works fine, basic circuit is I wanted to swap the op amp I-V converter for a transistor output -
Dear all, I designed a current mirror. Some papers such as said the DC gain is A0 = gm1 x B x ro3. I computed it with mine, but, in the simulation, the B factor doesn't seems to have any impact on the DC gain, only on the GBW. Not sure if there
Hi I want to use an ota integrator in a dual slope ADC. But since the input signal is large signal wont it change the gm for different levels? Thanks Salil
PM requirement is calculated with loop gain. For a closed-loop system with a closed loop gain larger than 1, ota PM requirement is lower, i.e., can be lower than 45 degree. A buffer (closed gain is 1) has the worst situation and requires largest PM. I do not know how to calculate a current integrator loop (...)
Hi, I am using the classic folded cascode one stage ota for the specification: gain=70dB, phase margin=60 degree and Unit gain frequency=90M Hz. load capacitor =50p F 1. How to increase phase margin without decreasing gain, unit gain frequency and also without increasing load capacitor? My (...)
I m using GATEWAY to design ota for bioamplifiers .how to find out the gain ,slew rate, bandwidth ,cmrr psrr ,power consumption in smartview?
Hi, I am designing a 2-stage miller ota like the one in the attachment. I need 72dB DC-gain, currently I'm stuck on 57.8dB. I've calculated an expression for the gain: Av(DC) = gm1(Ro1//Ro3)(Ro5//Ro6) What do you think of this expression? My instinct would say: Av(DC) = gm1(Ro1//Ro3)gm5(Ro5//Ro6) However the last doesn't
Hello, I'm drawing a 2 stage fully differential miller ota with 2 CMFB networks. These CMFB networks are ideal and contain a vcvs with a gain "Acm". However, when I put 2 instances on my schematic and use the ADE (Analog Design Environment) to retrieve the variables I only get 1 variable Acm for the 2 blocks. I wish to control them independently
I'm going to design a two stage folded cascode ota. first stage is folded cascode(nmos input pair) to provide gain second stage is common source to increase the output range compensation is cascode compensation My question is in my circuit, how to find poles and zeroes? It had a compex trasformer Eq. & I couldnt simple it. Thanks a
I have a major problem and i am out of ideas so any suggestions will be great.... below is the image of the circuit i am trying to simulate: its for an ota using 90nm technology: the requirements are 1. high linearity 2. high gain 3.low noise... the only difference in my circuit from the one in the image is that i am using all PMOSs 1) http
I am designing an ota but i am getting a very small linearity range... i need to increase the linearity.. I added passive resistors at the differential pair but i am not getting any improvements... so any ideas??? Thanks
In the architecture that you have shown, there are effectively two loops. One through just a single diode and other through a larger diode in series with the resistor R3. One of the loops will be in positive feedback and other will be in negative feedback. To obtain overall negative feedback for stability, you need the larger gain path to be in neg
Hello Analog guys I designed a current mirror ota with a partial positive feedback, the circuit is like the one I attached from Gregorian book, Figure Nr. 3.41. After I finished the design , I have simulated the circuit with and without the positive feedback as shown in the first and second image respectively. Here I have a couple of ques
Hello, I need to design an ota in 0.13 ?m CMOS (1.2 V) technology. My specs are: Av=80 db GBW>250 MHz. Slew rate > 100v/?s It is possible with a single telescopic stage to achieve this results? Any idea about the power need for achieve this specs? Regards
I have been trying to find some papers on this but am coming up short. I have heard that if you place a very broad band ota in parallel with a narrow band, the narrow band helps keep the loop stable. But what is the exact impact? If ota1 has BW of x and ota has bw of 3x, is the bandwidth of the system, 4x/2=2x? or is it 4x? I also (...)
Hi!, We have just designed a 2 stage ota with a cascoded differential pair as the first stage and a common source amplifier as the second stage. The gain is 59.3dB and we need to measure the slew rate. Can anyone please tell me how to go about measuring the slew rate? The method that we were using is to supply a 1Vpp pulse at the input and us
Am I understanding this correctly. I have an ota and given that the f3db is 60 and I want to increase its gain but the as the gain increases the value of the f3db decreases and the ouput resistance also increases and vice versa so there's no way to have a high increase in gain of ota while maintaining the (...)
Hello I am designing a class A amplifier to put later on the output of my operation amplifier, I have found that the output is not symmetrical about the half of the supply voltage as it the case of my op-amp, you can see that the gain at VDD= 2.5 the gain is zero ehich will kill the gain of the op-amp when I connect it. So how can I (...)
Dear friend I am designing a fully differential amplifier for the first time. I would design the CMFB for the ota shown in image I would use continuous time CMFB, while all the references I have only discussed the SC CMFB for this circuit. If any one can help me I will be tha
The problem isn't clear. You are showing an ota topology in post #3, it basically "mirrors" the bias current of the input stage into the output node (possibly with a gain factor in the current sources), thus the maximum output current will be symmetrical and meet your intention of symmetrical slew rate with capacitive load.
I am a beginner in Cadence,I am designing a two stage ota. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output shows amplification,but i get a triangle wave with ac ga
Your assumption can be easily verified by comparing the inverting OP gain expression A = -Z2/Z1 with ota gain A = gm*Z2.
Dear Friends: Several months ago,I have designed a two-stage ota and fabricated in 0.18um CMOS technology.Now,I faced with some problems in testing my ota.I have already worked out some close-loop test procedures for the ota,however,recently I have seen some papers showing their open-loop test results using network analyzer.I have no idea (...)
Hi, I have very basic question in mind. How do we decide DC gain of OPAMP or ota irrespective of application ? Does it decide on basis of settling error voltage or it has some other relation. If you have any good and basic refernce for it. then, please share it.
Hi Varunkant2k: Thanks for your help. Voltage mode have High impedance nod and the High impedance you mentioned is the Rout of the EA? And now I am confused about the function of EA, usually, its function is described as "amplify the error signal ", however, after adding the compensation net, the gain is determined by the ratio of
Your are mixing up ota (current output, gain is tranconductance) and OPA (voltage output, voltage gain) .
Hello guys. i am designing a ota in weak inversion... and the voltage gain looks good but the gm behavior shows very low values at low frequencies it this normal? I calcuate that from the ratio of the output current over the voltage input. It this correct? 73483 its only for gathering the idea for weak inversion
HI i am new to the analog based circuit design.. I have been designing folded cascode ota for 9-bit 200MSPS pipeline ADC in 90nm CMOS technology with the following specifications power supply =1v dc gain= 62db unity gain b/w =1.162Ghz phase margin =68.38deg But when i simulate the following ota for dc (...)
Hello everyone, I have designed ota for hearing aid application. I want to measure THD of ota. How can i measure it? The value that i get is it in percentage or not? Another query is that gain of the ota is the ratio of output current to input voltage or ratio of output voltage to input voltage? please help me i (...)
I am simulating a fully differential ota for a class project. I have the basic specs where I would like them (like gain,BW,PM). But, when I run my transient sims, I am seeing Vout and Voutb are not symmetric. Both are pulled up to about the common mode votlage of 1.1V and then are clipped. My differential output looks okay (Does this imply it i
Hi, We have designed 14 bit pipelined ADC, which is working up to 120MSPS at schematic level. But, after post layout, I see a settling gets delayed in MDAC (gain of 4) output. I see the dip before raising or very under damped behaviour. I found ota layout causing more than 1.5 pf extra parasitic capacitance in layout.