1000 Threads found on edaboard.com: Ota Gain
Am I understanding this correctly. I have an ota and given that the f3db is 60 and I want to increase its gain but the as the gain increases the value of the f3db decreases and the ouput resistance also increases and vice versa so there's no way to have a high increase in gain of ota while maintaining the (...)
Analog Circuit Design :: 10-24-2012 07:07 :: nosrej :: Replies: 3 :: Views: 342
I am designing a 2-stage miller ota like the one in the attachment.
I need 72dB DC-gain, currently I'm stuck on 57.8dB.
I've calculated an expression for the gain:
Av(DC) = gm1(Ro1//Ro3)(Ro5//Ro6)
What do you think of this expression?
My instinct would say:
Av(DC) = gm1(Ro1//Ro3)gm5(Ro5//Ro6)
However the last doesn't
Analog Circuit Design :: 04-08-2013 13:48 :: The_Dutchman :: Replies: 1 :: Views: 322
How to determine transistor size of folded cascode ota(gain=80db,fu=30Mhz)?
Analog Circuit Design :: 02-25-2004 20:47 :: rose_song :: Replies: 5 :: Views: 3463
iam designing a fully differential folded cascode ota
gain: 66 db
Vdd: 3.3 V
power dissipation 3.7 mW
BW: 980 Mhz
I have used switched capacitor CMFB(Common Mode Feed Back)
Problem: Iam getting gain of 54 dB and power dissipation of 2.7mW but the problem is that the gain curve is not crossing 0dB it reaches a (...)
Analog Circuit Design :: 01-22-2008 05:21 :: shobhit :: Replies: 6 :: Views: 2498
i am designing a 3rd order Sigma-Delta ADC for Audio applications. The specs would be something like 18bits, THD<0.1%, OSR = 256.
What will be an estimate of the ota gain and BW, and why?
Analog Circuit Design :: 10-20-2008 17:32 :: tapanshahp :: Replies: 0 :: Views: 457
1) I want to get a relation between the Vref variation due to the temperature variation and the ota gain of the bandgap reference source shown in the figure.
Could I make a small signal analysis???
something like that:
2) I saw, in simulations, a voltage variation between the input terminals of the ota due (...)
Analog Circuit Design :: 04-23-2009 14:26 :: jc2 :: Replies: 0 :: Views: 849
I am designing an ota for my GmC filter, and I have question regarding the THD simulation.
In, papers, I find THD results for the ota while sweeping input signal amplitude. However, I am not sure if the output is left open for this simulation. for example, if the ota gain is 40dB, then for a 100mVpp input which very often (...)
Analog IC Design and Layout :: 07-14-2010 02:24 :: LvW :: Replies: 1 :: Views: 663
My gain is an expression for a four stage ota gain, which i want to sweep with my input Common mode level. I guess there is little clue to what-to-do in your reply !
Analog IC Design and Layout :: 08-28-2010 13:34 :: EmbdASIC :: Replies: 4 :: Views: 646
I designed a current mirror. Some papers such as said the DC gain is
A0 = gm1 x B x ro3.
I computed it with mine, but, in the simulation, the B factor doesn't seems to have any impact on the DC gain, only on the GBW. Not sure if there
Analog IC Design and Layout :: 10-04-2013 12:42 :: Fabien :: Replies: 5 :: Views: 529
Thank you guys I agree that this is not a Op-amp. but can you provide some inside about the ac gain? How av=R2/R1?
Like any Class A amplifier small signal voltage gain is always Rc/Re.
Except this is used for voltage controlled current amp or ota. In the case of the classic CA3080 ota , Re =0, so internal rE
Analog IC Design and Layout :: 11-27-2014 11:36 :: SunnySkyguy :: Replies: 7 :: Views: 523
tsmc 0.35um Process ,, It is a little hard ,
We have implement 80M/12bit pipeline ADC ,
We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like ota . That ota can get more high gain . high BW
Analog IC Design and Layout :: 09-07-2005 02:17 :: mitgrace :: Replies: 4 :: Views: 989
If I want to design a 12bit, 65 or 80MHz pipeline ADC, how can I get the various modules' parameters, such as the sample resolution, ota gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my aim? T
Analog Circuit Design :: 09-06-2005 10:25 :: carlyou :: Replies: 2 :: Views: 996
UGF must be less than 20% of switching frequency.
Added after 3 minutes:
ota gain 60dB, Large UGF will get better Line and Load transenit response.
Analog IC Design and Layout :: 01-19-2007 10:49 :: mark_nctu :: Replies: 6 :: Views: 1630
the bootstrapped technique(fig.1) can enhance the gain in the ota application. but the bootstrap introduces a positive feedback loop in the ota. How about its stability?
If the closed loop negative feedback is strong enough to overcome the positive feedback introduced by bootstrap, is the ota stable?
then fig.2 is the (...)
Analog Circuit Design :: 07-24-2008 04:53 :: sunbeam :: Replies: 1 :: Views: 583
Your assumption can be easily verified by comparing the inverting OP gain expression A = -Z2/Z1 with ota gain A = gm*Z2.
Analog Circuit Design :: 09-13-2012 14:06 :: FvM :: Replies: 1 :: Views: 336
I just don't see any reason to simulate the DC gain of fully differential ota with SC CMFB using spectreRF: you may have some improper settings there which screwed up the ota DC gain. You can do some tricks to get the DC gain of the SC CMFB without using spectreRF.
Analog Circuit Design :: 06-10-2005 02:56 :: willyboy19 :: Replies: 6 :: Views: 1367
1. SC CMFB should not affect ur DC gain of ota
2. SC CMFB neet time to settle down to the correct voltage which will
bias the main ota at the right bias point.
3. u had better check bias points of ota, and compare it with SC CMFB & without SC CMFB. if ur result show 20dB degrade, then the bias point must be changed, (...)
Analog Circuit Design :: 02-04-2007 20:54 :: Btrend :: Replies: 4 :: Views: 1332
I have a simple and basic question...
Say I am designing a twe-stage ota. The first stage is for gain and the second stage is for output swing - for example, the first stage is telescopic ota and the second one is a common-source amplifier.
The small-signal gain of the first stage is 1000 and the second (...)
Analog Circuit Design :: 03-18-2006 15:21 :: ee484 :: Replies: 6 :: Views: 1594
i was wondering
1-what is the max. gain for a single stage ota,
2-and whether if this gain always increase with increasing the tail current (gm=2I/Veff)? ,
3-also when do i say this stage is not enough ,(i.e. i got max. use of it and i need another stage).
Analog IC Design and Layout :: 04-01-2006 01:56 :: safwatonline :: Replies: 1 :: Views: 1025
We want to design an ota with a gain of 8000. The first stage is a telescopic cascode and the 2nd stage is simply a CS. We tried to size our transistor but it seems like a mission impossible for us to get such a high gain. Can anybody help us? Thank you very much
Just use the gain-boost to increase the (...)
Analog IC Design and Layout :: 05-01-2006 06:46 :: bastos4321 :: Replies: 12 :: Views: 1468
i want to design low gain simple ota?
i need gain about 10-20 V/V with vdd <1.3V,3.3V>
Analog IC Design and Layout :: 05-03-2006 07:17 :: jutek :: Replies: 0 :: Views: 570
assume to design a telescopic fully differential ota with gain boost, the gain boost stages will be implemented in folded cascode fully differential topology, one for the upper side, andother for the downside. my question is: is it necessary to make sure that these two gain boosted stages have very close gain?
Analog Circuit Design :: 02-16-2007 23:52 :: asueee0 :: Replies: 0 :: Views: 547
How to design gain Boosting AMP used in ota
I am looking for ur help to design CS AMP which used in gain Boosting AMP or I have to design it before I start design hole ota or just I combined them together and start simulation directly
Analog Circuit Design :: 10-13-2007 15:11 :: wael_wael :: Replies: 10 :: Views: 1407
when i simulated the ota in the picture
sometimes i found the gain was very low
it was about 30dB
even the gain at the output(the second stage) was samller than the first stage
Can anybody tell me why this happenned?
Analog Circuit Design :: 03-03-2008 10:01 :: frankwen :: Replies: 3 :: Views: 1064
It could be that your ota is not strong enough to drive the input capacitance of your second stage.
What is the connection? You should upload a simplified schematic to allow others to debug your issue.
Analog IC Design and Layout :: 03-20-2008 19:43 :: electronrancher :: Replies: 10 :: Views: 1342
If you are using a typical two stage miller ota then 50dB is quite low as ur 1st stage itself can provide upto 40dB. Look into ur second stage for adding up some more gain.
If ur ota is folded cascode one then trying gain boosting in cascodes...
for this u can refer to paper by "Bult and Geeleen" " A fast settling 90dB (...)
Analog Circuit Design :: 05-21-2008 05:06 :: ashish_chauhan :: Replies: 10 :: Views: 1392
In order to improve the gain of an ota, the gain-boosting method is an useful thchnique.
what is the relationship between main ota, and "A" shown in the figure?
Supposed that the UGB of main ota is 200MHz, how about the opamp "A"?
Is any systematic calculation
Analog Circuit Design :: 07-17-2008 11:31 :: nathanee :: Replies: 4 :: Views: 1559
i am designing a gain boosted cascode folded opamp and i have done with my
main amplifier of 40dB and 300MHz. right now, i am doing the gain boosted ota.
the paper that i have read says that the input and ouput of the gain boosted
opamp are to be set, marked as red in the figure.
Analog Circuit Design :: 09-21-2009 05:20 :: ella1923 :: Replies: 1 :: Views: 2943
I am trying to design an ota in 0.18 ?m CMOS technology. My targets are:
ω (unity gain)>1.2GHz
I want to know: is it possible to design a telescopic ota WITHOUT gain boosting scheme to reach the above metnioned characteristics?
I like to design a very simple traditional telescopic (...)
Analog Circuit Design :: 05-05-2010 13:27 :: gigalove :: Replies: 3 :: Views: 780
the attached is a booster amp used a gain boosted ota, from one berkeley student's project report.
I don't understand why he used cascoded tail current source with one transistor controlled by biasing network and another by cmfb. Any particular advantage of this topology compared to normal cmfb tail current source (two parallel transi
Analog IC Design and Layout :: 06-30-2010 18:01 :: jszair :: Replies: 0 :: Views: 521
I have designed a capacitive feedback ota ( ota is folded cascode single stage ota with ideal CMFB). When I simulate the loop gain of ota (using iprobe and stb analysis in cadence) I get a 'High Pass' response at low frequencies.
I am not sure why this is happening. Please help to solve this issue. (...)
Analog IC Design and Layout :: 09-29-2010 15:46 :: niranjan1984 :: Replies: 3 :: Views: 1173
I have designed capacitive feedback fully differentail ota. I am trying to simulate loop gain and step response of ota. Fig1 shows the test bench used
Fig2 shows the loop gain and fig3 shows the step response. I have following questions
1. Why loop gain curve is not flat at the beginning? Theory (...)
Analog IC Design and Layout :: 09-30-2010 02:34 :: niranjan1984 :: Replies: 9 :: Views: 1383
Your ota is railed: one output is at 1.3V while the other is at 0.66V. The problem seems to be at the input differential pair. Are your transistors sized properly?
Analog IC Design and Layout :: 10-27-2010 23:45 :: JoannesPaulus :: Replies: 7 :: Views: 1167
I'm attaching schematic of differential ended ota(with ideal CMFB).Vin+ Vin- are my inputs and Out+ Out- are my outputs.I want to configure my ota in unity gain mode to calculate the settling time of ota.Please guide me.
I'm currently using ideal CMFB in my schematic, does this effect the settling time of (...)
Analog IC Design and Layout :: 04-05-2011 01:27 :: Ravinder487 :: Replies: 1 :: Views: 1171
HI i am new to the analog based circuit design.. I have been designing folded cascode ota for 9-bit 200MSPS pipeline ADC in 90nm CMOS technology with the following specifications
power supply =1v
dc gain= 62db
unity gain b/w =1.162Ghz
phase margin =68.38deg
But when i simulate the following ota for dc (...)
Analog IC Design and Layout :: 04-29-2012 08:06 :: nari reddy :: Replies: 1 :: Views: 635
I have very basic question in mind. How do we decide DC gain of OPAMP or ota irrespective of application ? Does it decide on basis of settling error voltage or it has some other relation.
If you have any good and basic refernce for it. then, please share it.
Analog Circuit Design :: 07-22-2012 08:58 :: girih192002 :: Replies: 5 :: Views: 425
I am a beginner in Cadence,I am designing a two stage ota. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output shows amplification,but i get a triangle wave with ac ga
Analog Circuit Design :: 09-28-2012 08:41 :: ncj :: Replies: 0 :: Views: 370
I need to design an ota in 0.13 ?m CMOS (1.2 V) technology. My specs are:
Slew rate > 100v/?s
It is possible with a single telescopic stage to achieve this results?
Any idea about the power need for achieve this specs?
Analog IC Design and Layout :: 01-14-2013 13:05 :: pcca :: Replies: 10 :: Views: 591
i need design one SC circuit,the frequency of clock is 1MHZ,VDD=2.5V,the visual GND=1.25v.now i need to firm the ota spec.i want the open-loop gain of ota is 40db at 1mhz,and the PM is 45 degree at 0db. its right?
the common inout voltage how to firm? and its should be ?
Analog Circuit Design :: 11-15-2004 21:40 :: jodenma :: Replies: 1 :: Views: 691
many ota architectures are suitable for your design. You have not mentioned several things about your ota:
- power supply voltage & target technology (Vt of transistor)
- required output swing
- power dissipation requirement
Analog Circuit Design :: 02-03-2005 18:46 :: borodenkov :: Replies: 8 :: Views: 3130
I've come up with a strange issue.
When simulating a ota with feedback, I simulated the loop gain by cutting the loop at ota input.
In almost all corners, the phase margin will be close to 70degree. However, in fast corner and hot temperature, the loop DC gain is positive. However, transient simulation shows that there (...)
Analog Circuit Design :: 03-21-2005 08:36 :: mike_bihan :: Replies: 7 :: Views: 871
I have recently seen in one publication a low-power SD ADC design with a single stage telescopic cascode ota with gain enchancement. The spec for the ota is:
Technology: 0.18u CMOS
Power supply: ≤1V
DC gain: 80 dB
Bandwidth with 2pF load: 8.5 MHz
However I highly doubt if it possible to realize telescopic (...)
Analog IC Design and Layout :: 04-21-2005 10:24 :: mr_chip :: Replies: 2 :: Views: 1345
I have to design buffer for bandgap voltage=1.2V at 0.35LV technology.
The requrements are low noise, gain>65dB, PM>70deg, GBW>6MHz, SR>10V/uS, VDDmin=2.4V.
Can any one give me advice wich type ota is most approprite for this goal,
Now I try to use folded casscode ota as a first stage, after that invertr with Miller capacitor, and (...)
Analog IC Design and Layout :: 06-14-2005 12:41 :: tyanata :: Replies: 6 :: Views: 992
I'm going to design a two stage folded cascode ota.
first stage is folded cascode(pmos input pair) to provide gain
second stage is common source to increase the output range
compensation is cascode compensation
My question is in my circuit, how to decide the input pair IDS and folded branch IDS.
Is there a design iteration flow for me to
Analog Circuit Design :: 06-19-2005 23:55 :: qslazio :: Replies: 1 :: Views: 1805
For my fully differential fold-cascode ota with SC-CMFB, according to the Ken's paper "Simulating Switched-Capacitor Filters with SpectreRF", I use PSS and can achieve good common mode output voltage results when I let two input signals are disabled. I have used two "vsource" as my two differential inputs, and actually I set ty
Analog IC Design and Layout :: 07-05-2005 05:08 :: ethan :: Replies: 0 :: Views: 964
I had designed a Fully DIfferential Folded Cascode ota. Now I want to characterize this ota for CMRR,PSRR,SFDR,IMD,Slew Rate etc. The measurement setup for some of the above parameters need ota to be configured in Unity Feedback. Now the question is
1. Can I have equal valued RESISTORS in input and feedback side of (...)
Analog Circuit Design :: 08-04-2005 07:01 :: Pack :: Replies: 1 :: Views: 1421
I got a question for the step response configuration, which I have not thought about clearly.
My opamp is single stage fully differential fold-cascode ota to drive capactive load. The CMFB is switch capacitor circuit.
When I tried to test step response, I used unity gain feedback configuration (shown in figure (a)) and go
Analog IC Design and Layout :: 08-10-2005 00:29 :: ethan :: Replies: 3 :: Views: 1278
I had desinged an ota or opamp for switched-capcitor circuits(Pipelined ADC),
but I don't know how to simulate the settling behavior.
As I know, a closed loop circuit composed of capacitors and ota is needed, then apply a step response to the input, we can get the DC error and settling
time(for example, 0.1%) according to the outp
Analog Circuit Design :: 09-12-2005 10:15 :: wdd :: Replies: 4 :: Views: 1216
i am desinging the 10msps pipelined adc.
for this i am desinging the S/H amplifier which is of type fully differential folded cascode with gain boosted opamp.
when i simulated my fully differential folded cascode witout gain boosting ..
i found my gain is 48db. UGB=230Mhz, settling time is 18ns.
but to increase the (...)
Analog IC Design and Layout :: 09-29-2005 07:25 :: manissri :: Replies: 4 :: Views: 1013
I have been seeing people use transconductor, gm, and operational-transconductance amplifier (ota) interchangeably, but I am not convinced that they are the same. May I get an opionion on them in terms of:
(1) What are the types of input/outputs (voltage, current, etc)?
(2) What are the impedance of input/outputs (high, low, resistive, capaciti
Analog Circuit Design :: 09-30-2005 15:58 :: DoctorX :: Replies: 4 :: Views: 1231