1000 Threads found on edaboard.com: Overlapping Clock
from a single phase clock how to generate a two phase differential non-overlapping clock...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-20-2006 02:00 :: deepa :: Replies: 7 :: Views: 1459
can anyone plz tell me how to construct a pseudo two phase non overlapping clock generator using cmos transmission gates or using 2 input nor gates...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-18-2006 16:44 :: hawks4peace :: Replies: 1 :: Views: 1493
I need three phase non-overlapping clock paper or other material, not two phase.
I can not find anything about three phase non-overlap clock, could you please share yours?
Analog Circuit Design :: 11-27-2007 19:44 :: iamxo :: Replies: 2 :: Views: 1411
I would like to know some materials about current spikes resulting from overlapping clock. Want to figure out the reason or analysis.
Analog Circuit Design :: 01-20-2009 09:48 :: yschuang :: Replies: 1 :: Views: 473
I think the second one can work too.
I am trying to make a two-phase non overlapping clock generator for my SC integrator. can u plz tell me why people use such a professional clock generator as this
Analog IC Design and Layout :: 10-17-2011 04:30 :: leo_o2 :: Replies: 7 :: Views: 886
Im not so experienced with non-overlapping clock generators so have 2 probably quite basic questions on them:
Going by the topology of two cross-coupled NOR gates with even numbers of inverters inserted in their feedback paths:
- Are the inverters inserted to increase the non-overlapping durations?
- Could you not just (...)
Analog IC Design and Layout :: 06-20-2013 04:01 :: diarmuid :: Replies: 3 :: Views: 329
Good day EDA fellows...
I'm having this 3 output non-overlapping clock generator circuit.
I'm having concern regarding those 2 MOS (drain and source connected). What's their purpose?
Thank you very much for spending time on this
Analog Circuit Design :: 09-30-2010 07:45 :: allennlowaton :: Replies: 5 :: Views: 1957
Hello sir. I am reading about lockup latches. Sir how exactly lockup cell removes the hold violation? And sir why we do check setup analysis in next clock and not at the same clock? If first clock for destination clock laging the source clock and during that time if data can settle then what will be happen? (...)
ASIC Design Methodologies and Tools (Digital) :: 09-10-2013 05:18 :: deepen talati :: Replies: 0 :: Views: 291
A popular clocking scheme is the two-phase clock, which consists of two signals called 1 and 2 that alternate being on and off .These values are generally nonoverlapping such that they are never both on at the same time (one must go off before the other goes on).
Analog IC Design and Layout :: 05-17-2006 00:16 :: analogartist :: Replies: 2 :: Views: 2584
Can anyone provide me the reference to generate the non-overlapping clock generator (with earl phasing) and a divide by 8 circuit?
Analog Circuit Design :: 01-08-2008 05:59 :: rampat :: Replies: 2 :: Views: 462
If this is to be implemented inside an IC and assuming the following
(a) clock is of the order of MHz
(b) This is a really good Foundry process
Feed the clock into a non overlapping clock generator that generates two non overlapping phases. This can be done with two NOR gates and 3 or 5 or (...)
Analog Circuit Design :: 09-21-2009 07:26 :: Colbhaidh :: Replies: 9 :: Views: 4226
I am designing a CMOS Dickson charge pump. The charge pump works fine when using ideal non-overlapping clock sources (vdc from analogLib).
The problem arises when using a clock oscillator (or even an ideal source) and apply it to a circuit to generate the 2 non-overlapping clocks.
Analog IC Design and Layout :: 02-28-2011 05:21 :: khaled2k :: Replies: 15 :: Views: 1562
You will always find a glitch at every transition. But how major is it depends on where the code is changing. For example, in a 4 bit DAC, you will see a max glitch where there is a transition of code from 0111 to 1000. But you will also notice glitches during the 0011 to 0100 transition and so on. The reason for these glitches are :
Analog Circuit Design :: 04-06-2005 02:26 :: Vamsi Mocherla :: Replies: 10 :: Views: 811
As far as I can see, you have two options to solve the problem:
1) Digital solution: digitize these two inputs and perform the subtraction in digital domain, or
2) Use switched capacitor circuitry with two non-overlapping clock phase to get the V1-V2 function you required, if the sampled nature of signal processing is allowed.
Other pure ana
Analog IC Design and Layout :: 04-08-2005 03:38 :: willyboy19 :: Replies: 12 :: Views: 1056
Thanks for your input!
If we do not consider the overhead of two-phase non-overlapping clock and suppose the gain accuracy is not very critical, what is the criterion of choosing opamp structure between sc circuitry and conventional method ?
Analog Circuit Design :: 07-17-2005 22:42 :: jordan76 :: Replies: 6 :: Views: 1789
But, the non-overlapping clock generates the non-50% duty cycle inherently.
The sampling peroid is not equal for the two phases.
How about this effect?
Analog Circuit Design :: 08-12-2005 01:50 :: hebu :: Replies: 7 :: Views: 1101
How long we have to design the time gap between two phases. For example,
the clock frequency is 1MHz, how about 3nS time gap? it's enough?
2)The common mode bias to switch
Can we only use resistor divider to generate a voltage to bias the common mode
node of switch? or, we need to make a low impedance to the (...)
Analog Circuit Design :: 09-16-2005 13:42 :: hebu :: Replies: 0 :: Views: 710
i need schematic & W/l values , Trade off between speed & powerconsumption
Electronic Elementary Questions :: 03-24-2006 10:36 :: RomiOoOo2013 :: Replies: 0 :: Views: 658
well, i THINK that this is usually dependent on the clock frequency, also the kind of application this dff is used in.
like if u are talking about multi-phase clock generator used in ADCs then the trise and tfall have to be lower than a certain limit not to violate the non-overlapping clock condition and also not to cut (...)
Analog IC Design and Layout :: 12-14-2007 06:35 :: safwatonline :: Replies: 7 :: Views: 1135
Here are some of the guidelines that should be followed in High speed PCB routing
Give a lot of consideration to component placement and orientation.
• Avoid overlapping clock harmonics. Make a harmonic table for each clock.
• clock signal loop area must be kept as small as possible. Get (...)
PCB Routing Schematic Layout software and Simulation :: 03-12-2008 01:51 :: sandhya.im :: Replies: 3 :: Views: 1221
You can use Switched-capacitor type with non-overlapping clock for up to 13~4bit resolution.(two stage opamp or gain booster)
For more resolution, you can use gate-bootstrapping technique.
There are many helpful thing in S.Lee 's thesis.
Analog Circuit Design :: 04-03-2008 19:20 :: ljy4468 :: Replies: 2 :: Views: 523
I'm designing an integrated voltage doubler. The power is in the range of 20 uW. The supply voltage is approx. 2 times bigger than Vth. Since I use integrated capacitors, I have ~20% of parasitics associated with them. The other losses stem from parasitics of MOSFET switches. I use a non-overlapping clock.
:arrow: I get consider
Analog IC Design and Layout :: 04-10-2008 10:39 :: malizevzek :: Replies: 1 :: Views: 766
Pls visit this link
Some common Design Tips are here....
Guidelines for the design and layout of high-speed digital logic PCBs.
• Give a lot of consideration to component placement and orientation.
• Avoid overlapping clock harmonics. Make a harmonic table for each clock.
PCB Routing Schematic Layout software and Simulation :: 05-16-2008 05:08 :: sandhya.im :: Replies: 8 :: Views: 2983
you can find answer in almost every textbook. normally you need to generate nonoverlapping logic first, by delaying the original clock and then pass it through NAND gate with the original signal. or more complicated one.
then you may estimate the load of control logic, and scale the output buffer.
Analog IC Design and Layout :: 08-06-2008 09:16 :: nus_lin :: Replies: 14 :: Views: 2907
i have to use of Non overlapping clock for S/H.all pieces of this project is real thus i must define real pulse source that have rise and fall time.i don't know that how specify these times,can we define percentage of pulse width for rise/fall time?
(for example define rise time=0.1% Pulse width)
Analog Circuit Design :: 02-10-2009 15:33 :: Monady :: Replies: 2 :: Views: 677
I am designing the non-overlapping clock generation block now for sigma delta ADC. Since our sampling frequency is low (~1MHz) and our technology is fast(0.13um), it's kind of difficult to seperate the clock edges. One way to increase the delay is to use big capacitor on the signal path, but this increase area and current (...)
Analog IC Design and Layout :: 04-27-2009 23:09 :: sapphire :: Replies: 2 :: Views: 836
I am trying to design a switched capacitor sampling system in virtuoso schematic editor. But I don't know how to:
1- Generate non-overlapping clocks.
2- How to model the switches? should I use like nfet or there are special switches?
Analog Circuit Design :: 05-22-2009 18:37 :: mahyar :: Replies: 3 :: Views: 1819
The non-overlapping time is the delay through the chain: td(NOR)+2*td(INV). If you want to decrese it, remove those two inverters.
Analog IC Design and Layout :: 08-04-2009 14:12 :: JoannesPaulus :: Replies: 1 :: Views: 623
i'm designing a two phase non-overlapping clock generor for a pipelined ADC.
in lots of papers,they combine a NAND2 following by a chain of cmos inverters for delay.but when i was simulating,i found that the delay of inverter chain is very small and it is not adequate. it is, however,still small when i add more inverters.
anyone have good
Analog IC Design and Layout :: 01-15-2010 21:02 :: urian :: Replies: 3 :: Views: 1579
Dear Friends, I am designing 10-bit SAR ADC. The blocks comparator, DAC has been completed.
But I am fully unaware of, how to design the digital control circuit.
Even I have tried with shift register, ring counter, D-FF , Non overlapping clock and gates.
But couldn't succeeded. Even I am getting the problem in understanding the timing function f
Analog Circuit Design :: 02-02-2010 07:12 :: kapil kumar rajput :: Replies: 2 :: Views: 1776
1- Regarding your digital, you need to design the clock generator circuit (non-overlapping clock), digital correction logic and the MDAC ( comparator + some gates + ...)
2- About literature, you can find theory in the following thesis (available in google):
(a) Design for Reliability of Low-voltage, Switched-capacitor Circuits by (...)
Analog Circuit Design :: 10-27-2010 14:38 :: palmeiras :: Replies: 7 :: Views: 2099
Well, are you still having a trouble to understand the over-lapping and non-overlappign clock thing ???
What would happen if you feed 010101 pattern to that circuit with overlapping clock ? If you think it still works in this scenario, you probably don't fully understand synchronous circuit and need to go back to the textbook.
Electronic Elementary Questions :: 11-15-2010 16:31 :: lostinxlation :: Replies: 7 :: Views: 909
I want to make the layout of a non-overlapping clock generator. In that circuit i am using two delay elements each of which is a cascade of even number of slow inverters having small aspect ratios(20 inverters in series). Can i use common centroid or some another layout techniques while making layout of the delay elements?
thanks in a
Analog IC Design and Layout :: 07-07-2011 08:34 :: nishanthpv :: Replies: 2 :: Views: 865
Can you show me the simulation of the signals clock_POS and clock NEG
You get the problem on clock edge ... therefore I think there might be something with your non-overlapping clock generator ....
Analog IC Design and Layout :: 06-07-2012 07:22 :: AmrZohny :: Replies: 10 :: Views: 1619
You can see this material:Simulating Switched-Capacitor Filters with SpectreRF~I designed one 4th order switched capacitor biquad filter in UMC 180 nm technology using cadence software (version 5.10.41).This circuit is operating on a two phase non overlapping clock generator (i/p frequency = 1 kHz). To simulate this circui
Analog IC Design and Layout :: 10-20-2012 22:19 :: superleaf :: Replies: 1 :: Views: 573
Draw the circuit diagram of a one-bit Dynamic Shift Register, based on
CMOS inverters and transmission gates, using a 2-phase,
non-overlapping clock. Briefly explain the operation of the circuit
Modify your design such that it has a parallel input and can store data
when the clock is stopped. Briefly explain its operation
For a (...)
Electronic Elementary Questions :: 07-30-2013 13:29 :: rafia123 :: Replies: 1 :: Views: 219
Can anybody give me a circuit that converts DC(direct current) voltage to square wave with an input voltage as low as 200mV?...Tnx
Analog Circuit Design :: 12-14-2013 08:56 :: millinium :: Replies: 2 :: Views: 233
I have a SC integrator implemented with complimentary switches. I use non-overlapping clocks. Does it matter if the complimentary clocks overlap.
What i mean is, the complimentary switch runs on two clocks that are the inverse to eachother. ie. clock and then clockbar. So in an integrator (...)
Analog Circuit Design :: 10-20-2004 00:41 :: cjupiter :: Replies: 9 :: Views: 1742
The sample and hold colck should high level no overlapping. and check the sample timing, CM switch should turn off first then sample switch turn off and then hold switch on. that can reduce the charge injection and clock feedthrough.
Analog Circuit Design :: 01-20-2008 07:51 :: jerryzhao :: Replies: 6 :: Views: 951
What is the real or optimum value of the non overlapping time of the two clock phases in a switched-capacitor CMFB circuit used for an integrator? What about the rising and falling time of the clock? Does it have any relation with the clock period? In my simulations the non overlapping time has a great (...)
Analog IC Design and Layout :: 08-07-2008 09:18 :: naalald :: Replies: 1 :: Views: 701
A simple clock generator would be a constant current feeding into a cap and using a comparator to look at cap slope to Vref ~ compare and reset cap and repeat. This comparator then just flips a D flip flop which then generates your 50K clock. Then you make an non overlapping nand latch to make your phi1 and phi2.
hope this helps
Analog IC Design and Layout :: 03-21-2011 14:40 :: jgk2004 :: Replies: 5 :: Views: 698
I have 3 clocks in my design. The third pulse clock is generated based on first clock.What is the best to represent this third pulse clock.
CLK1 and CLK2(duty cycle of 48%) are non overlapping phase clocks
CLK3 is a pulse clock that is double the frequency of CLK1 but (...)
ASIC Design Methodologies and Tools (Digital) :: 04-07-2011 13:10 :: manchuk :: Replies: 0 :: Views: 564
I am designing a high speed track and hold in Switched-Source-Follower topology. But I don't know whether the clock signals should be non-overlapping or not.
I have read a lot about the Switched-Capacitor type, and understand their clock signals should be non-overlapping. But what about SSF? I don't remember (...)
Analog Circuit Design :: 06-01-2011 10:43 :: Swordsman9 :: Replies: 0 :: Views: 414
6800 clock signal is defined to be NON overlapping phase-1 and phase-2
however reading from datasheet, the delay time "td" is maximum 9100 nano second.
this means phase-1 and phase-2 could be @ the same logic maximum 9100 ns.
which I find it is contradictory to the NON overlapping requirement.
could someone help me understand this (...)
Microcontrollers :: 08-15-2011 05:24 :: XC.6800 :: Replies: 2 :: Views: 355
Topology would depend on the relation / character of
the phases. A 5-stage ring oscillator would produce a
field of overlapping phases. A Johnson counter would
produce 5 nonoverlapping ones, as might a marching-
bit shift register (these, requiring a 5X clock input).
A shift register or binary counter plus poor-boy ROM
could produce you an (...)
Analog Circuit Design :: 01-15-2014 14:04 :: dick_freebird :: Replies: 6 :: Views: 299
Does anybody have any experiance with ATTiny12 running with internal clock.How accurate is the clock?Can it run half-duplex RS232 (software emulated)??
Professional Hardware and Electronics Design :: 02-22-2002 08:54 :: Rosko :: Replies: 3 :: Views: 1050
How can i make the constraint(in Synopsys and
apollo) to push the different gated clocks domain into balanced clock's latency ?
ASIC Design Methodologies and Tools (Digital) :: 03-08-2002 09:21 :: Nobody :: Replies: 6 :: Views: 3160
ICD2053 is the serial programmable pll clock synthesizer chip of Cypress.
But it no longer become production.
I'm lopking for for the replacement of ICD2053.
Is there anybody who know about this solution.
Professional Hardware and Electronics Design :: 05-20-2002 04:30 :: heastone :: Replies: 3 :: Views: 2034
Any one know this topic? I aready know PLL, but how to apply PLL to it?
ASIC Design Methodologies and Tools (Digital) :: 07-17-2002 18:31 :: dd2001 :: Replies: 8 :: Views: 1994
Synopsys Power Compiler can use integrated gate-clock cell (Latch type) to implement a low power design. Which StandCell Library support the integrated gate-clock cell (Latch Type) that can be used by power compiler ?
ASIC Design Methodologies and Tools (Digital) :: 07-21-2002 02:07 :: S0933263236 :: Replies: 7 :: Views: 2197