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Run DC analysis with temperature as sweeping parameter. Using calculator select VS of bandgap voltage. Then select DERIV Special function of calculator and click plot. You will get TC. If you prefer PPM multiply it by 1000000.
Make the steady ratio to 0.1 it might solve your problem. Steadt ratio is the parameter in analysis windows. Hi, can you show me, where can i find this option in cadence. Thanks
when I use cadence simulation,the test circuit is a inverter which is built by a PMOS and a NMOS transistor. A DC voltage source DC=3V was used to power this inverter. A pulse voltage source was connected to the input of this inverter with rail to rail square signal of period of 1 micro second. A transient analysis is chosen with end time of 10 m
Dear all, I have a question about the cadence simulation setting. I hope you could help me. In our simulation, I need to edit the ?input.scs? file. After I finished the edition and press the "RUN?icon in the Analog Design Environment Windows. The simulated result is same as the netlist I changed before. However, I run the (...)
Hi People, I'm running a simulation for a optical circuit design which consist of a Limiting amplifier and a common mode feedback circuit. I'm facing a problem in cadence simulation, that is while running transient simulation it is giving the convergence error as in the attachment. This error only come when i run at (...)
Hi, there A cadence simulation question: I change the library from one path to another, then I can not simualtion but get the following error msg: "None of the properties 'lastSchematicExtraction' or 'syLastExtraction' was found" how to overcome it? thanks
please tell can i run my simulation in multisession. say 100u sec simulation in two parts 50u+50U. if yes how
Hi Everybody I am new to this.... Can anyone help me in giving answer for following error ...... When I am running the cadence simulation for Inverter which I design through Verilog A than it is showing error as NO NETLIST FOUND.....Infact while doing check and save everything is ok... Thanks in advance
You define a transient sweep and setup a parameter sweep to sweep variable TEMPDC -- the variable can be picked up with menu. Then you setup an outpu expression with calculator. Maybe you need function "value". After a successful run, this expression should give a single value, displayed in the simulation window. Then you do the (...)
Hi All, I have a question related to cadence....After i do the DC sweep simulation, I want to plot the variation of some parameter vs any parameter..the cadence won't let me choose this option. It plots "vs" the default swept value. Eg: If i sweep W (width) of a device and now if i want to plot gm/Id vs Id, (...)
I encounted a problem is when I run around 10 times of simulations (small-size circuit), the cadence will say repeatedly more of less "out of memory and reset the cdsSpice by using -s option". Then, I follow this sentence to enlarge the memory, for example "cdsSpice -s200", but when the Analog Enivronment do simulation, it will (...)
My circuit is mixed signal design. for the digital part, it will cost me too much time to simulate it. Who can tell me the better ways to increase the simulation speed?
i have this 10-bit pipeline ADC that operates at 6.75Mhz, i wanna test INL & DNL factor for my ADC, i knew it supposed to be done using transient analyses...what type of input i should give, i've differential input in to ADC. ANd how long u need run & how many hours does it takes???
Is it possible in cadence to simulate circuit whoose two parts are at different temperatures?
Hi, While simulating in cadence Analog Design environment, I face the following problem. Any help would be of great value. ------------ Problem Description:The transistor count is approx. 5000 (7-bit ADC) for the circuit I want to simulate by spectre. I gave a "transient" simulation ("tran") from analog design environment for a period of ~ 525ns
I want to see the Ron of a transistor for different Width's; However, when i do a sweep for this component parameter, the results browser shows Ron of the last Width there a solution for this? Otherwise, i have to manually change the width each time and note the Ron...which is not that effecient...!! Regards,
I am simulating Folded Cascode opamp What are the steps for DC analysis in cadence? My main concern is which voltage source i have to sweep.... its a VDD = 1.8v ( by assuming using 0.18 tech)... or by sweeping Common mode Voltage source(VCM=VDD/2) connceted at the differential input??? Also what are the steps of AC analysis... can anyo
I'm designing a switch cap ckt now and I want to get a graph of "voltage vs. temperature" for my ckt simulation. does anyone know how to get this kind of graph? thanks. I'm really in urgent.
Who can give me a link or book for monte carlo simulation by cadence?
I am using a network enviroment in simulation, that is, all the user files are located in a fileserver, while the cadence main programme is located on another server. There is no problem when I run the simulation first time, but when I want to simulation again icfb will tell me " *error* asiiStart: error in start (...)
am using a network enviroment in simulation, that is, all the user files are located in a fileserver, while the cadence main programme is located on another server. There is no problem when I run the simulation first time, but when I want to simulation again icfb will tell me " *error* asiiStart: error in start function, (...)
Yes, the s-parameters that are created by ADS are recognized by cadence in Tocuhstone, CITI format. And also, by using RFDE , cadence will create spectre view for this component.
I have drawn schematic of a 700 MHZ cmos class E differential power amplifier in cadence Virtuoso svhematic .Now, to verify that it is a 700 MHZ power amplifier i need the graph of Output Power and PAE versus frequency . I am not able simulate to get the above graphs. Can anyone, who has done this type of simulation in cadence, can explain (...)
How to specify Vth(Threshold voltage) of a MOSFET as a parameter for monte carlo simulations. Thanks in advance.
assuming you would like to create a 4 port trasfromer model run the simulator with Vg connected to ground, or use your 5X5 s-par model with Vg connected to ground you now have a 4 port s-parameter block. build your best estimated trasformer model, with parasitics, etc. Have all these parasitics set up as variables usinfg the var block use ADS t
Hi, I am new in VLSI design. I want to start simulation on SRAM 6T memory cell in cadence. How can I start? Which material or book can help me? What is spice file? How can I edit or use that file in cadence? How can I get TSMC files and How to use that files for cadence simulation? Thank you.
Hi, I am new in VLSI design. I want to start simulation on SRAM 6T memory cell in cadence. How can I start? Which material or book can help me? What is spice file? How can I edit or use that file in cadence? How can I get TSMC files and How to use that files for cadence simulation? Thank you.
I have designed a low noise amplifier and gotten the satisfied simulation results when it was simulated in ADS. Unluckly, the simulation results in cadence(ic5141+mmsim610) is very bad. The paraments are all the same. The difference is that the PDK in ADS is TSMC rf cmos 0.18um v5 and the PDK in cadence is chrt rf cmos (...)
what's the acceptable difference between caculation and simulation. the calculated drain current is much more than the simulated one the schematic is a simple one, a common source circuit. the parameter is obtained from .scs file. thanks
I am using cadence virtuoso and spectre to simulate a complicated circuit I am building. I am trying to set up my stimulus properly so I wrote this .scs file. I am having trouble getting the piecewise linear function working. Can anyone please provide me with some help? I am very new to the tool set. I appreciate the assistance. Error f
I am wondering what is the difference between these 4 ways of running simulation with cadence 1. three step method ncvlog *.v ncelab top_module_name (-nc_options) ncsim top_module_name (-nc_options) 2. one step method ncverilog *.v (+nc_options) 3.ncsim by GUI. nclaunch & 4. irun command And which one is the preferred way.
I'm coming across the following errors when i run LVS on assura on my design. Can anyone help me with it? thank you for your help in advance! ====== parameter Mismatches for Instances ===================================== = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 1) Schematic Instance: R1 resnsnpoly
Hi all I would like to add noise source for my simulation under cadence but have no idea how to do so. Anyone has any idea how to do that?
Hi. Can you please tell me the interpretation of the betaeff and vdsat parameters obtained from cadence ADE simulation using "Results -> Print -> DC Operating Points" ? I am asking this because in a simulation of mine, the displayed results are as below: betaeff 3.837m ... ids 13.55u ... vdsat -113.3m v
First, you should check model accuracy by comparing simulation results with measuring data from foudry;then you can easily get level 1 parameters,from id-vd,or gm-id curves .
Is there a way in a cadence simulation flow (ncsim) to access a hierarchical Verilog signal from a VHDL testbench, or a hierarchical VHDL signal from a Verilog testbench? cadence has the nc_mirror feature which replicates the hierarchical referencing capabilities of Verilog, but is there a mixed-language equivalent?
I got this error message in simulation after I install a design kid. Where has the setting of spcifying the location of the input.scs file? Thanks
Now i designed a PLL, and want to calculate the output jitter from cadence simulation results. i want to plot the histogram, and calculate the rms jitter. how can i do that? thank you.
I design a PWM DC2DC .. but whole chip simuilation I find simulation is very very slow when I put "pure inductor" in circuit . even though I use aditspice .. how to speedup my simulation ?? or adit setting some parameter can simulation it . another problem is , hspice or aditspice can assign "probe node after (...)
Hi, I designed a fully differential op amp with CMFB. There is a requirement about the phase margin of CMFB in the specs. Then how can I get this from cadence simulation? Thank you for your help. princerock
After installing the PDK, I simulate a very simple circuit, but failed. My cadence version is 5141usr3 Error found by spectre during circuit read-in. input.scs: Q0 is an instance of an undefined model npn_JI. spectre terminated prematurely due to fatal error.
i cant make cadence analog design environment to plot current of any instances except a dc voltage source. this is a bit annoying, does anyone know what's going wrong? here's the error message on icfb window: *Warning* Wave10 is not a waveform object that can be displayed and will be turned OFF automatically. nam
I design 12-bit charge redistribution ADC. How I can simulate the INL and DNL parameters in cadence Design Environment. Should I simulate 4096 points? It's impossible. Or I can apply sine wave? Please, if possible, in detail. Big thankx
1. Between the input port and 1st transistor or output and input of 2nd stage, we usually put the coupling capacitor with series connection. But for my cadence simulation, there is no output coming out from the Spectre graph or operating in region "0" for a transistor. What?s the problem? I assume the input DC voltage as 0.7V only for input por
I am prototyping a IP core which was written in verilog languge in cyclone II application engineer wrote code in C for application level.Can i simulate the both in cadence simulation environment so that i can find the bug in real environment .Can anyone suggest on this.I am in desperate situation.Please help me. Thanking you kumar
Hello . I am trying to get the DNL from 10 bit sar adc ? I am using , cadence library "ahdlLib , dac_10bit_ideal " to convert the 10 bit ADC ramping output " D9:D0 to analog signal . Then using , " cadence library " ahdlLib , dac_dnl_10bit " to get the DNL of the ADC ? It supposed to output a histogram file or someting . But I dont see any file ?
I'm designing a switch cap ckt now and I want to get a graph of "voltage vs. temperature" for my ckt simulation. does anyone know how to get this kind of graph? thanks. I'm really in urgent.
Dear all, Does anyone suggest some cadence up-conversion mixer simulation example to me? My mixer is zero RF up to 1GHz. How could I do this kind of simulation? Thanks wccheng
Does anyone know how to simulate THD in circuit design environment of cadence ic6.1 version? how to right the thd() expression with calculator?
I'm still confused about the THD simulation result, I pasted the simulation figure, the left one is sinewave, and right one is the DFT simulation (only sampled the last period as LvW suggested) with rectangula window, from t