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193 Threads found on edaboard.com: Parameter Cadence Simulation
Run DC analysis with temperature as sweeping parameter.
Using calculator select VS of bandgap voltage. Then select DERIV Special function of calculator and click plot. You will get TC. If you prefer PPM multiply it by 1000000.
Analog IC Design and Layout :: 23.11.2004 05:24 :: Fom :: Replies: 9 :: Views: 2776
Make the steady ratio to 0.1 it might solve your problem. Steadt ratio is the parameter in analysis windows.
Analog Circuit Design :: 07.07.2007 05:08 :: pankajdudulwar :: Replies: 7 :: Views: 714
I want to see the Ron of a transistor for different Width's; However, when i do a sweep for this component parameter, the results browser shows Ron of the last Width there a solution for this?
Otherwise, i have to manually change the width each time and note the Ron...which is not that effecient...!!
Regards,
RF, Microwave, Antennas and Optics :: 17.04.2007 05:02 :: haadi20 :: Replies: 1 :: Views: 639
Make a parameter sweep with a variable named 'temp'. 'temp' is the default variable name of temperature at cadence. When you place the required voltage at the outputs, it will be plotted vs temp after the sweep.
Analog IC Design and Layout :: 09.04.2008 02:21 :: ieropsaltic :: Replies: 3 :: Views: 635
How to specify Vth(Threshold voltage) of a MOSFET as a parameter for monte carlo simulations. Thanks in advance.
Analog Circuit Design :: 22.03.2009 02:01 :: arunkumar446 :: Replies: 0 :: Views: 880
assuming you would like to create a 4 port trasfromer model
run the simulator with Vg connected to ground, or use your 5X5 s-par model with Vg connected to ground
you now have a 4 port s-parameter block.
build your best estimated trasformer model, with parasitics, etc. Have all these parasitics set up as variables usinfg the var block
use ADS t
Electromagnetic Design and Simulation :: 15.05.2009 02:48 :: isbarak :: Replies: 2 :: Views: 1429
what's the acceptable difference between caculation and simulation.
the calculated drain current is much more than the simulated one
the schematic is a simple one, a common source circuit.
the parameter is obtained from .scs file.
thanks
Analog Circuit Design :: 20.10.2009 10:23 :: foreveryanyee :: Replies: 1 :: Views: 512
I am using cadence virtuoso and spectre to simulate a complicated circuit I am building. I am trying to set up my stimulus properly so I wrote this .scs file. I am having trouble getting the piecewise linear function working. Can anyone please provide me with some help? I am very new to the tool set. I appreciate the assistance.
Error f
Analog Circuit Design :: 30.04.2010 02:21 :: Digital-L0gik :: Replies: 2 :: Views: 1575
Hi All, I have a question related to cadence....After i do the DC sweep simulation, I want to plot the variation of some parameter vs any parameter..the cadence won't let me choose this option. It plots "vs" the default swept value.
Eg: If i sweep W (width) of a device and now if i want to plot gm/Id vs Id, (...)
Analog IC Design and Layout :: 25.01.2011 15:08 :: mfhanif :: Replies: 3 :: Views: 1170
Hi,
Err: Sch RES missing params: w ; Lay RES L/W/m 0.00018 1.5e-06 1
Layout Instance is the merged result of: avD22_1 avD22_2
It looks like your schematic does not have "w" parameter definitions.
I'm guessing either that you did not define the parameter values in your device (I wonder if this can pass Virtuoso's 'Check & Sav
Analog IC Design and Layout :: 16.10.2012 22:53 :: cop02ia :: Replies: 6 :: Views: 539
cadence that is installed RedHat 7.3 doesn't recognize active component models even I have tried to transform SpectreS models to Spectre format by aid of Model Translation utiliy.
What should I do to use active device models in cadence ? Everything seems to be ok but when I do a simulation with active devices such as transistors , diodes (...)
Linux Software :: 30.11.2003 09:35 :: BigBoss :: Replies: 2 :: Views: 1116
IC 5.033 base version has many bugs ( as usual in cadence ) and therefore SP's and some Hot Fixes must be installed.
I have installed approx 6 SP to get it more stable and avery SP has 2 CD !! 8O
But now, it's not so bad.. :)
The most difficult thing is the configuration and there are many tricks to correct the bugs... :!:
But I can s
Linux Software :: 15.03.2004 20:33 :: BigBoss :: Replies: 29 :: Views: 32701
Noise Figure obtained from ADS, Is't include "gate noise" or not? :?:
the BSIM3 model doesn't include parameter of "gate noise", How can ADS to get out right NF if it doesn't calculate "gate noise"?
RF, Microwave, Antennas and Optics :: 15.06.2004 06:01 :: cqmyg5 :: Replies: 3 :: Views: 1218
I have found out that you can basically plot any transistor parameter versus sth else by using the calculator, then choose MP, click on the particular instance of transistor then choose what parameter you want to plot, there is a whole bunch of them like 80 or so, export expression from calculator to output setup and plot, thanks
Analog IC Design and Layout :: 05.07.2004 01:05 :: kytan :: Replies: 5 :: Views: 2410
An easy way to do it, if you're not familiar with s parameters and you have problems with calculator expression, is to put an ac current source with AC=1 at the pin you want to measure the impedance and perform an ac simulation over your interesting frequency range, then plot the voltage at input pin (as mag and/or phase). Being Z=V/I with I=1, Z=V
Analog IC Design and Layout :: 23.08.2004 05:30 :: Mazz :: Replies: 4 :: Views: 1787
Hi.
Since the transistor parameters are usually obtained in a typical operation region, you may not obtain the fT frequency directly from the simulation. Instead, you will obtain the gain at -3dB cutoff frequency, and fT will be obtained by extrapolating the curve. Since the frequency characteristics of the transistor shows only one pole, the re
Analog IC Design and Layout :: 01.08.2004 19:10 :: yjkwon57 :: Replies: 5 :: Views: 1742
The hspice model of vcvs recognizes the max and min parameters, but the spectre model does not. If you are using spectre, you may use veriloga to model the saturation effect.
Analog IC Design and Layout :: 18.11.2004 20:26 :: Hughes :: Replies: 18 :: Views: 20128
Why you use VCVS to transform single ended to balanced?? In cadence all ports are already balanced !! Connect them as is...
If you intend to obtain 90 degree phase difference, simply put 90 degree in Phase specs. in Port definition.
Of course you may not obtain s-parameters because VCVS's don't have equivalent circuits and therefore s-paramet
RF, Microwave, Antennas and Optics :: 21.11.2004 09:11 :: BigBoss :: Replies: 5 :: Views: 3549
First, you should check model accuracy by comparing
simulation results with measuring data from foudry;then you can easily get level 1 parameters,from id-vd,or gm-id curves .
Analog IC Design and Layout :: 13.01.2005 03:45 :: thcm :: Replies: 9 :: Views: 1179
which parameter is used for model,while simulate the noise.
Analog IC Design and Layout :: 28.01.2005 00:28 :: rongli :: Replies: 4 :: Views: 2925
Well, just add the property "m" to the instances. In analog artist, the hierarchy netlister can recognize the "m" parameter. But the flat mode not.
Another way is to add a CDF parameter "mul" for the inverter. Then set the "Multiplier" of nmos and pmos in the inverter to 'pPar("mul"). To display the parameter "mul", add a "NLPLabel" label ""
Analog IC Design and Layout :: 27.02.2005 03:41 :: Hughes :: Replies: 11 :: Views: 3413
I tried a finite-ground singlewire layout simulation in Momentum for a 7-metal process. I chose AM as the signal layer and M1 as the ground layer. The ground layer has the same length and a three-time width as the signal layer. Two 50ohm ports are made by AM layer. Then I ran S-parameter simulation in Momentum. However, the results were (...)
RF, Microwave, Antennas and Optics :: 26.02.2005 19:18 :: magicRF :: Replies: 1 :: Views: 625
hi
i am doing LNA for 2.4G wireless lan application.i am struggling to characterise regarding noise figure,s parameters in cadence.can anubody help me to simulate the circuit for those parameters in cadence.i want detailed information.pls post some documents or help manual regarding that.
for s parameter (...)
RF, Microwave, Antennas and Optics :: 09.03.2005 00:53 :: balu304 :: Replies: 3 :: Views: 3407
Because the need of simulation,I need to get a current source,
whose value is "I=10mA*exp(T/27)",T=temperature,
so when I do temperature sweep, I can get a changed current source as the expression above.
But I don't know how to cite the parameter "temperature",
can anyone know?
Analog Circuit Design :: 08.07.2005 06:06 :: newhand :: Replies: 2 :: Views: 946
I am simulating an oscillator in cadence. I only have the s-parameter file of the resonator. so I use n1port to model the resonator. But I can not do pss or pnoise simulation when using the model in cadence ic. I can only do trans. Is there any other way I can simulate phase noise in cadence ? Thanks.
RF, Microwave, Antennas and Optics :: 19.09.2005 18:24 :: danda821 :: Replies: 0 :: Views: 478
Hi, all:
I am a fresh man to design analog circuit, and now I use cadence IC to simulate circuit.
Now I have some questions:
1. how to simulate corner?
2.when will we use the following simulations:
Envelope Following Analysis (envlp)
Circuit Information (info)
Immediate Set Options (options)Periodic AC Analysis (pac)
Periodic Distor
Analog Circuit Design :: 04.11.2005 19:27 :: wjxcom :: Replies: 1 :: Views: 1302
Please check also the "Section" parameter where you need to tell the simulator which process corner you want to use .. for example, ff (fast fast) ..
You can find the process corner name in your model file..
Analog IC Design and Layout :: 26.11.2005 17:42 :: mm6349 :: Replies: 13 :: Views: 1309
Refer to "Spectre Circuit Simulator Reference" page 73
"... Currently, multithreading is only available for devices evaluation for BSIM3v3, and BSIM4.
Multithreading does not work with table model. If there is an instance of a primitive using table
model, multithreading would not be applied to all instances of that primitive.
Multithreading
Software Problems, Hints and Reviews :: 01.12.2005 10:48 :: Amuro :: Replies: 3 :: Views: 1215
I am using the TSMC 0.18um model files. When I run the simulator I get an error which says level=49 not supported. I think this is the spice level parameter mentioned in the model file.
Just to see if it works fine, I changed the level to 11 and it seems to work. Is this ok for simulating(are the results going to differ a lot fr
Analog Circuit Design :: 03.01.2006 23:31 :: Chethan :: Replies: 7 :: Views: 1780
You must simulate it as a spread parameter network. Use just R and C devices.
For more about this go for example to cadence DIVA manual and look for parasitic extraction of metals.
Analog IC Design and Layout :: 14.02.2006 19:34 :: Teddy :: Replies: 1 :: Views: 917
firstly u need to really understand the architecture...
Then every component in SAR need to drawn a block....the comparator, DAC and S&H ciruit.
I beleive in MAtlab all these block has already there....Sample and Hold is under sample circuit
Connect them all. double click on the block...and play with the parameter untill u achieve your spe
Analog Circuit Design :: 06.03.2006 01:39 :: Syukri :: Replies: 2 :: Views: 997
You can plot Vgs at max gm using calculator special functions.
Use DC analysis with Vgs sweep and parametric analysis sweeping L as parameter.
Then plot xmax(deriv(Id)). It will plot Vgs at gm max vs. L.
Analog IC Design and Layout :: 06.03.2006 00:50 :: Fom :: Replies: 1 :: Views: 1528
When i use simulation by spectre,there's an error.
Error found by spectre during hierarchy flattening
V1:Waveform type must be specified if any waveform parameters are given.
It's seem as the Independence source,just like(Vsin,Vpluse and so on)
How did you run spectre? Did you run spectre in a terminal window, or run f
Software Problems, Hints and Reviews :: 17.03.2006 19:06 :: Hughes :: Replies: 14 :: Views: 4762
when simulating mixer's noise figure with pss and pnoise, what dose the parameter "Reference side-band, enter in field" stand for?
in the cadence help document, it is written "The Reference Sideband must be -1 because this is a down converter. Other possible choices are 0 and +1."
i am a little confuse about it. In pnoise arguments setup, fo
RF, Microwave, Antennas and Optics :: 23.03.2006 02:40 :: hqing :: Replies: 0 :: Views: 833
Please check the netlist to see which parameter use pPar() function. If you use AEL to set the model or m parameter, most likely you will get errors.
Software Problems, Hints and Reviews :: 04.04.2006 09:58 :: Hughes :: Replies: 4 :: Views: 1583
If you have s-parameters of that spiral, it's quite easy.
Put it in cadence schematic and do a s-parameter simulation and then obtain z or y parameters.
Q Factor= real part(Z1) /imaginary part(Z1)
Z1: Seen input impedance when one port is short circuited.
Analog IC Design and Layout :: 16.04.2006 17:20 :: BigBoss :: Replies: 4 :: Views: 2142
Of course you can have the functionality in Verilog A. You can model a resistor in Verilog A as :
I(in,out) <+ V(in,out)/R;
where you can model R as
parameter real R = Ro + sin(w*t);
remember to mark the nodes in and out as electrical.
Analog Circuit Design :: 25.04.2006 07:08 :: Vamsi Mocherla :: Replies: 28 :: Views: 6050
do i need to specify a model parameter to be changed, like Vth?
Analog Circuit Design :: 20.05.2006 11:15 :: yolande_yj :: Replies: 3 :: Views: 859
Hi all,
I have done the sp simulation with the Analog Design Envionment in icfb. I could display the s-parameter table after simulation by selecting "Results->Print->S-parameter->2 port". According to a tutorial I'm using, I should be able to plot the s parameters by first clicking on "Tools->Waveform (...)
Software Problems, Hints and Reviews :: 19.06.2006 18:32 :: carl_chao :: Replies: 1 :: Views: 962
if you make your layout in cadence environment, then you can export your layout to gdsII format and import it in Momentum. you have to enter in momentum your technology parameters (number of metals, metal and oxide thickness, substrate conductivity etc.) in "Create Substrate" option. depending on the type of your inductor (differential, single-en
RF, Microwave, Antennas and Optics :: 18.07.2006 15:43 :: estradasphere :: Replies: 5 :: Views: 1495
OK. Thanks.
But I haven't in my kit MC model.
Can I change some model parameter for make MC?
Analog IC Design and Layout :: 13.09.2006 10:54 :: unit900 :: Replies: 2 :: Views: 622
hello
i made transit analysis in cadence, and make parametric sweep, the result is several sine waves versus time , each corresponds to a parameter value that i made sweep for it,,,,now , i want to plot the maximum of those sine waves versus the corresponding parameter value,, can i make that using the calculator or anything else? if (...)
Software Problems, Hints and Reviews :: 28.09.2006 14:02 :: ravet :: Replies: 2 :: Views: 1076
I tried to read the Virtuoso manual and spectreRF simulation manual but I can not define the parameters of the diode in cadence Virtuoso ver.2004
Could you guys please answer the questions about the parameters below?
I also attach the pictures including parameter.
Model Name
Device area
Junction (...)
Software Problems, Hints and Reviews :: 12.10.2006 18:05 :: whitewiz :: Replies: 0 :: Views: 973
hope it will help you
tc:D
Analog Circuit Design :: 12.10.2006 23:40 :: laxre_06 :: Replies: 3 :: Views: 1617
I tried to read the Virtuoso manual and spectreRF simulation manual but I can not define the parameters of the diode in cadence Virtuoso ver.2004
Could you guys please fill out the blank of the parameters about any diode in cadence?
I also attach the pictures including parameter.
Software Problems, Hints and Reviews :: 15.10.2006 02:54 :: whitewiz :: Replies: 0 :: Views: 1005
Because the simulation information in the CDF of cellview res doesn't define L and W.
Open the CDF form, fill in the form with the library name and cell name of res, and change "Effictive" to "Base"
Open the "simulation Information" section, and select the auCDL simulator. Add l and l to the instance parameter field.
Analog Circuit Design :: 08.11.2006 23:48 :: Hughes :: Replies: 2 :: Views: 1802
Thanks for replying, but can you tell me exactly what tool i am suppose to use once i have extracted the layout with parasitics.
U may use the Start_XT(synopsys) of Dracula(cadence),They are the best tools for extract parameter on the layout.
Then, u may annotate the delay infor from the parameter into your netlist and run
ASIC Design Methodologies and Tools (Digital) :: 12.11.2006 22:52 :: visualart :: Replies: 6 :: Views: 1174
hi, i need something that can get some insight into the device. we set up the layout and process parameter(like finger width, doping), it gives us RF performance. is there such a tool?
RF, Microwave, Antennas and Optics :: 17.12.2006 11:45 :: ustc_tweeg :: Replies: 6 :: Views: 931
now i m in inverter tutorial and getting error =
xi0.m1: Effective length is less than or equal to zero.
I changed the L & W to a certain range but it did not help.
Moreover for an another project i need to vary L & W to a certain range and see its graph simultaneously ... Can i do this? I know i can vary dc ac voltage and all that in a
Linux Software :: 16.02.2007 12:01 :: dozy_walia :: Replies: 15 :: Views: 1767
I build a Verilog-A VCO model. The model can work well in cadence spectre simulation. But its frequency can't be tuned in nanosim simulation.
Can you help me?
Following is the VCO Verilog_A model:
`include "discipline.h"
`include "constants.h"
`define PI 3.14159265358979323846264338327950288419716939937511
module (...)
Analog IC Design and Layout :: 12.01.2007 04:28 :: hmsheng :: Replies: 0 :: Views: 1074
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