Search Engine


Add Question

Are you looking for?:
parastic capacitance
28 Threads found on Parastic
Hello All. I am wondering for what should I use for the IBIS model including PKG RLC in Designer, Pin model or Buffer model?? There are 2 types of models in IBIS file, Pin model and Buffer model. If I want to use the IBIS model with PKG RLC while I run the DDR SI simulation in Designer, which model is right for? Pin model or Buffer model??
Hi I am looking at using multiple 18s20 devices in a monitoring unit, I was thinking of using parastic power for the device. Has any one used this mode? Is so make what is the max cable distance used ? What number of devices? Thanks
I just want to understand the capacitance such as cdd,cddbi and cjd,cjs.I know that the simulator Sprectre of Candence uses BSIM model and I have already downloaded the BSIM3v3 manual reference.But I could not find the parastic capacitance I mentioned above.Thank you ---------- Post added at 19:29 ---------- Previous post w
You mainly refer to parastic capacitance to substrate? This was the effect that seems most obvious to me, and might explain the high frequency issue. On PCB, I have used gate bias network with a combination of SMD resistor and lines up to 24GHz, so I am not aware of a fundametal frequency limit. But maybe I miss
Hi, Can anyone tell me what is 2D and 3D parastic(RC) extraction? Regards.
hi, I want to put devices under mim caps, but how to calculate the parastic parameters, and how to do in the lvs and rcx? what should i pay more attention ? thanks
how to implement the parastic BJT equations of MOSFET into a SPICE circuit simulator? I think at first, I should get to know how to do with the standard MOS SPICE equations implement to the SPICE circuit simulator, right? i read there is a paper: "Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulation
A commerical simulator is used Hi ! What kind if simulator do you use ? (1) how to determine the fundamental mode, the first-order modes, the second-order mode,... because there are many parastic modes existing in this structure? (2) how to determine the cutoff frequencies of the modes? Most RF sim
I think the reason for slow negative going slew rate is the parastic capacitance at the drain of M51 or M512. you should simulate it to satisfy the spec.
How could I get the information about the package parasitic for different pacakge? I mean the parastic capacitor and indunctance.
tlup and tlup+ are both parastic model for astro to estimiate net load. tlup is 2d model, while tlup+ is 2.5d model, with more parastic cap model provided, and is more accurate than tlup model. and star-RC use 3d model extraction, thus cause post sta to be most accurate, but also most possimistic.
Added after 6 minutes: the parastic diode can not decide the discharge performance, but the mos diode can do it.
some ASIC design use parastic Cap for switch Cap amplifier .. Like flash A/D comparator
tsmc/ umc or other Fab will provide 5x5 or 10x10um (emitter area) BJT gds layout . but you should know in CMOS no twin/triple_well , only PNP bjt be use beta is small , only use for diode or bandgap cell some high Volt cmos process provide "really Npn or PNP" device . by the way , parastic BJT spice model is simple even corner
Some ways may work. For examples, MOS in subthreshold region, parastic pnp device. But the performance is not good. Any good suggestion? Thanks.
all element is important for analog design ,whatever it is active or passive, at the same time metal track is important too, layout floorplan is the key of analog layout design, power track, signal tracks and their distribution, difference floorplan can lead difference parastic cap and resistor. Usually, symmetry floorplan are used in the most case
maybe you can disable the PFD data when you extraction, so only the parastic is remain.
to sum up . bandgap use parastic Pnp device and consider Resistor variation , no trim bandgap will drfit some voltage .. another problem is "density or concentration" I ever met , from WAT restsor data is Ok , but really bandgap design use 2 long channel resistor . and cause resistor value mismatch . WAT only measure little square resist
Astro support TLU and TLU plus module for parastic estimation. which are chose in Timing Setup Sheet. usually, the TLU model exist in the Technology File, with the format of capacitance lookup table. while the TLUplus model is generate form the .nxgrd format, which is for RCXtract stage. and you have to check the RCXtraction Reference manual
It is said that the resistor shunt or series at the ouput of the LNA would decrease the 1dB compression point of LNA. So the parastic resistor of inductor would decrease the 1dB compression point of LNA. i have simulated the schematic below and found that the 1dB compression point of LNA decreases shapely from 12dBm(with ideal inductor) to 8.5dBm(
i think there is any command.. you get the netlist from DC.. and imported it to STAR-RCXT where you can extract parastic file. using certain commands given is user guides... Added after 2 minutes: i think there is any command.. you get the netlist from DC.. and imported it to STAR-RCXT wher
I want to make a diode in a digital CMOS process. The conventional method is to use a parastic pnp transistor. However, I want to make a diode that the minus terminal of the diode is floating. How to realize it in the digital CMOS process with out large leakage current ? Thanks in advances!!!
Hi, The main problem of IC analog design is the rising of parastic capcitance of CMOS, and that is mainl in high speed application. This capacitance come from different transistor compnents and layers. What is most parameters that is effecting that capacitance and how they modeled in IC. Is there any routing procedure to decrease it. Any issue
S/H switch use "dummy Mos" can really reduce charge injection , I ever use 1/2 size dummy Mos siwtch , but simulation sitll have charge injection maybe small switch W/L reduce , and reduce parastic Cap for reduce clock feedthrough
I think the cadence supply a tutorial for you . you have to reading the user guide of Assura of candence. the main steps as below: 1. load the technology file; 2. do layout; 3. do DRC LVS and RCX with the command files; 4. recerive the netlist with parastic components;
It should be less parastic capacitor, because the drain and source can share.
I have interesting in standard BJT process how to write LPE command file ? how can give some examples about to extract "parastic device" in BJT process I know CMOS process can use poly & active --> mos but BJT design have NBL , Epi .. how to define and extract parastic diode ??
in CMOS processs Poly R is small , but sheet resistance about 90~150 (N type or P type ..) and if use 0.25um process need include "interface resistance very large" what is your process ?? in CMOS design bjt is parastic device .. I don't know BJT process resistor value can you post BJT process document ?? which process ..