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I am looking for path based analysis in ASIC hardware. This analysis will be carried out during SI analysis.
I dont think u can modify the netlist in PT. U can only analyze in PT and make the changes going back to any backend tool like ICC, talus or soc encounter. And after doing the change select the path and do a path based analysis in PT ans finalize. Hope it helped.....
if you are doing ASIC design, sure the synthesis tools and layout tools will list the worst slack path based on the constraints you feed into the tools. if you are doing full customer, you have to run simulation to know how critical the path is regarding you expectation. in the case you want to mannually calculate delay for some (...)
Hi, As i understand the whole concept of STA is to analyse all the timing paths with respect to one clock cycle(exception of multicycle path).Then how are latch based designs analysed? Also why is it suggested that the latches should be avoided as far as possible. Vicky
DTA means.. You give a set of test vectors ..for which the simulator caluclates the output values based on available timing information.. ie.. verifying your verilog RTL code by using a testbench and inputs.. You may miss some bugs in ur code if u didnt give a exhaustive or atleast representative set of test vectors.. STA is basically calc
For low freq (1GHz) we are using Q3D to extract the model and proceed to Hspice for SI analysis For higher freq, HFSS is used to model the package and same Hspice for SI analysis. Latest trend/development in Ansoft Designer makes it a good alternative for full path simulation i.e. when combining package and MB in one simulation (...)
hi, you know what CTS does.. it inserts clock buffers and forms a clock tree such that clock skew from source to all flipflops are same.. If you design is not meeting setup time constraints then additional buffers leads to more complicated violations and similarly for hold violations.. if we have setup violations then this delay in clock path
Hi, Static timing analysis pertains to calculating path delays without applying any test vectors. The dynamic analysis is related to gate level simulation after inserting delays for each gate this done after synthesis, this needs test vectors to analsys. The path delays varies with applied test vectors. This DTA takes (...)
about STA, in what process corners u will check for setup and hold violations. There may questions, how setup check and hold check for the same paths.
hi muthamil, my 2 cents, Max operating frequency can be found by the Design Timing Critical path based on Timing analysis. Switching frequency for a cell is basically state driven and this information will be available in your library (state dependant power). happy designing chip design made easy
At Speed test uses two high speed functional clock pulse to test the delay of the combinational lgoic between registers. However, some combinational logic will take more than one cylce to propagate. So the two clock pulses are not enough for these logic. usually, we will set false paht of these paths. Another way is to use pipelineing to make
Hi, u know the time path model DC/PT will analyze is DFF'S CLOCK TO NEXT DFF'S DATA-IN. in order to analysis the I/O timing path , assign a true clock or virtual clock for the I/O port, make the I/O analysis based the model like the above(DFF->DFF) . Of course need use set_input_delay ,set_output_delay (...)
In Static Timing analysis (STA) static delays such as gate delay and net delays are considered in each path and these delays are compared against their required maximum and minimum values. Circuit to be analyzed is broken into different timing paths constituting of gates, flip flops and their interconnections. Each timing (...)
Cross-connect the inputs (INP1=INN2 , INN1=INP2) , VREF1=VREF2 . Standard feedback. You'll need an additional common mode feedback path to implement a fully differential amplifier. Otherwise the "standard feedback" isn't able to keep both outputs within reasonable bounds.
The answer is simple. Synopsys doesn't want any timing analysis tool in the industry other than Prime-Time. Extreme-DA's tool named "Gold-Time" was one of the competitor for PT, so the acquisition happened. The same case is with Magma, here Magma was getting better in Analog Simulation side, again acquisition happened
Hi all , I am bit confused with the AOCVM calculations done by PT all the synopsys documents , it is mentioned that graph based / path based aocvm derates will be applied starting from the common path in the clock path ( excluding the common clock cell).The common clock path will not be (...)
The ADS OscPort model for HB analysis is based on the Nyquist stability test critetion, which is described in "Microwave Transistor Amplifiers, analysis and Design, 2nd Ed, G. Gonzalez", chapter 5, section 2. The idea is measuring the close-loop gain and phase to determine the oscillating condition and frequency. The following is my (...)
Dear zeshan102 The results you can get using S parameters to design oscillators are poor, although they can be used for the first step of the design. This is because the S parameters are linear and small signal parameters by nature. In contrast the behavior that describe an oscillator is nonlinear and large signal based. To design your VCO you
timing analyzer is the best tool in ISE, you can do static analysis on any path you may also include the asynchronous reset/preset signals
You might want to take a look at: Pages 23-26 of this presentation give a good summary of current thinking regarding ground planes based on properly done signal analysis and experience. Controlled impedance for very high frequencies is more difficult on inner layers than on to
Running post layout gate simulation is necessary, if your constraints contains complicated multi-cycle path.
Hi, I already had solved the first one by coping link libraries from .synopsys_dc.setup file to .synopsys_pt.setup. About the second one, I don't want to sepcify one particular timing arc. I need prime time to examin different timing paths and specify the worst delay, but report_timing and report_delay_calculation don't work this way. I'm sti
How to design asymmetrical Doherty power amplifier? Using uneven power splitter could be one way. question is how to define which path have more power, main amplifier path or peak amplifier path? Other way is to use different LDMOS transistor, do you have some suggestion on it? Besides, how to design three-way doherty power amplifier?
Hi : how does the ICC calculate the EM problems?? go to lef to find the max current density limite, then to calculate a max density of a certain path?? thanks a lot Added after 42 minutes: Hi : how does the ICC calculate the EM problems?? go to lef to find th
dynamic timing simulation are vector based. you will define some 1,0 at input ports and change them in testbench.. in static timing simulation vectors are not applied,you have to apply a clock only.. all timing paths in ur designs are checked for timing violations and worst case results are reported ... e.g. flop to flop timings (...)
Hi Everbody, I need your help I am not good at matlab/simulink, My Problem is about Multipath Rayleigh Channel BER Calculation in Simulin/matlab. BER Results are for the below cases; Generating Data:Bernoulli Binary Generator Modulation:QPSK Modulator Channel:Rayleigh Fading and AWGN Equalizer:LMS based Equalizer Demodulation:QPSK Demodul
Hi, Can anyone explain answers for the following questions? 1. What is the difference between Total Negative Slack and Worst Negative Slack? 2. Does Synopsis DC do the static timing analysis based on the input slope and output cap info of cells present in the critical path of a design. If so, how does it calculate the timing of a (...)
When I design the module, do I also need to simulate my design? Or do I just only need to design the schematic & PCB layout? If you design something based on the chip manufacturers application note, but with modifications to the layout, it's a good idea to do some EM analysis of your layout. This will allow y
Hello Friends, In my understanding asynchrouns or exclusive clocks are those which do not communicate with each other and can be set those clocks in false path. But in PrimeTime command "set_clock_groups" have two switchs "-logically_exclusive " and "-asynchronous" . Could anyone explain what is difference between those two clock groups and how
The circuits without a current path for the OP input current can be sorted out from further analysis, I think. They don't represent working OP configurations. Thevenins theorem applies to linear networks and has in so far limited significance for OP circuits. E.g. the floating OP input in three of the circuits will drive the OP into saturation a