30 Threads found on edaboard.com: Path Based Analysis
Hardware or Software?
I often do path analysis for software, goes something like this.
ASIC Design Methodologies and Tools (Digital) :: 09.06.2010 19:32 :: wassabi :: Replies: 2 :: Views: 1635
I dont think u can modify the netlist in PT.
U can only analyze in PT and make the changes going back to any backend tool like ICC, talus or soc encounter.
And after doing the change select the path and do a path based analysis in PT ans finalize.
Hope it helped.....
ASIC Design Methodologies and Tools (Digital) :: 13.02.2012 01:23 :: pavanks :: Replies: 6 :: Views: 1160
if you are doing ASIC design, sure the synthesis tools and layout tools will list the worst slack path based on the constraints you feed into the tools.
if you are doing full customer, you have to run simulation to know how critical the path is regarding you expectation.
in the case you want to mannually calculate delay for some (...)
ASIC Design Methodologies and Tools (Digital) :: 26.05.2004 01:07 :: gerade :: Replies: 5 :: Views: 2730
As i understand the whole concept of STA is to analyse all the timing paths with respect to one clock cycle(exception of multicycle path).Then how are latch based designs analysed?
Also why is it suggested that the latches should be avoided as far as possible.
ASIC Design Methodologies and Tools (Digital) :: 17.12.2004 01:07 :: mvvijay78 :: Replies: 1 :: Views: 1391
DTA means.. You give a set of test vectors ..for which the simulator caluclates the output values based on available timing information..
ie.. verifying your verilog RTL code by using a testbench and inputs..
You may miss some bugs in ur code if u didnt give a exhaustive or atleast representative set of test vectors..
STA is basically calc
ASIC Design Methodologies and Tools (Digital) :: 21.01.2005 05:52 :: eda_wiz :: Replies: 4 :: Views: 2171
For low freq (1GHz) we are using Q3D to extract the model and proceed to Hspice for SI analysis
For higher freq, HFSS is used to model the package and same Hspice for SI analysis.
Latest trend/development in Ansoft Designer makes it a good alternative for full path simulation i.e. when combining package and MB in one simulation (...)
Electromagnetic Design and Simulation :: 12.10.2005 02:00 :: riz_aj :: Replies: 4 :: Views: 1566
you know what CTS does.. it inserts clock buffers and forms a clock tree such that clock skew from source to all flipflops are same..
If you design is not meeting setup time constraints then additional buffers leads to more complicated violations and similarly for hold violations.. if we have setup violations then this delay in clock path
ASIC Design Methodologies and Tools (Digital) :: 25.05.2006 05:45 :: shankarmit :: Replies: 3 :: Views: 1464
Static timing analysis pertains to calculating path delays without applying any test vectors. The dynamic analysis is related to gate level simulation after inserting delays for each gate this done after synthesis, this needs test vectors to analsys. The path delays varies with applied test vectors. This DTA takes (...)
ASIC Design Methodologies and Tools (Digital) :: 24.01.2007 23:26 :: satyakumar :: Replies: 8 :: Views: 1746
in what process corners u will check for setup and hold violations.
There may questions, how setup check and hold check for the same paths.
ASIC Design Methodologies and Tools (Digital) :: 31.01.2007 04:29 :: au_sun :: Replies: 8 :: Views: 2198
my 2 cents,
Max operating frequency can be found by the Design Timing Critical path based on Timing analysis.
Switching frequency for a cell is basically state driven and this information will be available in your library (state dependant power).
chip design made easy
ASIC Design Methodologies and Tools (Digital) :: 30.11.2008 05:37 :: vlsichipdesigner :: Replies: 1 :: Views: 1115
At Speed test uses two high speed functional clock pulse to test the delay of the combinational lgoic between registers. However, some combinational logic will take more than one cylce to propagate. So the two clock pulses are not enough for these logic.
usually, we will set false paht of these paths. Another way is to use pipelineing to make
ASIC Design Methodologies and Tools (Digital) :: 06.12.2009 03:56 :: owen_li :: Replies: 3 :: Views: 1072
u know the time path model DC/PT will analyze is DFF'S CLOCK TO NEXT DFF'S DATA-IN.
in order to analysis the I/O timing path , assign a true clock or virtual clock for the I/O port, make the I/O analysis based the model like the above(DFF->DFF) .
Of course need use set_input_delay ,set_output_delay (...)
ASIC Design Methodologies and Tools (Digital) :: 13.02.2011 21:56 :: sunjianhuigou :: Replies: 3 :: Views: 1133
In Static Timing analysis (STA) static delays such as gate delay and net delays are considered in each path and these delays are compared against their required maximum and minimum values. Circuit to be analyzed is broken into different timing paths constituting of gates, flip flops and their interconnections. Each timing (...)
ASIC Design Methodologies and Tools (Digital) :: 23.08.2011 02:05 :: ckshivaram :: Replies: 3 :: Views: 351
Cross-connect the inputs (INP1=INN2 , INN1=INP2) , VREF1=VREF2 . Standard feedback. You'll need an additional common mode feedback path to implement a fully differential amplifier. Otherwise the "standard feedback" isn't able to keep both outputs within reasonable bounds.
Analog Circuit Design :: 07.01.2012 10:39 :: FvM :: Replies: 8 :: Views: 724
The answer is simple. Synopsys doesn't want any timing analysis tool in the industry other than Prime-Time. Extreme-DA's tool named "Gold-Time" was one of the competitor for PT, so the acquisition happened.
The same case is with Magma, here Magma was getting better in Analog Simulation side, again acquisition happened
ASIC Design Methodologies and Tools (Digital) :: 11.04.2012 21:11 :: waycorner :: Replies: 3 :: Views: 512
Hi all ,
I am bit confused with the AOCVM calculations done by PT all the synopsys documents , it is mentioned that graph based / path based aocvm derates will be applied starting from the common path in the clock path ( excluding the common clock cell).The common clock path will not be (...)
ASIC Design Methodologies and Tools (Digital) :: 09.07.2012 07:14 :: jaya sree :: Replies: 1 :: Views: 865
The ADS OscPort model for HB analysis is based on the Nyquist stability test critetion, which is described in "Microwave Transistor Amplifiers, analysis and Design, 2nd Ed, G. Gonzalez", chapter 5, section 2. The idea is measuring the close-loop gain and phase to determine the oscillating condition and frequency.
The following is my (...)
RF, Microwave, Antennas and Optics :: 05.07.2003 03:54 :: jon2000 :: Replies: 3 :: Views: 967
The results you can get using S parameters to design oscillators are poor, although they can be used for the first step of the design. This is because the S parameters are linear and small signal parameters by nature. In contrast the behavior that describe an oscillator is nonlinear and large signal based.
To design your VCO you
RF, Microwave, Antennas and Optics :: 03.09.2003 12:35 :: nandopg :: Replies: 29 :: Views: 6456
timing analyzer is the best tool in ISE, you can do static analysis on any path you may also include the asynchronous reset/preset signals
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.08.2005 07:23 :: bibo1978 :: Replies: 7 :: Views: 758
You might want to take a look at:
Pages 23-26 of this presentation give a good summary of current thinking regarding ground planes based on properly done signal analysis and experience.
Controlled impedance for very high frequencies is more difficult on inner layers than on to
PCB Routing Schematic Layout software and Simulation :: 17.09.2005 18:05 :: House_Cat :: Replies: 3 :: Views: 2910
In STA you chek all the paths wether they meet the timming or not........ what you dont check is the functionality of the chip......
In post layout simulation you do a functional simulation with the knowledge of delay values
ASIC Design Methodologies and Tools (Digital) :: 24.08.2006 01:17 :: neo_chip :: Replies: 18 :: Views: 2471
I already had solved the first one by coping link libraries from .synopsys_dc.setup file to .synopsys_pt.setup.
About the second one, I don't want to sepcify one particular timing arc. I need prime time to examin different timing paths and specify the worst delay, but report_timing and report_delay_calculation don't work this way. I'm sti
ASIC Design Methodologies and Tools (Digital) :: 26.08.2008 13:36 :: Mahzad :: Replies: 6 :: Views: 1255
How to design asymmetrical Doherty power amplifier? Using uneven power splitter could be one way. question is how to define which path have more power, main amplifier path or peak amplifier path?
Other way is to use different LDMOS transistor, do you have some suggestion on it?
Besides, how to design three-way doherty power amplifier?
RF, Microwave, Antennas and Optics :: 29.12.2008 03:13 :: slienteyes :: Replies: 6 :: Views: 3483
how does the ICC calculate the EM problems??
go to lef to find the max current density limite,
then ....how to calculate a max density of a certain path??
thanks a lot
Added after 42 minutes:
how does the ICC calculate the EM problems??
go to lef to find th
ASIC Design Methodologies and Tools (Digital) :: 30.10.2009 02:26 :: devop :: Replies: 1 :: Views: 1006
dynamic timing simulation are vector based.
you will define some 1,0 at input ports and change them in testbench..
in static timing simulation vectors are not applied,you have to apply a clock only..
all timing paths in ur designs are checked for timing violations and worst case results are reported ...
flop to flop timings (...)
ASIC Design Methodologies and Tools (Digital) :: 13.12.2009 22:09 :: ankitgarg0312 :: Replies: 1 :: Views: 828
I need your help I am not good at matlab/simulink,
My Problem is about Multipath Rayleigh Channel BER Calculation in Simulin/matlab.
BER Results are for the below cases;
Generating Data:Bernoulli Binary Generator
Channel:Rayleigh Fading and AWGN
Equalizer:LMS based Equalizer
Digital communication :: 05.06.2010 11:46 :: realbaltalyus :: Replies: 7 :: Views: 2077
Can anyone explain answers for the following questions?
1. What is the difference between Total Negative Slack and Worst Negative Slack?
2. Does Synopsis DC do the static timing analysis based on the input slope and output cap info of cells present in the critical path of a design. If so, how does it calculate
ASIC Design Methodologies and Tools (Digital) :: 27.06.2010 18:27 :: randyest :: Replies: 3 :: Views: 2521
When I design the module, do I also need to simulate my design? Or do I just only need to design the schematic & PCB layout?
If you design something based on the chip manufacturers application note, but with modifications to the layout, it's a good idea to do some EM analysis of your layout. This will allow y
RF, Microwave, Antennas and Optics :: 24.06.2011 05:29 :: volker_muehlhaus :: Replies: 9 :: Views: 998
If you are already a PT user, the man page for this command gives very good explanations. I can clarify some of the points where I have got confused during my early working days.
1.) Looks like you are mixing set_false_path and set_clock_groups. Both of them are very different and typically you don't need both at the same time in a certain section
ASIC Design Methodologies and Tools (Digital) :: 01.07.2011 14:24 :: matter :: Replies: 2 :: Views: 3186
The circuits without a current path for the OP input current can be sorted out from further analysis, I think. They don't represent working OP configurations.
Thevenins theorem applies to linear networks and has in so far limited significance for OP circuits. E.g. the floating OP input in three of the circuits will drive the OP into saturation a
Electronic Elementary Questions :: 25.10.2012 03:20 :: FvM :: Replies: 6 :: Views: 998