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I am looking for path based analysis in ASIC hardware. This analysis will be carried out during SI analysis.
Hi, I was trying to look for some information on path based analysis but good explanations are few and far between. Does anyone know of any good videos or any websites where I can find more about this?
Hi, In Advanced OCV, How is Depth calculated in Graph based analysis and path based analysis?? How is Distance calculated in Graph based analysis and path based analysis?? Thanks, Ravi Shankar.
dear all , in the figure what is diff between Block based STA and path based STA i have interview on monday please help me regards venkatesan.K
In path based AOCV the depth is calculated once per timing path. I find the single depth consistently applied to all cells and constant depth applied to nets in the data path. There is no problem correlating depths in data path. I have the launch and capture clocks paths exactly same. I (...)
I dont think u can modify the netlist in PT. U can only analyze in PT and make the changes going back to any backend tool like ICC, talus or soc encounter. And after doing the change select the path and do a path based analysis in PT ans finalize. Hope it helped.....
if you are doing ASIC design, sure the synthesis tools and layout tools will list the worst slack path based on the constraints you feed into the tools. if you are doing full customer, you have to run simulation to know how critical the path is regarding you expectation. in the case you want to mannually calculate delay for some (...)
about STA, in what process corners u will check for setup and hold violations. There may questions, how setup check and hold check for the same paths.
i have a question for all u syntheis how can i insert a driving buffer in a critical path to reduce load or fanout on the net .can it be done in logic synthesis ot it can only be done in physical design.plz answer
hi muthamil, my 2 cents, Max operating frequency can be found by the Design Timing Critical path based on Timing analysis. Switching frequency for a cell is basically state driven and this information will be available in your library (state dependant power). happy designing chip design made easy
I think they should be defined as false paths, since they are clearly crossing clock domains.
Hi Nikhil The local variation does not cancel out as the depth increases. But OCV values are calculated as %, ie. STA would consider de rate factors for signoff. so for the the first cell we de rate the data or clock path, as we go deeper into the logic for every cell data and clock path are de-rated which is over pessimism. so we can say as we
The answer is simple. Synopsys doesn't want any timing analysis tool in the industry other than Prime-Time. Extreme-DA's tool named "Gold-Time" was one of the competitor for PT, so the acquisition happened. The same case is with Magma, here Magma was getting better in Analog Simulation side, again acquisition happened
Hi all , I am bit confused with the AOCVM calculations done by PT all the synopsys documents , it is mentioned that graph based / path based aocvm derates will be applied starting from the common path in the clock path ( excluding the common clock cell).The common clock path will not be (...)
Hello folks, I'm trying to build a homebrew RF receiver board. The receiver is of 2 stage down-converter schema. The first IF SAW filter of that receiver is selected to 190Mhz center frequency. In actual measurement the 2IF output, I found a Spur in middle of receiver passband. With some experiments, I found the spur is due to the harmonic produc
Hello What is CBCM- Charge based capacitence measurement Methods for Mos Devices?. Why do we need it and What are the advantages of using these methods? Thanks BB
I am doing a VCD based Dynamic IR analysis. In the results I find that the ground net current (VSS) loaded is much less than the power net currents combined (VDD). This happens only for vector based vectorless analysis VDD and VSS currents are comparable. What could be the possible reason for this?
Formal and STA can't replace the gate simulation(pre-simulation and post-simulation). 1). Formal tools only check the function of the design. It compare design between the different levels, and don't care the timing. 2). STA tools will check the timing of path which we don't set "flase_path" on. Now in SOC design, there are many clock domai
I want to develop a software which is responsible for monitorin serial port that is used by another program for protocol based analysis.For such a configration, i dont know how to sniff the serial port in WIN32 api platform.. is there anybody who knows these?? thanks in advance...
In one my case, timing check is met in Astro, but have violations in PT. Anyone can tell me why is the same instance's inc-time close to twice in PT's timint-report than Astro's ? :cry: How can I do to approach the timing-reportbetween Astro and PT? Thank you veryvery much!
Try googling for path loss analysis. Somewhere on the net is a path loss analysis for the Mars pathfinder mission that you might find instructive. Excel is the tool I'm seen most used for this, so try filetype:xls at the end Dave
Hi everyone! I am a newbie in both RF & HFSS. Therefore, before I start performing simulation for my new design using HFSS, I tried to verify my setting (in HFSS) by comparing the result obtained with those of SONNET and Momentum (published in a journal paper). It's a simple problem concerning a square spiral inductor. I found out that SONNET ga
PrimeTime is a static timing analyzer (STA). Internally it actually consists of 2 parts: The first part is a "delay calculator". As the name suggests, this engine calculates the delay through a gate or the delay along a wire. In order to calculate these delays, PrimeTime needs an electrical-equivalent model for the physical wire. This is generate
Hi. I have generated a .sdf file using primetime. I want to use the .sdf file in tetramax to generate test pattern for path delay fault. But tetramax gives an error saying that the sdf file has parsing error (missing field) at a certain line. So I check the .sdf file and the error was at the last closing bracket. This is weird because the br
When I synthesize smaller blocks (synthesized to ~200k standard cells) with "synthesize -to_mapped -effort high", everything looks fine. The design gets mapped and many rounds of incremental optimization operation (incr_delay) are done, the final synthesized design is very fast. Now, I synthesize the top level (should synthesize to ~600k standa
Dear Forum, Please let me know what is IBIS AMI model. What is its standard? Any references would be helpful. Thanks, Hayk
The term hall current probe isn't quite clear, I think. I would use it for DC current sensors with open magnetical path, based on hall effect sensors. Like this instrument
i am not aware of any product in the market which would help report path based power. Curious to know why this need?
Hi Please help me, While I tried CTS with the ideal clock, the negative slacks are minimal range i.e -30ps. When i tried to use below command 'set_propagated_clock ' for a single clock module right after the CTS stage(i.e cksynthesis), the higher negative slacks were seen in reg2reg & reg2out paths alone. (i.e -1000ps). T
Hi, As i understand the whole concept of STA is to analyse all the timing paths with respect to one clock cycle(exception of multicycle path).Then how are latch based designs analysed? Also why is it suggested that the latches should be avoided as far as possible. Vicky
DTA means.. You give a set of test vectors ..for which the simulator caluclates the output values based on available timing information.. ie.. verifying your verilog RTL code by using a testbench and inputs.. You may miss some bugs in ur code if u didnt give a exhaustive or atleast representative set of test vectors.. STA is basically calc
For low freq (1GHz) we are using Q3D to extract the model and proceed to Hspice for SI analysis For higher freq, HFSS is used to model the package and same Hspice for SI analysis. Latest trend/development in Ansoft Designer makes it a good alternative for full path simulation i.e. when combining package and MB in one simulation (...)
DSP based SoC Static/Dynamic Timing analysis Using PrimeTime/PowerMill Yaacov Kobrinsky, Eli Ofek DSP Group, Inc Israel ABSTRACT Our DSP based System On a Chip (SoC) is aimed at achieving the best cost-performance for a given silicon area, taking into account memories area size (ROM/RAM), ?glue logic? (ASIC portion), smart power (...)
Hi, Static timing analysis pertains to calculating path delays without applying any test vectors. The dynamic analysis is related to gate level simulation after inserting delays for each gate this done after synthesis, this needs test vectors to analsys. The path delays varies with applied test vectors. This DTA takes (...)
path groups are usually organized by clock group (primetime does this by default). When you have thousands of violations it's much easier having some sort of organization to them
I want to estimate power consumpton of standard cell (logic gate) in Encounter. and I use Simulation based power analysis. From rtl simulation in ncsim, dump .vcd file and load it into Encounter. But in log file, only leakage power has a value, the values of switch power and internal power are zero. I'm confused below log file from Encount
At Speed test uses two high speed functional clock pulse to test the delay of the combinational lgoic between registers. However, some combinational logic will take more than one cylce to propagate. So the two clock pulses are not enough for these logic. usually, we will set false paht of these paths. Another way is to use pipelineing to make
i want to know how to get the dump file for the simulation-based power analysis , i've tried the VCD file but it gave me error :"invalid net toggle probability "-1" , i am using SOC encounter
Hi All, So I came across an interview question: How will you time the input/output path in STA ? Found the answer here: Static Timing analysis | Chip Design Articles I understand what the answer is talking about. BUT, I still don't understand w
Hi , I have a design which has many FIFOs in it. I'm running SPY Glass CDC analysis on it. What I found it report is that Spy Glass is not able to detect the FIFO architecture and generates lots of Error / Warnings like "Data hold check:FAILED" Ac_cdc01a. for the wr and rd pointer flops. It also shouts for underflow/ overflow. But my design uses
In Static Timing analysis (STA) static delays such as gate delay and net delays are considered in each path and these delays are compared against their required maximum and minimum values. Circuit to be analyzed is broken into different timing paths constituting of gates, flip flops and their interconnections. Each timing (...)
Cross-connect the inputs (INP1=INN2 , INN1=INP2) , VREF1=VREF2 . Standard feedback. You'll need an additional common mode feedback path to implement a fully differential amplifier. Otherwise the "standard feedback" isn't able to keep both outputs within reasonable bounds.
what is meant by time based power or power/time ? what happens in time based power analysis. can you please explain time based power with example.
This program is written to provide an ease in the quasi-static analysis/synthesis of SYMMETRIC CPS lines based on conformal mapping method. It is able to take care the finite thickness of the dielectric used and provides the option of including the effect of metallization thickness.
Hi This web-based advanced course on VLSI system design has evolved from the lecture notes and the additional material used by Prof. Daniel Mlynek and Prof. Yusuf Leblebici in their senior-year course offerings at the Swiss Federal Intitute of Technology - Lausanne, over the past several years. The aim of the course series is to present a unifie
Time domain reflectometry works quite well, but implementing it is diifficult and expensive. If you have a digital storage oscilliscope, a fast pulse generator and a calculator you should be able to get a reasonable result. However, if the cable is really long, you will need to know its velocity factor. An easier solution is to use your brain! C
SIMetrix OS Win 95/98/NT Description: SIMetrix is a SPICE based analog simulator, schematic editor and waveform analyser all integrated in one executable.
Of course the lib path to your model library must be set into pspice. See the following topic. One had the same problem some weeks ago :
are there anybody working on DVB? I'm trying to design sth. related to DVB Transport Stream analysis and Demultiplexing. I'd like to talk with some expierenced guys here on this topic. Any help is appreciated. Thx. Please send private message to me or contact me with my
Hi Signs - free gate-level logic synthesis, analysis and simulation based on a VHDL subset. 1. -> t tnx