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30 Threads found on edaboard.com: Path Group
Hi All, While doing timing analysis, I have a different path group as "reg2reg_temp.2234" instead of "reg2reg" path group. The path group is supposed to be reg2reg right? Why this change? Is there anything else I can do to change this? And in timing (...)
hi, If I want to do static timing analysis of my design having MBIST controller I need to consider the whole MBIST circuitry for STA or only those parts of MBIST where my functional path goes through ?? In case of MBIST only MBIST collar will come in design functional path so according to me only MBIST collar has to be considered for doing STA ?
Hi I am having setup slack after post Route stage. I decided o manually upsize the cells.. But is it possible to upsize a particular cell and check the timing for that path alone? and Still problem exists.. I planned to go for grouping the cells or pipelining.. how to group the cells? any command to do that? thanks
How to analyze a timing path for path group reg to reg?
Hello, First of all, If you want to cover critical path, you have to use path Delay testing. Critical path are not covered by SA and Transition testing. Should you have generated path delay patterns by providing the Critical paths? 1. PI means Primary Inputs. Scan IN, Clock, Scan enable are PIs. So it (...)
Hi All, I am using Xilinx's Vivado 2013.3 for generating the *.bin file. There are a lot asynchronous paths in my design. for example if I have grouped the signals like : # in CLK1 domain set group1 ; set group1 ; set group1 ; # in CLK2 domain set group2 [get_cells {sig_
I guess if ur keeping the logic together close enough the tool might try to put buffers in the common path. Also the CG cells placement matters here. If u have to split the logic group to two u can make two branches of CTS. This might also help.
i am not sure at which stage do you refer this question for synthesis, placement, optimization etc.. But anyways at either stage this is important and really helps in closing the timing for a specific design. Basically from my understanding and experience so far EDA tools work better under a path group structure. Ideally under the hood all thes
hai friends i am using encounter for PnR can anybody say , what does the command returns report_timing -collection i am confused whether it returns only a single path or a group of paths thank you
When DC do optimization, it will give more effort(such as run time) to path group with bigger weight. By default, all the path are given the same default weight value.
Hi everyone, I am a learner of encounter (cadence) and meet the setup violation on the inclkSrc2reg group, which is shown as follows: path 1: VIOLATED Setup Check with Pin \DFF_1048/Q_reg /CLK Endpoint: \DFF_1048/Q_reg /D (^) checked with leading edge of 'CK' Beginpoint: g35 (v) triggered by leading edge of 'CK' (...)
hi, answer to these questions plz 1. how to know the datapath and clock path from timing reports... 2. any script for macro placement . can i group macro according to their sdf file i dint see which clock is given to which macro...how can i know
Hi Seems by definition: local skew is the skew between any two flops that have a path between them global skew on the other hand is the skew between any two flops on the same clock group even if they donot talk to each other. Its seen that EDA tools work on optimizing global skew and not local skew. My question: Why don't ED
below is path : Startpoint: TST_TARG_sms_early_resetb (input port clocked by SCLK) Endpoint: vl_sms_sblk_scb_proc_1_sms_1_stp/U_sblk_scb_proc_1_adg/t_data_2_reg_1_ (rising edge-triggered flip-flop clocked by SCLK) path group: io_to_flop path Type: max Point (...)
Yes, dc_compiler will focus on paths that are at the critical range value or less. The weight option is also used to provide priority.
Hi Guys, I am new to RC synthesis Tool. While doing synth -to_map, RC dumps the global estimated target slack as : ======== Cost group 'abc1' target slack: 59 ps Target path end-point (Pin: top/abc/abc1/dataram_rdata_lat_reg_03/d) Warning : Possible timing problems have been detected in this design. : The design is 't
report_timing shows the most critical path (it may show the most critical path for each clock group) critical path is defined as worst negative slack, which is the difference between data required and arrival time. When you time with latchs, time borrowing may happen and your required and arrival times will be the same (...)
Thank for a link. I will need to clarify my need, that is to use bindkey to change a selected layer path already in layout database . For instance : I select layer(s) metal 1 path then press button "2". Selected layer(s) metal1 will change to metal 2. thank in advance.
hi a little help needed i want some good ieee papers and other good material on: comparison between wimax models on the basis of path loses,models are to be used in matlab are: okumura model,ericson model and stanford university model. can anyone provide a good link to any web where i can find these models and all the basic theory.
to get the reg2reg timing, 1. set_false_paths -from set_false_paths -to 2. use group_path and group all inputs and outputs (except input & output clocks) into one IO_pathS group. now it shows reg2reg as one group and io paths as (...)
Hi, Query1: I have done CTS and after that I have got two report one clock skew report and one timing report. Now there are some clock path group whose Global skew is bad and also I can also see timing violation for the same clock path group is quite high. So should I try to debug the timing report and try to see how (...)
To add skew to a particular FF or a group of FFs, all you need to do is add buffers in the clk path.. but where you add the clks is the point.. if you want to add skew to a particular FF, then add the buffer to the leaf of the clock which is only supplying clk to that FF. on the other hand if you want to add the skew to a set of FFs connected by a
path groups are usually organized by clock group (primetime does this by default). When you have thousands of violations it's much easier having some sort of organization to them
Startpoint: rst_n (input port) Endpoint: v_data_array_reg (rising edge-triggered flip-flop clocked by clk) path group: clk path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ scale_8_5_gai ForQA cb35os142_max P
Please reference the following for the next group of questions Startpoint: fifo_rd_pd_reg_16_ (rising edge-triggered flip-flop clocked by my_clock) Endpoint: we_bank_0_reg_2_ (rising edge-triggered flip-flop clocked by my_clock) path group: my_group path Type: max (...)
Hi buts101, Attach a LED with LDR and cover the LED and LDR so tht only reflected light falls on LDR. For more about path following robot, see my book MY EXPERIENCE IN AUTONOMOUS ROBOTICS It is a free book. You can get it from yahoo group-booksbybibin Bibin John
In general, the more bits per symbol, the more critical distortion and noise in the path between the modems become. FSK is more tolerant of group delay variations across the frequency range used. PSK and QPSK is more tolerant of noise. If you are using your own set of wires between the modems you can use any mode. If you are going through the
there is a timing report by synopsys primetime. ************************************************************* Startpoint: xt_aclk (clock source 'xt_aclk') Endpoint: ad_a_ad (output port clocked by xt_aclk) path group: xt_aclk path Type: max Point Incr path (...)
Startpoint: clk (clock source 'clk') Endpoint: ram (rising edge-triggered flip-flop clocked by clk) path group: clk path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ xx xxx xx Point (...)
hi, i came to know that u can get those s/w from anonymous login also....but when i tried that "ls" command did not work!!! may they are hiding those s/ws. i hope many in our group knows the path and name of the softwares in that ftp site. i request him/her sincerely to provide those links for the use of students like us. pls consider this since