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Hi guys, Looking for good document/book on how to decide a good pcb stackup. -kib
Hi Can anyone give me a typical pcb stackup for an 8 layer board of 1.6mm? I would like each individual layer thickness e.g. copper, prepeg etc. Thanks Jon
How to design a pcb stackup?
How do I choose which layers will be core or prepreg in my pcb stackup? I'm going to use 6 copper layers.
I would need advice in deciding what pcb stackup to use for my project. I have two voltages (5V and 3.3V) and some LVDS (differential signals). Is this a good stackup? Layer 1: Components, small routing near ICs. I have also some signals that need to be 100 ohm (differential impedance). These I would like to route on the top layer (...)
I'm Looking For You'r Opinion About The Ideal pcb stackup Layers For Multilayer High Speed Design. i Would like To use At Least Half Of The Layers For Signals, But I Would Also Would Like To Keep Clock Layer Isolated, I also Would Preffer To Locate Voltage Plane Near To GND Layer. I'll Apretiate You'r Contribution !
Hi, The things which should concern you in high speed pcb design are signal integrity, EMI, EMC. A lot of books are available for download in e-books upload/download section. Here is one , look for other related stuff. /pisoiu
Hello All, I have small Project and I need some help from you guys My project is to design High speed pcb to connect CPU to couple of external memories. If you were me how could you defines: - pcb stackup (2,4,6,8 layers!!!). - Trace design based on I/O driver!!! how!! what!!. - pcb terminations for these signals: (...)
Hello, Recently I received a pcb stackup design from my client that I feel the design is very odd, but I'm not sure whether the design can be fabricated or not? please refer in the following enquiries: 1) Client intended to use 3 layers(1 copper foil +1 core with 1oz of copper at top and bottom) to form a lamination prior to generate the buri
You can see the details from the following link:
Hello friends, I've designed a lot of pcbs over years, including some simple multilayer (4-6 layers), but never faced problems to dig deep into stacking fabric (let manufacturer handle). But now we have to make a pcb with some diff. sensitive traces @100...200Mbps, so we need to calculate impedances involved. I'll summarize the questions for kin
Hi, im using a roger material RO4350B for pcb design.Can someone tell me how to properly specify the pcb material in ADS 2009. Thanks
How to select impedance during pcb stackup? Thanks!
Hi All, Have you ever used any "FREE", or "OPEN SOURCE" tool for creating & editing the pcb Stack up ? I am aware of tools such as Polar instruments, but they are licensed tools. Any help will be of great use.
Can LVDS be used for say traveling 1 foot across a cable to another pcb or should it only be used within a signal pcb or pcb stackup?
Hi everyone, I was wondering which tool is best for model pcb stack up and able to do simulation on the model. We are talking about multiple layer. I would like to be able to change the dielectric constant and dissipate factor for core a on each layer. An example of layout is: Plane Gnd Core Signal Cu pre-preg plane Gnd I want to f
Hi Michael, I would suggest you to read following topics on pcb Stack Design: In pcb design you use even numbers of pcb layers. Although you can use separate layer for every voltage and ground but this approach will increase cost of the pcb manufacturing. These days embedded processo
I'm looking to find a way or any info to do a 24 layers pcb with a thickness of 0.065" (65mil). Any tools or software to confirm if it's possible to acheive this ?
The pcb designer's bible ... Coombs' Printed Circuits Handbook Try Amazon Good starting point for material etc.
A table you can refer to pin_density signal_layer pcb layer >1.0 2 2 0.6-1.0 2 4 0.4-0.6 4 6 0.3-0.4 4 8 0.2-0.3 6 10 <0.2 8 >14
It sounds like you are in over your head with this design. I don't mean that as an insult; however, you seem not to understand the many factors that drive board stackup. First, to prevent board warpage and twist, it is usually a good idea to keep the number of planes even and the number of signal layers even. They are arranged about the centra
The number of layers in a pcb design depends on the design complexity and also maximum thickness you can have .
you can mesure your own pcb dielectric using this way: 1-obtain the 2 layer pcbof area A 2- connect two wire in two side of pcb 3-using LCR meter and mesure the value of capacitance 4- using the formula of parrallel plate capasitor C=e0erA/d
Hello I would like some recommendation from users on an econimical RF simulator for pcb layout. I have a requirement to simulate / optimise / match a F or SMA connector input to the input of MOPLL device for satellite 900-2200MHz but I have not ever done this before. The mechanical constraints will mean a distance from centre pin of conne
Hi all, How can bow and twist of pcb can be prevented ? Thanks.
i am using 62 mil pcb thickness and 1 oz copper on each layer can u tell me what should be the thickness of substrate inbetween the layers. thanks in advance
Iam very new to pcb design & i want to know, is there any rule for pcb layer stackup, like, is it necessary for a signal layers need an adjacent plane layer etc.
Do you have an Idea on how pcb design company charge their customers? what are the basis? example, board size, number of components, density of components with respect to size, SMT...
Hello All, I just want some help for this problem if u can pls! I want to do high speed pcb design for a processor connected into two external memory. and maybe i need to use clock for sync. I want to know this 1- pcb stackup 2- terminations stratagy ( clock - address bus- reset) 3- trace design. (assume I have the input and output (...)
Dear all, If a pcb board, 2 mils of core with 1oz copper at the top and bottom, is it a good board to be fabricated? will it be caused warpage during etching for inner layer process? if yes, what is the real factor caused to warpage? How to solve this problems? For my understanding, if the thickness of copper is greater than thickness of core
anybody can give me websites on different types of layers for different purposes
i don't know anything abt 8 layer board so wat am i suppose to ask my supervisor abt the transfer to pcb info?? can anybody tell me....if i do auto-routing hw long will i be able to finish???
Hi Does anyone have any idea of the cost of using blind vias on a pcb? cheers Jon
Hi all, i have MX27 chip, MAPBGA-404, intend to route on 8 layers board any recommendation on stuff like ...address and data to be on which layers? and layer stackup? Thanks
The stackup is made of a central core. then above and below prepeg layers are added I think. I think it is the way of manufacturing pcbs. Technology Manufacturing related.
Thanks Guys. I got the PDFs and the book. From what i have read so far it seems like a fair amount of live experimentation with the pcb is required to achieve low-Z decoupling over the whole range of frequencies that can cause VCC noise and EMI. In particular, we cant to make sure that the poles of the cap impedance do not coincide which might caus
Hi I am designing an 8 layer board with the following stackup 1 signal 2 ground 3 signal 4 power 5 power 6 signal 7 ground 8 signal I need to have the signal layer as 50 ohmn impedance. How do I find out what the pcb manufacturer will use for the thickness of the layers so that I can calculate my track widths and spacing to give
In general, keep your stackup symmetrical from the middle of the stackup, this will reduce bow and twist. If possible put a power and ground plane together, this will act as a capacitor. For stackup dimensions you have to contact the pcb manufacturer, he can tell you wich materials (and thicknesses) are on stock. You (...)
Hi, I also wanted to ask a question about core/prepreg stuff. If I design a several layer pcb can I define the stack in whatever way I want? I mean, is the order: top-prepreg-mid1-core-mid2-prepreg-bottom equivalent to: top-core-mid1-prepreg-mid2-core-bottom ? Can the controlled impedance tracks be made between the copper layers with cor
I am doing SI simulation using HSPICE. the topology is as follows. Driver (ASIC) --> pcb trace --> Receier (ASIC). Total number of layers in pcb: 12 I need to use stripline for simulation. Right now i took inner 4 layers (GND, SIGNAL, SIGNAL, GND) only to model the pcb trace. I am using field solver to model the trace. Is it (...)
Hi, everyone. I have a question about the multi-layer pcb for RF passives. Right now I ran out of the space to put my microstrip power dividers and hybrids on a two layer pcb design. And I am thinking whether I can put the power divider into the other layer which is sandwiched by two ground plane as a stripline structure, and use PTH to connect
The current is only flowing at the via outside due to the skin effect Vias are of course acting as a discontinuity for a transmission line. Depending on the pcb stackup and design rules, they act either capacitive or inductive. The via dimensions can be tuned to minimum reflection factor, at least i
Hi Friends, Please guide me to understanding of EMI / EMC issues related to pcb layout design. what are the measures need to take care of in the layout. Thanks in Advance. Manikandan
pcb SI is initiated from inside the pcb editor program. Its' a pule down, but it doesn't actually say "pcb SI". From the pcb editor, you have to set up all the nets, power/grounds, stackup, components, etc, then initiate the program, and it will then launch sig explorer with the extracted topology (...)
Hi pcb Friends, What are the guideline we have to implement in this pcb. In this board i used Blackfin532 IC 176pTQFP, Sdram,Flash,ethernet controller ,audio codec,USb host ,Magnetics,Lan and some more Pheripherals. I planned to do in 6 layer can any one suggest spacing rules for this and also good stackup. impedance 90 ohms and (...)
I have 6-layers stackup: -----SIGNAL -----GND -----SIGNAL -----SIGNAL -----VCC -----SIGNAL the board is for PCI express cards, with differential lines, that must be impedance controlled to 100 Ohm differential. For top layer and layer 3, the reference layer is the GND layer and I can use the microstrip model for calculationg the impedan
Hi pcb newbie`s, To become a professional in pcb one should have Good knowledge on the following points : 1.Drawing Schematics in different tools/pkgs (ALtium,PADS, Allegro,..etc) 2.Understanding the errors and procedure of rectifications 3.Board Details understanding 4.Datasheet understanding for footprint creation 5.Footprint Cr
Hi there, I need SATA pcb layouts in GERBER, PDF or any CAD software. I am intending to add SATA HDD support to my OMAP via USB 2.0 interface. I am planning to use JM20339, but the manufacturer lacks of the pcb guidelines. I would be thankful if you send/point to me any source of information about the specifics of the SATA design. Than
I'm doing a pcb design with a Microprocessor & few DDR2 667MHz. The recommended layer stack up was TOP, GND, INN1, INN2, VCC, BOTTOM. Can you recommend thickness of the board(prepreg and conductor layers? Impedances from the board are 50 & 100ohms. Also what will be the drill pairs from my board. I'll be using blind & buried vias. Thanks
I added all the layer's thickness together and found it is less than 0.06 inch Yes, thats's reasonable, it's a pretty standard pcb stackup. What's your question with it? For tolerances, the manufaturer will refer to IPC standards. You can expect a tolerance of about 10% for finished thickness. If you need higher accuracy, e.g.