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This question is not pertaining to any datasheet but philosophy of PLL. I was referring to the link . I found the following statement "When the PLL, phase locked loop, is in lock a steady state error voltage is produced. By using an ampli
The circuit makes no sense. Why would you connect L and C in series with the fan motor? A possible capacitor application would be for a "capacitor-run" single phase motor with two windings.
Hi, I don´t think it makes sense to perform any calculation on unspecified sample values. Some do voltage readings with 100Msample/s on a clean DC reference voltage. Some do 15 minute average readings on 3 phase AC power grid voltage. Completely different data without I could upload data of 20ms RMS mains AC voltage readings. You will see a
I've got a LT isolated, closed loop, flyback demo board straight out of the box and am looking at the gain/phase plots etc. My question is about the phase. Do I interpret the phase margin here as about 55deg or 235deg. Looking at other examples I think it must be the latter because of the low frequency phase. Seams weird (...)
The Laplace transform is used for the VCO transfer function. Such a function is defined for linear conditions only. Therefore, it applies to the PLL under locked condition only - and this is the key for an answer to your question: The PLL linear transfer function - hence, also the VCO function - is defined in the phase domain only. And for the vol
Hello, Please can you confirm that the use of a Unidirectional Current sense Transformer (CST) as shown on the first page of the UCC28950 (phase shift full bridge converter) datasheet is totally wrong? (It is a phase Shift Full Bridge converter and the Current sense Transformer should instead be a Bidirectional Current (...)
i am measuring 3 phase voltage using pic micro , for that i am scalling 440v to 1.5v using resister 2.2meg and 6.8k. every thing works fine i can see the 3 phase voltage on lcd but if i disconnect 1 phase in the 3 core wire i can see some leakage voltage present the line tester glows bot very little current if i touch in hand no shock. my (...)
@schmitt in my experience when high frequency high voltage is generated by 3 phase drive it create strong electromagnetic field due this i thought may performance of hall sensor is get very. PWM with high dv/dt at current carrying conductor may affect the performance of the current sensor due to capacitive coupling. To reduce capaci
here is ltspice simulation of circuit grid tie inverter, ltspice is free. You do not need to always sense the mains, you just have to know when is the zero crossing, then you shovel in your sinusoidal current in phase with it. You need to have a dc supply of voltage higher than the mains peak, so that you can always shovel power into the main
Can you tell me how such a filter can compensate for leading and lagging actions of the input signals ? No, because the statement doesn't make sense. A "lag-lead" loop filter (lag-lead because the pole comes before the zero) acts as a low-pass filter without reducing the loop phase margin too much. It's necessary because the VCO
Hi guys, i am using micro controller arduino uno to produce 3 phase PWM pulses by using DDS method available online. the PWM pulses will be fed into a ....... your description didnt have any info on the feedback pulses from bldc.(hal sensor) did you sense it and control the bldc? [SIZE=1
Yes, but I'm not sure what you are trying to achieve. The circuit uses phase control so either you have to use the PWM very slowly, like an on/off switch to control the average output power to the load or you have to synchronize the PWM to the zero crossing of the AC and set the trigger points within a single cycle of the AC. You do not show
The S-parameters obtained from the simulation do not make any sense (Figure2). How can you know? You have magnitude only s-parameters, phase is unknown. Thus you can't predict if superimposing signals at multiple input ports will increase or decrease the magnitude at a certain frequency. Presumed you are modelling a linear sy
The term "lock-in amplifier" doesn't exactly match the application, but a complex impedance measurement with phase sensistive rectifier is perfectly suited. In addition a measurement circuit that is insensitive to cable capacitances, e.g. voltage source/current sense. That's how all AC impedance (LCR) meters work.
Hello, We are using the ML4425 3 phase inverter controller IC for driving a BLDC for water pumps which form an irrigation system for Tulip Fields. All we need is for the pump motor to spin at 8000 RPM. We will bypass the ML4425?s current sense by grounding the ?Isense? pin?we will then control the current which feeds the (...)
What is the center frequency, required bandwidth (given certain VSWR), available space, maximum attenuation, input power, phase delay, preferred technology, etc?
Hi All, I wanted to use an oamp and measure the phase between voltage and current. I need to view this on an oscilloscope. I wanted to measure the phase shift between V & I circuit with an inductor load for a 100Khz sinusoidal signal input. At present I used a current sense method by putting a 1 ohm resistor at the output of a (...)
Hi to all. I hope this explanation makes sense. I'm using a pic24fj256ga104 to control an AC motor using a triac. Speed control is achieved by varying the firing of the triac with respect to the zero crossing. phase control I think it called. It is all working as expected. The issue I have is I'm sure I've made a "mountain out of a moll hi
A shunt won't be connected across the phase rather then in series with the load (similar to a CT). So your observations seems to be wrong. A single-phase energy meter would use either a shunt or CT for current measurement, but not both. Also a voltage divider to sense the phase voltage and some kind of power supply, e.g. (...)
I don't believe that the phase response is correct. It's impossible to achieve. A physical plausible phase response is e.g. shown in Figure 22 of the TPS54331 datasheet. In contrast to the plotted response, there will be an additional phase lag caused by the average PWM modulator delay.
89975 In the attached circuit is driving capacitance load and current of 5mA. sense and vdd_1v8 pins are shorted outside. To check stability and see loop gain and phase response for this circuit, where exactly i need to break loop?
I was plotting gamma in multical and the plot y-axis label reads "Relative phase Constant and Loss (dB/cm). Does anyone know if the units apply for both the beta and alpha portions of gamma? It makes sense to me that the units of loss be given in dB/cm but not those of beta. I was expecting beta to be in rad/m. Any help will be greatly apprecia
Thanks for reply, I am just interested for i/p connection of three phase for detection. O/p ckt and Resistor values are different. So, please tell me is it work?
I was also thinking of losses first. However, chuckeys explanation of complex k factor due to the distributed nature of the inductors makes perfect sense to me. The physical size will lead to some small phase offset between the inductors -> complex k.
maybe you could rephrase your question, as it does not make any sense to me. If you have a vco that has a tuning range of 0 to 3 volts, and you connect it to a modern PLL chip with a charge pump output, with that PLL chip running off of say 3.3 V DC, then the PLL phase detector will automatically put out a voltage between zero and 3 volts to try
I'd use the cross() calculator function looking for the right-sense zero crossings, and do the arithmetic to turn time into degrees. Timebase being the fundamental period of whichever phase you call the master reference.
I don't understand the sense of accuracy problems. There are different ways to drive a triac. Diac driver circuits are good for simple phase angle control circuits (e.g. light dimmers). A diac can easily provide high pulse current and drive even triacs that need high gate currents. DC drive is possible as well, mostly using sensitive triacs.
Hi, I wish to protect the power MOSFETs in a 3-phase inverter from short-circuit current or overcurrent. I will monitor the dc-link current using a current sense resistor (R1 in attached figure). Besides aluminium electrolytic capacitors (C1~C4), I would like to add a 2.2uF metallised polypropylene (MKP) capacitor as shown in the figure as C5. H
Assuing you mean the clock frequency: 1. If the device has an internal clock, the phase will change and gain needed to sustain oscillation will drop as frequency increases. At some frequency it will reach the point where the oscillator will nor start or run reliably. 2. Inside the microcontroller there will be thousands or millions of gates, each
I find the stability analysis (stb) tool convenient yet untrustworthy. If there is anything "funny" it will give you results that don't make sense without saying why. Always look at the simple gain / phase frequency analysis plot if you have any doubt at all about reasonableness.
In your question, the sense is missing. At ~400 MHz, you can design your local oscillator for instance as a quartz-crystal driven oscillator and a multiplier to the desired frequency. Or, you can use a VCO with the phase-locking circuit for it. To make a PLO as it is known, you must also make a quartz-crystal driven oscillator and a frequency mul
A and K could be current sense resistor P1 and P ?? G represent Gate U represent Upper basically GU & GU(BAR) would be signal to gate and they would be 180 out of phase. I think you can short A and K p1 and P
Looks rather strange. The gain drops with app. 20 dB/dec and the phase goes rapidly down (rather than to approach 90 deg.) . Something must be wrong in your simulation setup.
Your question does not make too much sense. If you have one ideal carrier, modulated by another ideal modulating tone, the phase NOISE is zero. There is no random noise on the signal. Try to imagine your modulated signal in the frequency domain. You are very much modulating the carrier with a large angle modulation. Your spectrum will look l
Hi, as the divider has to cover very wide freq range(0-2G), I want to use true-single-phase structure to design the DFF. I am not quite familiar with this. It works well for 2G with 0.18um process. Can it support as low as several MHz or KHz? Thanks!
Hi All, I am now designing a dc to ac buck converter . There is a comparator in a voltage loop. I am now getting a severe phase delay when I tried to sense the output voltage and do the subtraction with Vref. Is it possible that the delay is mainly contributed by the comparator? Thank you very much,
Hi all, Couple of questions I'm hoping someone can give me a hand with. I'm implementing a motor controller, basically three cascaded control loops to control position, velocity and current of an electromechanical actuator. Motor is 3 phase brushless driven by 4 quad operation pwm. First question, I am sensing current using a sense resistor a
you can use Hall Sensors. Three Hall sensor would be enough to sense the position of 3 phase motor for control purpse. Umesh.
Depents upon target process, 2.4GHz may be another good choice. Maight want to check phase noise at 1MHz offset.
For a circuit without feedback If plotting its Bode Diagram: GAIN=20log(out/in), phase Is there also a phase margin here? If it is, what does this phase margin mean? (As in a feedback loop, the phase margin of the loop gain means the stability problem)
how to model the motor to hall sensor then to ic Hall sensor input ? I mean , when we design a brushless 3 phase motor controller , all we know is that 1 : sense the hall sensor input , U,V,W 2: send the UVW signal to matrix control to decode and re-arrange it to driver the top arm & bottom arm of driver for motor . 3 . when the motor inducto
If they bill it by line, then yes. At my house we get billed by our single phase power line. It would make sense that if you had 3 phases you would get billed for each phase. If one of the CTs failed it would read 0 current, so they would think you weren't using one of the phases until they discovered that (...)
What does one mean by differential inductor , DCR and resistor current sensing(in a 6 phase buck reg)? What is meaning of light load efficieny? VID ? APA Adaptive phase alignment modulation scheme? APP Active pulse positioning? Integrated open sense line protection?
There will be amplitudes and phase associated with the harmonics. Usually for the sake of conservation of energy the higher frequencies contain lower amplitudes. Each harmonic is a sinusoidal oscillation in time domain with different phases. If you simply superimpose them on one another you will get the actual waveform whose harmonics you found out
Kouly is right, if you are using it in an digital comms system and good BER is critical then the stated phase noise is probably a little high at 100kHz offset figures of -100dBc/Hz or better is good and desirable. Shogun
most oft published papers use S domain linaer analysis for phase noise analysis of the PLL khouly
What are you trying to do?? What is phase delay between those two clocks?? please provide more details
Hi! I want to measure the current of a single phase motor. which sensor should i use? I read about current transformers but i cannot understand how to use them. Can you help me. Thanx
hi all, Can you pls tell me how to measure the phase noise contributed from the PFD. What do you mean by noise in PFD wrt Jitter. I got the phase noise curve of the pfd+cp which is like a varyoung curve over the relative freq. of 1Hz to 10MHz. But i could not make any sense out of it interms of jitter. Can any body explain? (...)
Hello, I have a question.Static phase error spec makes sense only in the PLL locked condition i.e CP output voltage in locked condition or should it be checked @ 0 and Max CP output voltage?Please comment in this regard... Regards, Ashish.