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9 Threads found on edaboard.com: Physical Design Using Astro
I'm trying to lay out a design with two large modules connected by some simple glue logic. I want the modules to be laid out physically as two separate bodies on the chip. I know the placed-and-routed area of each individual module, and I'm using that for two plan groups (see below). My current flow: design Compiler (...)
what is the physical design inputs?
Hi all, I have a basic doubt. I doing physical design of a block for practice using astro for the first time. When I checked the summary after the CTS, I found that the core area occupied by the 21k standard cells is (1210 * 1214). Now I am unale to figure out whether this value is in (milli*milli) or (micr*micro). Is (...)
PD: at least 5 yrs experience in physical design using Magma blastfusion, Apollo/astro or SOC encounter. Verification Engineer: at least 5 yrs experiencein asic verification, using specman, vera, or systemverilog/systemC. Familiar with PCI-Express, USB 2.0 etc. US work permission required. contact:
Can anyone throw some light on the whole galaxy design flow? I have started using astro and physical Compiler recently.. would like to know where these fit in the Galaxy flow? Can anyone share the user guides for physical compiler from psyn1 and psyn2 folder... it would be of great help
we need a verification engineer urgently using specman tools and physical design engineer (first encounter, calibre or astro/apollo). Any one interested, pls. leave you contact info or send me email at bullyaya@yahoo.com you must have US working permission first. Senior physical (...)
Paul Zimmer Specializing in: Static Timing using Synopsys PrimeTime Synthesis using Synopsys design Compiler RTL coding using Verilog Static Timing using IBM Einstimer physical design using Synopsys astro
I have a design which using astro to do APR.... In the physical Verification state, astro check DRC result is no violation. But check DRC in calibre have violation. Can anyone tell me how to fix the DRC violation?
hi tahar, the steps 6,10,11,12,13 are needed only in ASIC flow. You cant learn them with Altera FPGA and Quartus tools. You need process library and very expensive EDA tools for this purpose. eg: Synopys design compiler,physical compiler, astro, StarRC.. Proabaly ur university has a license to these tools .. check them out... the (...)