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33 Threads found on edaboard.com: Pipeline Comparator
Hi, pipeline digital correction solves some offset of comparator, but it can't correct gain error, right? For example, for a 10 bit adc, the first stage is 1.5 bit stage, the idea gain of this stage should be 2, but the actual gain is 1.9. Even with the help of digital correction, it can not correct the gain error? right? How to understand
Hello all; In pipeline ADCs where charge distribution dynamic comparators are used, the design of the different comparators is the same, they are only fed with different references to make them get exercised at different input voltage values.....When applying a ramp to the ADC each comparator exhibits a certain value of (...)
hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline ADC in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-ADC.. I have several questions.. 1) How to choose the value of Vrn and Vrp? 2) How to select (...)
this is a 10bit pipeline adc, it has a front end sampling hold circuit which followed by 8 stages of MDACs, each stage is 1.5bit, the last stage is a 2bit flash adc. but in front end s/h circuit, there is a 1bit comparator, it output to digital error correction, why they use the comparator , how this works in digital correction?
I understand that digital error correction for a pipeline ADC which is based on 1.5 bit per stage is used in order to correct offsets from comparator, opamp, etc. My question is, how does it actually correct this offset? What is the exact mechanism that allows you to be able to tolerate a larger comparator offset just because you have (...)
I don't think the ADC should drive a 50ohm resistor. Maybe, you mean that the ADC should have a 50ohm input termination... Just do a search on the IEEExplore website or google for "pipeline ADC" and you will find tons of references.
Hi all: I am design a 10bits, 50M/s pipeline ADC, but I do not konw how to design a comparator. Would you give me some advices? for example, how to design the pre-amplifier, what's the value of the bandwidth and gain of the pre-amplifier? how to design the latch? I beg your help! thanx!!
There looks to be a lot of glitching in the logic outputs and my first guess would be that you are overclocking the layers of decision logic and catching an unsettled comparator output, or something like that. If this is a pipeline with multiple layers of add & carry, that might add up to more than 30nS setup time if you add in the analog por
our project is to design a 14bit 80M pipeline adc.The first stage is 4bit(1 bit redundancy) followed by 8 stages of 1.5bit/stage.the decision level of 1.5bit/stage is ?Vref/4,which can tolerated ?Vref/4(or ?Vref/2) offset.I dont know how people think up this method. and i dont know what are the first stage decision levels either. Could someone ex
hi there, Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline ADC design? what is the advantage of it compared to other structures?
Hi, there, As is well known, the comparators in the sub-ADCs of a 1.5b/stage pipeline ADC can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks! Added after 16 minutes: AND I also want to know which is the FIRST paper
Dear everyone.. I'm undergraduated students.. my final research project is pipeline ADC.. I finished op amp and comparator.. now I want to start design a switch capacitor circuit.. but I have no idea how to decide the value (capacitance) of capacitor in SHA circuit.. I read it, that the capacitor value will be compared.. so is there an
Thank you so much, guy. Now, I just use early latch signal to my sub-ADC, and the error caused by kick-back noise has almost no effect on my Sha. However, are these methods common in commercial pipeline ADC design? Such as early latch signal, parallel path?
1\in pipeline adc design, we need to maesure SNR\THD\INL\DNL\SFDR,but what parameters in circuit are related to them separately?and if one of them or more don't meet the requirement,how to improve them(such as THD and SFDR)?and what method can be used?pls help me. 2\in sc-cmfb circuit,there are two cap C1 and C2(C1 connected Vo+\Vo- and C2 conne
Hi guys, I have a question with regards to the parameters such as comparator offset, gain, capacitor mismatch etc.. in a given stage of pipeline adc. In general how much variation can you expect for the above paramters in terms of percentage with increase or decrease in temperature and ageing for 0.18um technology. Assume that the adc is working
Hi guys, I would like to know how to make each stage of pipeline behave similarily as close to each other as possible. I mean the multiplication factor of residue in each stage should be nearly same among all stage of pipeline. Its doesnt matter if there are large errors in each stage but the error factors like the comparator offset (...)
in pipeline adc of 2.5bit per stage,what kind of comparator can be used?if i use built-in threshold comparator as in 1.5bit per stage,is that ok?if not,what kind of comparator should i use ?pre-amplify+latched comparator is ok?if i use pre-amplify+latched comparator,then i will have a (...)
can the sar adc be desiged for 40Msps and 12 bit. if not then why . as we can design the 12 bit 40msps pipeline adc easly but not sar adc . please clarify my doubt. regards
high speed ADC 1. pipeline 2. fold 3. flash 300MHz flash A/D can use "switch comparator" use switch Cap .. and clock will do auto zero (cancel offset ...) comparator use "preamp + latch " for high speed signal you cn find many paper talk about this A/D
hi,guys I am confused that why makes addtion of alll stages' digital output can correct the error such as comparator's offset introduced. Expecting your comments, thank you very much. san
It depends on what architectures you chose (pipeline, full-flash, subrange,SAR,etc.), you must specify the one.
how do i define the spec of the comparator used in 1.8V 40MB 10Bit pipeline ADC stage(CMOS process)? like 1.resolution 2.propagation delay one thing that confuses me is, how do i know my comparator is "fast enough"? check Bode plot for BW ,or just run a transient simulation by input a step signal? Added after 17 m
Dear Suhas, I think that it depends on the number of bits you resolve in each stage of the pipeline. Vref/4 would apply to about 2 bits per stage, if I am not wrong. Also, the residue gain is also critical in defining the required offset.
You first model your system from top level to sub would contain...comparators....S/H...m-DAC...dig correction blocks etc....now just write the routines for each of them....this routine basically contain the IP-OP relation-ship of the blocks (in voltage domain)....just like C-prog.... Once this is done you call them in proper manner..
Dear all: I designed a switch-capacitor comparator,which is used in the pipeline ADC. The function of this comparator is right,.but i don't know how to simulate the offset of this comparator. This comparator is Preamplifer+latch with autozero function.Thanks
im not quite sure abt all this testbed(cct) for testing pipeline ADC performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
Now I design dynamic comparator for pipeline ADC. But there are some is my design parameter. Vdd = 3.3V (CM = 1.65V) Vref+ = 1.9 V Vref- = 1.4 V Vin+ - Vin- ; ramp signal from -3.3V to 3.3V 1. This comparater generates 1/4Vref threshold voltage if I design W2/W1=0.25.
that's the spirit of pipeline ADC. if the residue is not amplified after the subtraction, ur next stage need the same accuracy as ur previous stage.
For a flash AD (pipeline AD), I need a reference voltage 1.25V and 1.75V which is connected to sample/Hold circuit (comparator). Because of the clock feedthrough and charge injection of the sampling switch, the reference voltage is changed. So I add a buffer connected opamp to isolate it. The buffer input is i.25 and 1.75(volt). I
Hi fellows This thread interests me very much.. since my final school project it's projecting ADC pipeline (with Flash arquitecture) i want to know if you fellows can give a clue how i can make the digital correction algorithm when i'm joining diferent types of arquitecture, i.e i want to project a pipeline that have more than one arquitecture,
Hello Friends, I am looking for job and simultaneously in the mean time I am planning to design and simulate Flash or pipeline ADC circuits. Please suggest me which is the best option for designing any of these circuits. Also please suggest me study material which will be useful in designing that ADC. Thanks in Advance Rajeev Verma
I am designing a 8bit 100MHz pipeline ADC, and the result puzzled me. The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation? Additions: In this design, there are a S/H circuit, gain stage(include OTAs), dynamic comparator, and bias circuit. How about
please search this forum .. someone provide a Good site have many theis about 100M 10bit pipeline ADC design report